1[
2    {
3        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
4        "EventCode": "0xff",
5        "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
6        "PerPkg": "1",
7        "UMask": "0x20",
8        "Unit": "imc_free_running_0"
9    },
10    {
11        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
12        "EventCode": "0xff",
13        "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
14        "PerPkg": "1",
15        "UMask": "0x10",
16        "Unit": "imc_free_running_0"
17    },
18    {
19        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
20        "EventCode": "0xff",
21        "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
22        "PerPkg": "1",
23        "UMask": "0x30",
24        "Unit": "imc_free_running_0"
25    },
26    {
27        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
28        "EventCode": "0xff",
29        "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
30        "PerPkg": "1",
31        "UMask": "0x20",
32        "Unit": "imc_free_running_1"
33    },
34    {
35        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
36        "EventCode": "0xff",
37        "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
38        "PerPkg": "1",
39        "UMask": "0x10",
40        "Unit": "imc_free_running_1"
41    },
42    {
43        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
44        "EventCode": "0xff",
45        "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
46        "PerPkg": "1",
47        "UMask": "0x30",
48        "Unit": "imc_free_running_1"
49    }
50]
51