1[
2    {
3        "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
4        "EventCode": "0xE6",
5        "EventName": "BACLEARS.ANY",
6        "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
7        "SampleAfterValue": "100003",
8        "UMask": "0x1f"
9    },
10    {
11        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
12        "EventCode": "0xAB",
13        "EventName": "DSB2MITE_SWITCHES.COUNT",
14        "PublicDescription": "Number of DSB to MITE switches.",
15        "SampleAfterValue": "2000003",
16        "UMask": "0x1"
17    },
18    {
19        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
20        "EventCode": "0xAB",
21        "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
22        "PublicDescription": "Cycles DSB to MITE switches caused delay.",
23        "SampleAfterValue": "2000003",
24        "UMask": "0x2"
25    },
26    {
27        "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",
28        "EventCode": "0xAC",
29        "EventName": "DSB_FILL.EXCEED_DSB_LINES",
30        "PublicDescription": "DSB Fill encountered > 3 DSB lines.",
31        "SampleAfterValue": "2000003",
32        "UMask": "0x8"
33    },
34    {
35        "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
36        "EventCode": "0x80",
37        "EventName": "ICACHE.HIT",
38        "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
39        "SampleAfterValue": "2000003",
40        "UMask": "0x1"
41    },
42    {
43        "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",
44        "EventCode": "0x80",
45        "EventName": "ICACHE.IFETCH_STALL",
46        "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.",
47        "SampleAfterValue": "2000003",
48        "UMask": "0x4"
49    },
50    {
51        "BriefDescription": "Instruction cache, streaming buffer and victim cache misses",
52        "EventCode": "0x80",
53        "EventName": "ICACHE.MISSES",
54        "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.",
55        "SampleAfterValue": "200003",
56        "UMask": "0x2"
57    },
58    {
59        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
60        "CounterMask": "4",
61        "EventCode": "0x79",
62        "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
63        "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
64        "SampleAfterValue": "2000003",
65        "UMask": "0x18"
66    },
67    {
68        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
69        "CounterMask": "1",
70        "EventCode": "0x79",
71        "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
72        "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
73        "SampleAfterValue": "2000003",
74        "UMask": "0x18"
75    },
76    {
77        "BriefDescription": "Cycles MITE is delivering 4 Uops",
78        "CounterMask": "4",
79        "EventCode": "0x79",
80        "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
81        "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.",
82        "SampleAfterValue": "2000003",
83        "UMask": "0x24"
84    },
85    {
86        "BriefDescription": "Cycles MITE is delivering any Uop",
87        "CounterMask": "1",
88        "EventCode": "0x79",
89        "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
90        "PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.",
91        "SampleAfterValue": "2000003",
92        "UMask": "0x24"
93    },
94    {
95        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
96        "CounterMask": "1",
97        "EventCode": "0x79",
98        "EventName": "IDQ.DSB_CYCLES",
99        "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
100        "SampleAfterValue": "2000003",
101        "UMask": "0x8"
102    },
103    {
104        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
105        "EventCode": "0x79",
106        "EventName": "IDQ.DSB_UOPS",
107        "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
108        "SampleAfterValue": "2000003",
109        "UMask": "0x8"
110    },
111    {
112        "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
113        "EventCode": "0x79",
114        "EventName": "IDQ.EMPTY",
115        "PublicDescription": "Counts cycles the IDQ is empty.",
116        "SampleAfterValue": "2000003",
117        "UMask": "0x2"
118    },
119    {
120        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
121        "EventCode": "0x79",
122        "EventName": "IDQ.MITE_ALL_UOPS",
123        "PublicDescription": "Number of uops delivered to IDQ from any path.",
124        "SampleAfterValue": "2000003",
125        "UMask": "0x3c"
126    },
127    {
128        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
129        "CounterMask": "1",
130        "EventCode": "0x79",
131        "EventName": "IDQ.MITE_CYCLES",
132        "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
133        "SampleAfterValue": "2000003",
134        "UMask": "0x4"
135    },
136    {
137        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
138        "EventCode": "0x79",
139        "EventName": "IDQ.MITE_UOPS",
140        "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
141        "SampleAfterValue": "2000003",
142        "UMask": "0x4"
143    },
144    {
145        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
146        "CounterMask": "1",
147        "EventCode": "0x79",
148        "EventName": "IDQ.MS_CYCLES",
149        "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
150        "SampleAfterValue": "2000003",
151        "UMask": "0x30"
152    },
153    {
154        "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
155        "CounterMask": "1",
156        "EventCode": "0x79",
157        "EventName": "IDQ.MS_DSB_CYCLES",
158        "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
159        "SampleAfterValue": "2000003",
160        "UMask": "0x10"
161    },
162    {
163        "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy",
164        "CounterMask": "1",
165        "EdgeDetect": "1",
166        "EventCode": "0x79",
167        "EventName": "IDQ.MS_DSB_OCCUR",
168        "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.",
169        "SampleAfterValue": "2000003",
170        "UMask": "0x10"
171    },
172    {
173        "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
174        "EventCode": "0x79",
175        "EventName": "IDQ.MS_DSB_UOPS",
176        "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
177        "SampleAfterValue": "2000003",
178        "UMask": "0x10"
179    },
180    {
181        "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
182        "EventCode": "0x79",
183        "EventName": "IDQ.MS_MITE_UOPS",
184        "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
185        "SampleAfterValue": "2000003",
186        "UMask": "0x20"
187    },
188    {
189        "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
190        "CounterMask": "1",
191        "EdgeDetect": "1",
192        "EventCode": "0x79",
193        "EventName": "IDQ.MS_SWITCHES",
194        "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
195        "SampleAfterValue": "2000003",
196        "UMask": "0x30"
197    },
198    {
199        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
200        "EventCode": "0x79",
201        "EventName": "IDQ.MS_UOPS",
202        "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",
203        "SampleAfterValue": "2000003",
204        "UMask": "0x30"
205    },
206    {
207        "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
208        "EventCode": "0x9C",
209        "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
210        "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.",
211        "SampleAfterValue": "2000003",
212        "UMask": "0x1"
213    },
214    {
215        "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
216        "CounterMask": "4",
217        "EventCode": "0x9C",
218        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
219        "SampleAfterValue": "2000003",
220        "UMask": "0x1"
221    },
222    {
223        "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
224        "CounterMask": "1",
225        "EventCode": "0x9C",
226        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
227        "Invert": "1",
228        "SampleAfterValue": "2000003",
229        "UMask": "0x1"
230    },
231    {
232        "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
233        "CounterMask": "3",
234        "EventCode": "0x9C",
235        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
236        "SampleAfterValue": "2000003",
237        "UMask": "0x1"
238    },
239    {
240        "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
241        "CounterMask": "2",
242        "EventCode": "0x9C",
243        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
244        "SampleAfterValue": "2000003",
245        "UMask": "0x1"
246    },
247    {
248        "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
249        "CounterMask": "1",
250        "EventCode": "0x9C",
251        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
252        "SampleAfterValue": "2000003",
253        "UMask": "0x1"
254    }
255]
256