1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Intel Atom platform clocks for BayTrail and CherryTrail SoC.
4  *
5  * Copyright (C) 2016, Intel Corporation
6  * Author: Irina Tirdea <irina.tirdea@intel.com>
7  */
8 
9 #ifndef __PLATFORM_DATA_X86_CLK_PMC_ATOM_H
10 #define __PLATFORM_DATA_X86_CLK_PMC_ATOM_H
11 
12 /**
13  * struct pmc_clk - PMC platform clock configuration
14  *
15  * @name:	identified, typically pmc_plt_clk_<x>, x=[0..5]
16  * @freq:	in Hz, 19.2MHz  and 25MHz (Baytrail only) supported
17  * @parent_name: one of 'xtal' or 'osc'
18  */
19 struct pmc_clk {
20 	const char *name;
21 	unsigned long freq;
22 	const char *parent_name;
23 };
24 
25 /**
26  * struct pmc_clk_data - common PMC clock configuration
27  *
28  * @base:	PMC clock register base offset
29  * @clks:	pointer to set of registered clocks, typically 0..5
30  * @critical:	flag to indicate if firmware enabled pmc_plt_clks
31  *		should be marked as critial or not
32  */
33 struct pmc_clk_data {
34 	void __iomem *base;
35 	const struct pmc_clk *clks;
36 	bool critical;
37 };
38 
39 #endif /* __PLATFORM_DATA_X86_CLK_PMC_ATOM_H */
40