1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Toppoly TD028TTEC1 panel support
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 *
8 * Neo 1973 code (jbt6k74.c):
9 * Copyright (C) 2006-2007 by OpenMoko, Inc.
10 * Author: Harald Welte <laforge@openmoko.org>
11 *
12 * Ported and adapted from Neo 1973 U-Boot by:
13 * H. Nikolaus Schaller <hns@goldelico.com>
14 */
15
16 #include <linux/module.h>
17 #include <linux/delay.h>
18 #include <linux/spi/spi.h>
19 #include <video/omapfb_dss.h>
20
21 struct panel_drv_data {
22 struct omap_dss_device dssdev;
23 struct omap_dss_device *in;
24
25 int data_lines;
26
27 struct omap_video_timings videomode;
28
29 struct spi_device *spi_dev;
30 };
31
32 static const struct omap_video_timings td028ttec1_panel_timings = {
33 .x_res = 480,
34 .y_res = 640,
35 .pixelclock = 22153000,
36 .hfp = 24,
37 .hsw = 8,
38 .hbp = 8,
39 .vfp = 4,
40 .vsw = 2,
41 .vbp = 2,
42
43 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
44 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
45
46 .data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
47 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
48 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
49 };
50
51 #define JBT_COMMAND 0x000
52 #define JBT_DATA 0x100
53
jbt_ret_write_0(struct panel_drv_data * ddata,u8 reg)54 static int jbt_ret_write_0(struct panel_drv_data *ddata, u8 reg)
55 {
56 int rc;
57 u16 tx_buf = JBT_COMMAND | reg;
58
59 rc = spi_write(ddata->spi_dev, (u8 *)&tx_buf,
60 1*sizeof(u16));
61 if (rc != 0)
62 dev_err(&ddata->spi_dev->dev,
63 "jbt_ret_write_0 spi_write ret %d\n", rc);
64
65 return rc;
66 }
67
jbt_reg_write_1(struct panel_drv_data * ddata,u8 reg,u8 data)68 static int jbt_reg_write_1(struct panel_drv_data *ddata, u8 reg, u8 data)
69 {
70 int rc;
71 u16 tx_buf[2];
72
73 tx_buf[0] = JBT_COMMAND | reg;
74 tx_buf[1] = JBT_DATA | data;
75 rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
76 2*sizeof(u16));
77 if (rc != 0)
78 dev_err(&ddata->spi_dev->dev,
79 "jbt_reg_write_1 spi_write ret %d\n", rc);
80
81 return rc;
82 }
83
jbt_reg_write_2(struct panel_drv_data * ddata,u8 reg,u16 data)84 static int jbt_reg_write_2(struct panel_drv_data *ddata, u8 reg, u16 data)
85 {
86 int rc;
87 u16 tx_buf[3];
88
89 tx_buf[0] = JBT_COMMAND | reg;
90 tx_buf[1] = JBT_DATA | (data >> 8);
91 tx_buf[2] = JBT_DATA | (data & 0xff);
92
93 rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
94 3*sizeof(u16));
95
96 if (rc != 0)
97 dev_err(&ddata->spi_dev->dev,
98 "jbt_reg_write_2 spi_write ret %d\n", rc);
99
100 return rc;
101 }
102
103 enum jbt_register {
104 JBT_REG_SLEEP_IN = 0x10,
105 JBT_REG_SLEEP_OUT = 0x11,
106
107 JBT_REG_DISPLAY_OFF = 0x28,
108 JBT_REG_DISPLAY_ON = 0x29,
109
110 JBT_REG_RGB_FORMAT = 0x3a,
111 JBT_REG_QUAD_RATE = 0x3b,
112
113 JBT_REG_POWER_ON_OFF = 0xb0,
114 JBT_REG_BOOSTER_OP = 0xb1,
115 JBT_REG_BOOSTER_MODE = 0xb2,
116 JBT_REG_BOOSTER_FREQ = 0xb3,
117 JBT_REG_OPAMP_SYSCLK = 0xb4,
118 JBT_REG_VSC_VOLTAGE = 0xb5,
119 JBT_REG_VCOM_VOLTAGE = 0xb6,
120 JBT_REG_EXT_DISPL = 0xb7,
121 JBT_REG_OUTPUT_CONTROL = 0xb8,
122 JBT_REG_DCCLK_DCEV = 0xb9,
123 JBT_REG_DISPLAY_MODE1 = 0xba,
124 JBT_REG_DISPLAY_MODE2 = 0xbb,
125 JBT_REG_DISPLAY_MODE = 0xbc,
126 JBT_REG_ASW_SLEW = 0xbd,
127 JBT_REG_DUMMY_DISPLAY = 0xbe,
128 JBT_REG_DRIVE_SYSTEM = 0xbf,
129
130 JBT_REG_SLEEP_OUT_FR_A = 0xc0,
131 JBT_REG_SLEEP_OUT_FR_B = 0xc1,
132 JBT_REG_SLEEP_OUT_FR_C = 0xc2,
133 JBT_REG_SLEEP_IN_LCCNT_D = 0xc3,
134 JBT_REG_SLEEP_IN_LCCNT_E = 0xc4,
135 JBT_REG_SLEEP_IN_LCCNT_F = 0xc5,
136 JBT_REG_SLEEP_IN_LCCNT_G = 0xc6,
137
138 JBT_REG_GAMMA1_FINE_1 = 0xc7,
139 JBT_REG_GAMMA1_FINE_2 = 0xc8,
140 JBT_REG_GAMMA1_INCLINATION = 0xc9,
141 JBT_REG_GAMMA1_BLUE_OFFSET = 0xca,
142
143 JBT_REG_BLANK_CONTROL = 0xcf,
144 JBT_REG_BLANK_TH_TV = 0xd0,
145 JBT_REG_CKV_ON_OFF = 0xd1,
146 JBT_REG_CKV_1_2 = 0xd2,
147 JBT_REG_OEV_TIMING = 0xd3,
148 JBT_REG_ASW_TIMING_1 = 0xd4,
149 JBT_REG_ASW_TIMING_2 = 0xd5,
150
151 JBT_REG_HCLOCK_VGA = 0xec,
152 JBT_REG_HCLOCK_QVGA = 0xed,
153 };
154
155 #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
156
td028ttec1_panel_connect(struct omap_dss_device * dssdev)157 static int td028ttec1_panel_connect(struct omap_dss_device *dssdev)
158 {
159 struct panel_drv_data *ddata = to_panel_data(dssdev);
160 struct omap_dss_device *in = ddata->in;
161 int r;
162
163 if (omapdss_device_is_connected(dssdev))
164 return 0;
165
166 r = in->ops.dpi->connect(in, dssdev);
167 if (r)
168 return r;
169
170 return 0;
171 }
172
td028ttec1_panel_disconnect(struct omap_dss_device * dssdev)173 static void td028ttec1_panel_disconnect(struct omap_dss_device *dssdev)
174 {
175 struct panel_drv_data *ddata = to_panel_data(dssdev);
176 struct omap_dss_device *in = ddata->in;
177
178 if (!omapdss_device_is_connected(dssdev))
179 return;
180
181 in->ops.dpi->disconnect(in, dssdev);
182 }
183
td028ttec1_panel_enable(struct omap_dss_device * dssdev)184 static int td028ttec1_panel_enable(struct omap_dss_device *dssdev)
185 {
186 struct panel_drv_data *ddata = to_panel_data(dssdev);
187 struct omap_dss_device *in = ddata->in;
188 int r;
189
190 if (!omapdss_device_is_connected(dssdev))
191 return -ENODEV;
192
193 if (omapdss_device_is_enabled(dssdev))
194 return 0;
195
196 if (ddata->data_lines)
197 in->ops.dpi->set_data_lines(in, ddata->data_lines);
198 in->ops.dpi->set_timings(in, &ddata->videomode);
199
200 r = in->ops.dpi->enable(in);
201 if (r)
202 return r;
203
204 dev_dbg(dssdev->dev, "td028ttec1_panel_enable() - state %d\n",
205 dssdev->state);
206
207 /* three times command zero */
208 r |= jbt_ret_write_0(ddata, 0x00);
209 usleep_range(1000, 2000);
210 r |= jbt_ret_write_0(ddata, 0x00);
211 usleep_range(1000, 2000);
212 r |= jbt_ret_write_0(ddata, 0x00);
213 usleep_range(1000, 2000);
214
215 if (r) {
216 dev_warn(dssdev->dev, "transfer error\n");
217 goto transfer_err;
218 }
219
220 /* deep standby out */
221 r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x17);
222
223 /* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
224 r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE, 0x80);
225
226 /* Quad mode off */
227 r |= jbt_reg_write_1(ddata, JBT_REG_QUAD_RATE, 0x00);
228
229 /* AVDD on, XVDD on */
230 r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x16);
231
232 /* Output control */
233 r |= jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0xfff9);
234
235 /* Sleep mode off */
236 r |= jbt_ret_write_0(ddata, JBT_REG_SLEEP_OUT);
237
238 /* at this point we have like 50% grey */
239
240 /* initialize register set */
241 r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE1, 0x01);
242 r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE2, 0x00);
243 r |= jbt_reg_write_1(ddata, JBT_REG_RGB_FORMAT, 0x60);
244 r |= jbt_reg_write_1(ddata, JBT_REG_DRIVE_SYSTEM, 0x10);
245 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_OP, 0x56);
246 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_MODE, 0x33);
247 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
248 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
249 r |= jbt_reg_write_1(ddata, JBT_REG_OPAMP_SYSCLK, 0x02);
250 r |= jbt_reg_write_1(ddata, JBT_REG_VSC_VOLTAGE, 0x2b);
251 r |= jbt_reg_write_1(ddata, JBT_REG_VCOM_VOLTAGE, 0x40);
252 r |= jbt_reg_write_1(ddata, JBT_REG_EXT_DISPL, 0x03);
253 r |= jbt_reg_write_1(ddata, JBT_REG_DCCLK_DCEV, 0x04);
254 /*
255 * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
256 * to avoid red / blue flicker
257 */
258 r |= jbt_reg_write_1(ddata, JBT_REG_ASW_SLEW, 0x04);
259 r |= jbt_reg_write_1(ddata, JBT_REG_DUMMY_DISPLAY, 0x00);
260
261 r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_A, 0x11);
262 r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_B, 0x11);
263 r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_C, 0x11);
264 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
265 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
266 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
267 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
268
269 r |= jbt_reg_write_2(ddata, JBT_REG_GAMMA1_FINE_1, 0x5533);
270 r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_FINE_2, 0x00);
271 r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_INCLINATION, 0x00);
272 r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
273
274 r |= jbt_reg_write_2(ddata, JBT_REG_HCLOCK_VGA, 0x1f0);
275 r |= jbt_reg_write_1(ddata, JBT_REG_BLANK_CONTROL, 0x02);
276 r |= jbt_reg_write_2(ddata, JBT_REG_BLANK_TH_TV, 0x0804);
277
278 r |= jbt_reg_write_1(ddata, JBT_REG_CKV_ON_OFF, 0x01);
279 r |= jbt_reg_write_2(ddata, JBT_REG_CKV_1_2, 0x0000);
280
281 r |= jbt_reg_write_2(ddata, JBT_REG_OEV_TIMING, 0x0d0e);
282 r |= jbt_reg_write_2(ddata, JBT_REG_ASW_TIMING_1, 0x11a4);
283 r |= jbt_reg_write_1(ddata, JBT_REG_ASW_TIMING_2, 0x0e);
284
285 r |= jbt_ret_write_0(ddata, JBT_REG_DISPLAY_ON);
286
287 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
288
289 transfer_err:
290
291 return r ? -EIO : 0;
292 }
293
td028ttec1_panel_disable(struct omap_dss_device * dssdev)294 static void td028ttec1_panel_disable(struct omap_dss_device *dssdev)
295 {
296 struct panel_drv_data *ddata = to_panel_data(dssdev);
297 struct omap_dss_device *in = ddata->in;
298
299 if (!omapdss_device_is_enabled(dssdev))
300 return;
301
302 dev_dbg(dssdev->dev, "td028ttec1_panel_disable()\n");
303
304 jbt_ret_write_0(ddata, JBT_REG_DISPLAY_OFF);
305 jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0x8002);
306 jbt_ret_write_0(ddata, JBT_REG_SLEEP_IN);
307 jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x00);
308
309 in->ops.dpi->disable(in);
310
311 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
312 }
313
td028ttec1_panel_set_timings(struct omap_dss_device * dssdev,struct omap_video_timings * timings)314 static void td028ttec1_panel_set_timings(struct omap_dss_device *dssdev,
315 struct omap_video_timings *timings)
316 {
317 struct panel_drv_data *ddata = to_panel_data(dssdev);
318 struct omap_dss_device *in = ddata->in;
319
320 ddata->videomode = *timings;
321 dssdev->panel.timings = *timings;
322
323 in->ops.dpi->set_timings(in, timings);
324 }
325
td028ttec1_panel_get_timings(struct omap_dss_device * dssdev,struct omap_video_timings * timings)326 static void td028ttec1_panel_get_timings(struct omap_dss_device *dssdev,
327 struct omap_video_timings *timings)
328 {
329 struct panel_drv_data *ddata = to_panel_data(dssdev);
330
331 *timings = ddata->videomode;
332 }
333
td028ttec1_panel_check_timings(struct omap_dss_device * dssdev,struct omap_video_timings * timings)334 static int td028ttec1_panel_check_timings(struct omap_dss_device *dssdev,
335 struct omap_video_timings *timings)
336 {
337 struct panel_drv_data *ddata = to_panel_data(dssdev);
338 struct omap_dss_device *in = ddata->in;
339
340 return in->ops.dpi->check_timings(in, timings);
341 }
342
343 static struct omap_dss_driver td028ttec1_ops = {
344 .connect = td028ttec1_panel_connect,
345 .disconnect = td028ttec1_panel_disconnect,
346
347 .enable = td028ttec1_panel_enable,
348 .disable = td028ttec1_panel_disable,
349
350 .set_timings = td028ttec1_panel_set_timings,
351 .get_timings = td028ttec1_panel_get_timings,
352 .check_timings = td028ttec1_panel_check_timings,
353 };
354
td028ttec1_probe_of(struct spi_device * spi)355 static int td028ttec1_probe_of(struct spi_device *spi)
356 {
357 struct device_node *node = spi->dev.of_node;
358 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
359 struct omap_dss_device *in;
360
361 in = omapdss_of_find_source_for_first_ep(node);
362 if (IS_ERR(in)) {
363 dev_err(&spi->dev, "failed to find video source\n");
364 return PTR_ERR(in);
365 }
366
367 ddata->in = in;
368
369 return 0;
370 }
371
td028ttec1_panel_probe(struct spi_device * spi)372 static int td028ttec1_panel_probe(struct spi_device *spi)
373 {
374 struct panel_drv_data *ddata;
375 struct omap_dss_device *dssdev;
376 int r;
377
378 dev_dbg(&spi->dev, "%s\n", __func__);
379
380 if (!spi->dev.of_node)
381 return -ENODEV;
382
383 spi->bits_per_word = 9;
384 spi->mode = SPI_MODE_3;
385
386 r = spi_setup(spi);
387 if (r < 0) {
388 dev_err(&spi->dev, "spi_setup failed: %d\n", r);
389 return r;
390 }
391
392 ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
393 if (ddata == NULL)
394 return -ENOMEM;
395
396 dev_set_drvdata(&spi->dev, ddata);
397
398 ddata->spi_dev = spi;
399
400 r = td028ttec1_probe_of(spi);
401 if (r)
402 return r;
403
404 ddata->videomode = td028ttec1_panel_timings;
405
406 dssdev = &ddata->dssdev;
407 dssdev->dev = &spi->dev;
408 dssdev->driver = &td028ttec1_ops;
409 dssdev->type = OMAP_DISPLAY_TYPE_DPI;
410 dssdev->owner = THIS_MODULE;
411 dssdev->panel.timings = ddata->videomode;
412 dssdev->phy.dpi.data_lines = ddata->data_lines;
413
414 r = omapdss_register_display(dssdev);
415 if (r) {
416 dev_err(&spi->dev, "Failed to register panel\n");
417 goto err_reg;
418 }
419
420 return 0;
421
422 err_reg:
423 omap_dss_put_device(ddata->in);
424 return r;
425 }
426
td028ttec1_panel_remove(struct spi_device * spi)427 static void td028ttec1_panel_remove(struct spi_device *spi)
428 {
429 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
430 struct omap_dss_device *dssdev = &ddata->dssdev;
431 struct omap_dss_device *in = ddata->in;
432
433 dev_dbg(&ddata->spi_dev->dev, "%s\n", __func__);
434
435 omapdss_unregister_display(dssdev);
436
437 td028ttec1_panel_disable(dssdev);
438 td028ttec1_panel_disconnect(dssdev);
439
440 omap_dss_put_device(in);
441 }
442
443 static const struct of_device_id td028ttec1_of_match[] = {
444 { .compatible = "omapdss,tpo,td028ttec1", },
445 /* keep to not break older DTB */
446 { .compatible = "omapdss,toppoly,td028ttec1", },
447 {},
448 };
449
450 MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
451
452 static const struct spi_device_id td028ttec1_ids[] = {
453 { "toppoly,td028ttec1", 0 },
454 { "tpo,td028ttec1", 0},
455 { /* sentinel */ }
456 };
457
458 MODULE_DEVICE_TABLE(spi, td028ttec1_ids);
459
460 static struct spi_driver td028ttec1_spi_driver = {
461 .probe = td028ttec1_panel_probe,
462 .remove = td028ttec1_panel_remove,
463 .id_table = td028ttec1_ids,
464
465 .driver = {
466 .name = "panel-tpo-td028ttec1",
467 .of_match_table = td028ttec1_of_match,
468 .suppress_bind_attrs = true,
469 },
470 };
471
472 module_spi_driver(td028ttec1_spi_driver);
473
474 MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
475 MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
476 MODULE_LICENSE("GPL");
477
