1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
5 *
6 */
7
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/of.h>
11 #include <linux/pinctrl/pinctrl.h>
12 #include <linux/regmap.h>
13 #include <linux/pinctrl/pinconf-generic.h>
14 #include <dt-bindings/pinctrl/mt65xx.h>
15
16 #include "pinctrl-mtk-common.h"
17 #include "pinctrl-mtk-mt2712.h"
18
19 static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = {
20 MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
21 MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
22 MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
23 MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
24 MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
25 MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
26
27 MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
28 MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
29 MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
30 MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
31 MTK_PIN_PUPD_SPEC_SR(34, 0xf40, 2, 1, 0),
32 MTK_PIN_PUPD_SPEC_SR(35, 0xf40, 6, 5, 4),
33 MTK_PIN_PUPD_SPEC_SR(36, 0xf40, 10, 9, 8),
34 MTK_PIN_PUPD_SPEC_SR(37, 0xc40, 2, 1, 0),
35 MTK_PIN_PUPD_SPEC_SR(38, 0xc60, 2, 1, 0),
36 MTK_PIN_PUPD_SPEC_SR(39, 0xc60, 2, 1, 0),
37 MTK_PIN_PUPD_SPEC_SR(40, 0xc60, 2, 1, 0),
38 MTK_PIN_PUPD_SPEC_SR(41, 0xc60, 2, 1, 0),
39 MTK_PIN_PUPD_SPEC_SR(42, 0xc60, 2, 1, 0),
40 MTK_PIN_PUPD_SPEC_SR(43, 0xc60, 2, 1, 0),
41 MTK_PIN_PUPD_SPEC_SR(44, 0xc60, 2, 1, 0),
42 MTK_PIN_PUPD_SPEC_SR(45, 0xc60, 2, 1, 0),
43 MTK_PIN_PUPD_SPEC_SR(46, 0xc50, 2, 1, 0),
44 MTK_PIN_PUPD_SPEC_SR(47, 0xda0, 2, 1, 0),
45 MTK_PIN_PUPD_SPEC_SR(48, 0xd90, 2, 1, 0),
46 MTK_PIN_PUPD_SPEC_SR(49, 0xdf0, 14, 13, 12),
47 MTK_PIN_PUPD_SPEC_SR(50, 0xdf0, 10, 9, 8),
48 MTK_PIN_PUPD_SPEC_SR(51, 0xdf0, 6, 5, 4),
49 MTK_PIN_PUPD_SPEC_SR(52, 0xdf0, 2, 1, 0),
50 MTK_PIN_PUPD_SPEC_SR(53, 0xd50, 2, 1, 0),
51 MTK_PIN_PUPD_SPEC_SR(54, 0xd80, 2, 1, 0),
52 MTK_PIN_PUPD_SPEC_SR(55, 0xe00, 2, 1, 0),
53 MTK_PIN_PUPD_SPEC_SR(56, 0xd40, 2, 1, 0),
54
55 MTK_PIN_PUPD_SPEC_SR(63, 0xc80, 2, 1, 0),
56 MTK_PIN_PUPD_SPEC_SR(64, 0xdb0, 14, 13, 12),
57 MTK_PIN_PUPD_SPEC_SR(65, 0xdb0, 6, 5, 4),
58 MTK_PIN_PUPD_SPEC_SR(66, 0xdb0, 10, 9, 8),
59 MTK_PIN_PUPD_SPEC_SR(67, 0xcd0, 2, 1, 0),
60 MTK_PIN_PUPD_SPEC_SR(68, 0xdb0, 2, 1, 0),
61 MTK_PIN_PUPD_SPEC_SR(69, 0xc90, 2, 1, 0),
62 MTK_PIN_PUPD_SPEC_SR(70, 0xcc0, 2, 1, 0),
63
64 MTK_PIN_PUPD_SPEC_SR(89, 0xce0, 2, 1, 0),
65 MTK_PIN_PUPD_SPEC_SR(90, 0xdd0, 14, 13, 12),
66 MTK_PIN_PUPD_SPEC_SR(91, 0xdd0, 10, 9, 8),
67 MTK_PIN_PUPD_SPEC_SR(92, 0xdd0, 6, 5, 4),
68 MTK_PIN_PUPD_SPEC_SR(93, 0xdd0, 2, 1, 0),
69 MTK_PIN_PUPD_SPEC_SR(94, 0xd20, 2, 1, 0),
70 MTK_PIN_PUPD_SPEC_SR(95, 0xcf0, 2, 1, 0),
71 MTK_PIN_PUPD_SPEC_SR(96, 0xd30, 2, 1, 0),
72
73 MTK_PIN_PUPD_SPEC_SR(135, 0xe50, 11, 10, 9),
74 MTK_PIN_PUPD_SPEC_SR(136, 0xe50, 14, 13, 12),
75 MTK_PIN_PUPD_SPEC_SR(137, 0xe70, 5, 4, 3),
76 MTK_PIN_PUPD_SPEC_SR(138, 0xe70, 8, 7, 6),
77 MTK_PIN_PUPD_SPEC_SR(139, 0xe70, 11, 10, 9),
78 MTK_PIN_PUPD_SPEC_SR(140, 0xe70, 14, 13, 12),
79 MTK_PIN_PUPD_SPEC_SR(141, 0xe60, 2, 1, 0),
80 MTK_PIN_PUPD_SPEC_SR(142, 0xe60, 5, 4, 3)
81 };
82
83 static const struct mtk_pin_ies_smt_set mt2712_smt_set[] = {
84 MTK_PIN_IES_SMT_SPEC(0, 3, 0x900, 2),
85 MTK_PIN_IES_SMT_SPEC(4, 7, 0x900, 0),
86 MTK_PIN_IES_SMT_SPEC(8, 11, 0x900, 1),
87 MTK_PIN_IES_SMT_SPEC(12, 12, 0x8d0, 6),
88 MTK_PIN_IES_SMT_SPEC(13, 13, 0x8d0, 7),
89 MTK_PIN_IES_SMT_SPEC(14, 14, 0x8d0, 6),
90 MTK_PIN_IES_SMT_SPEC(15, 15, 0x8d0, 7),
91 MTK_PIN_IES_SMT_SPEC(18, 23, 0x8d0, 1),
92 MTK_PIN_IES_SMT_SPEC(24, 25, 0x8d0, 2),
93 MTK_PIN_IES_SMT_SPEC(26, 26, 0x8d0, 3),
94 MTK_PIN_IES_SMT_SPEC(27, 27, 0x8d0, 4),
95 MTK_PIN_IES_SMT_SPEC(28, 29, 0x8d0, 3),
96 MTK_PIN_IES_SMT_SPEC(30, 36, 0xf50, 13),
97 MTK_PIN_IES_SMT_SPEC(37, 37, 0xc40, 13),
98 MTK_PIN_IES_SMT_SPEC(38, 45, 0xc60, 13),
99 MTK_PIN_IES_SMT_SPEC(46, 46, 0xc50, 13),
100 MTK_PIN_IES_SMT_SPEC(47, 47, 0xda0, 13),
101 MTK_PIN_IES_SMT_SPEC(48, 48, 0xd90, 13),
102 MTK_PIN_IES_SMT_SPEC(49, 52, 0xd60, 13),
103 MTK_PIN_IES_SMT_SPEC(53, 53, 0xd50, 13),
104 MTK_PIN_IES_SMT_SPEC(54, 54, 0xd80, 13),
105 MTK_PIN_IES_SMT_SPEC(55, 55, 0xe00, 13),
106 MTK_PIN_IES_SMT_SPEC(56, 56, 0xd40, 13),
107 MTK_PIN_IES_SMT_SPEC(57, 62, 0x900, 3),
108 MTK_PIN_IES_SMT_SPEC(63, 63, 0xc80, 13),
109 MTK_PIN_IES_SMT_SPEC(64, 66, 0xca0, 13),
110 MTK_PIN_IES_SMT_SPEC(67, 67, 0xc80, 13),
111 MTK_PIN_IES_SMT_SPEC(68, 68, 0xca0, 13),
112 MTK_PIN_IES_SMT_SPEC(69, 69, 0xc90, 13),
113 MTK_PIN_IES_SMT_SPEC(70, 70, 0xc80, 13),
114 MTK_PIN_IES_SMT_SPEC(71, 74, 0x8d0, 8),
115 MTK_PIN_IES_SMT_SPEC(75, 77, 0x8d0, 9),
116 MTK_PIN_IES_SMT_SPEC(78, 81, 0x8d0, 10),
117 MTK_PIN_IES_SMT_SPEC(82, 88, 0x8d0, 9),
118 MTK_PIN_IES_SMT_SPEC(89, 89, 0xce0, 13),
119 MTK_PIN_IES_SMT_SPEC(90, 93, 0xd00, 13),
120 MTK_PIN_IES_SMT_SPEC(94, 94, 0xce0, 13),
121 MTK_PIN_IES_SMT_SPEC(95, 96, 0xcf0, 13),
122 MTK_PIN_IES_SMT_SPEC(97, 100, 0x8d0, 11),
123 MTK_PIN_IES_SMT_SPEC(101, 104, 0x8d0, 12),
124 MTK_PIN_IES_SMT_SPEC(105, 105, 0x8d0, 13),
125 MTK_PIN_IES_SMT_SPEC(106, 106, 0x8d0, 14),
126 MTK_PIN_IES_SMT_SPEC(107, 107, 0x8d0, 15),
127 MTK_PIN_IES_SMT_SPEC(108, 108, 0x8e0, 0),
128 MTK_PIN_IES_SMT_SPEC(109, 109, 0x8e0, 1),
129 MTK_PIN_IES_SMT_SPEC(110, 110, 0x8e0, 2),
130 MTK_PIN_IES_SMT_SPEC(111, 111, 0x8d0, 13),
131 MTK_PIN_IES_SMT_SPEC(112, 112, 0x8d0, 14),
132 MTK_PIN_IES_SMT_SPEC(113, 113, 0x8d0, 15),
133 MTK_PIN_IES_SMT_SPEC(114, 114, 0x8e0, 0),
134 MTK_PIN_IES_SMT_SPEC(115, 115, 0x8e0, 1),
135 MTK_PIN_IES_SMT_SPEC(116, 116, 0x8e0, 2),
136 MTK_PIN_IES_SMT_SPEC(117, 117, 0x8e0, 3),
137 MTK_PIN_IES_SMT_SPEC(118, 118, 0x8e0, 4),
138 MTK_PIN_IES_SMT_SPEC(119, 119, 0x8e0, 5),
139 MTK_PIN_IES_SMT_SPEC(120, 120, 0x8e0, 3),
140 MTK_PIN_IES_SMT_SPEC(121, 121, 0x8e0, 4),
141 MTK_PIN_IES_SMT_SPEC(122, 122, 0x8e0, 5),
142 MTK_PIN_IES_SMT_SPEC(123, 126, 0x8e0, 6),
143 MTK_PIN_IES_SMT_SPEC(127, 130, 0x8e0, 7),
144 MTK_PIN_IES_SMT_SPEC(131, 134, 0x8e0, 8),
145 MTK_PIN_IES_SMT_SPEC(135, 142, 0x8d0, 1),
146 MTK_PIN_IES_SMT_SPEC(143, 147, 0x8e0, 9),
147 MTK_PIN_IES_SMT_SPEC(148, 152, 0x8e0, 10),
148 MTK_PIN_IES_SMT_SPEC(153, 156, 0x8e0, 11),
149 MTK_PIN_IES_SMT_SPEC(157, 160, 0x8e0, 12),
150 MTK_PIN_IES_SMT_SPEC(161, 164, 0x8e0, 13),
151 MTK_PIN_IES_SMT_SPEC(165, 168, 0x8e0, 14),
152 MTK_PIN_IES_SMT_SPEC(169, 170, 0x8e0, 15),
153 MTK_PIN_IES_SMT_SPEC(171, 172, 0x8f0, 0),
154 MTK_PIN_IES_SMT_SPEC(173, 173, 0x8f0, 1),
155 MTK_PIN_IES_SMT_SPEC(174, 175, 0x8f0, 2),
156 MTK_PIN_IES_SMT_SPEC(176, 176, 0x8f0, 1),
157 MTK_PIN_IES_SMT_SPEC(177, 177, 0x8f0, 3),
158 MTK_PIN_IES_SMT_SPEC(178, 178, 0x8f0, 4),
159 MTK_PIN_IES_SMT_SPEC(179, 179, 0x8f0, 3),
160 MTK_PIN_IES_SMT_SPEC(180, 180, 0x8f0, 4),
161 MTK_PIN_IES_SMT_SPEC(181, 181, 0x8f0, 5),
162 MTK_PIN_IES_SMT_SPEC(182, 182, 0x8f0, 6),
163 MTK_PIN_IES_SMT_SPEC(183, 183, 0x8f0, 5),
164 MTK_PIN_IES_SMT_SPEC(184, 184, 0x8f0, 6),
165 MTK_PIN_IES_SMT_SPEC(185, 186, 0x8f0, 7),
166 MTK_PIN_IES_SMT_SPEC(187, 187, 0x8f0, 8),
167 MTK_PIN_IES_SMT_SPEC(188, 188, 0x8f0, 9),
168 MTK_PIN_IES_SMT_SPEC(189, 189, 0x8f0, 8),
169 MTK_PIN_IES_SMT_SPEC(190, 190, 0x8f0, 9),
170 MTK_PIN_IES_SMT_SPEC(191, 191, 0x8f0, 10),
171 MTK_PIN_IES_SMT_SPEC(192, 192, 0x8f0, 11),
172 MTK_PIN_IES_SMT_SPEC(193, 194, 0x8f0, 10),
173 MTK_PIN_IES_SMT_SPEC(195, 195, 0x8f0, 11),
174 MTK_PIN_IES_SMT_SPEC(196, 199, 0x8f0, 12),
175 MTK_PIN_IES_SMT_SPEC(200, 203, 0x8f0, 13),
176 MTK_PIN_IES_SMT_SPEC(204, 206, 0x8f0, 14),
177 MTK_PIN_IES_SMT_SPEC(207, 209, 0x8f0, 15)
178 };
179
180 static const struct mtk_pin_ies_smt_set mt2712_ies_set[] = {
181 MTK_PIN_IES_SMT_SPEC(0, 3, 0x8c0, 2),
182 MTK_PIN_IES_SMT_SPEC(4, 7, 0x8c0, 0),
183 MTK_PIN_IES_SMT_SPEC(8, 9, 0x8c0, 1),
184 MTK_PIN_IES_SMT_SPEC(10, 11, 0x8c0, 4),
185 MTK_PIN_IES_SMT_SPEC(12, 12, 0x890, 6),
186 MTK_PIN_IES_SMT_SPEC(13, 13, 0x890, 7),
187 MTK_PIN_IES_SMT_SPEC(14, 14, 0x890, 6),
188 MTK_PIN_IES_SMT_SPEC(15, 15, 0x890, 7),
189 MTK_PIN_IES_SMT_SPEC(18, 23, 0x890, 1),
190 MTK_PIN_IES_SMT_SPEC(24, 25, 0x890, 2),
191 MTK_PIN_IES_SMT_SPEC(26, 26, 0x890, 3),
192 MTK_PIN_IES_SMT_SPEC(27, 27, 0x890, 4),
193 MTK_PIN_IES_SMT_SPEC(28, 29, 0x890, 3),
194 MTK_PIN_IES_SMT_SPEC(30, 36, 0xf50, 14),
195 MTK_PIN_IES_SMT_SPEC(37, 37, 0xc40, 14),
196 MTK_PIN_IES_SMT_SPEC(38, 45, 0xc60, 14),
197 MTK_PIN_IES_SMT_SPEC(46, 46, 0xc50, 14),
198 MTK_PIN_IES_SMT_SPEC(47, 47, 0xda0, 14),
199 MTK_PIN_IES_SMT_SPEC(48, 48, 0xd90, 14),
200 MTK_PIN_IES_SMT_SPEC(49, 52, 0xd60, 14),
201 MTK_PIN_IES_SMT_SPEC(53, 53, 0xd50, 14),
202 MTK_PIN_IES_SMT_SPEC(54, 54, 0xd80, 14),
203 MTK_PIN_IES_SMT_SPEC(55, 55, 0xe00, 14),
204 MTK_PIN_IES_SMT_SPEC(56, 56, 0xd40, 14),
205 MTK_PIN_IES_SMT_SPEC(57, 62, 0x8c0, 3),
206 MTK_PIN_IES_SMT_SPEC(63, 63, 0xc80, 14),
207 MTK_PIN_IES_SMT_SPEC(64, 66, 0xca0, 14),
208 MTK_PIN_IES_SMT_SPEC(67, 68, 0xc80, 14),
209 MTK_PIN_IES_SMT_SPEC(69, 69, 0xc90, 14),
210 MTK_PIN_IES_SMT_SPEC(70, 70, 0xc80, 14),
211 MTK_PIN_IES_SMT_SPEC(71, 74, 0x890, 8),
212 MTK_PIN_IES_SMT_SPEC(75, 77, 0x890, 9),
213 MTK_PIN_IES_SMT_SPEC(78, 81, 0x890, 10),
214 MTK_PIN_IES_SMT_SPEC(82, 88, 0x890, 9),
215 MTK_PIN_IES_SMT_SPEC(89, 89, 0xce0, 14),
216 MTK_PIN_IES_SMT_SPEC(90, 93, 0xd00, 14),
217 MTK_PIN_IES_SMT_SPEC(94, 94, 0xce0, 14),
218 MTK_PIN_IES_SMT_SPEC(95, 96, 0xcf0, 14),
219 MTK_PIN_IES_SMT_SPEC(97, 100, 0x890, 11),
220 MTK_PIN_IES_SMT_SPEC(101, 104, 0x890, 12),
221 MTK_PIN_IES_SMT_SPEC(105, 105, 0x890, 13),
222 MTK_PIN_IES_SMT_SPEC(106, 106, 0x890, 14),
223 MTK_PIN_IES_SMT_SPEC(107, 107, 0x890, 15),
224 MTK_PIN_IES_SMT_SPEC(108, 108, 0x8a0, 0),
225 MTK_PIN_IES_SMT_SPEC(109, 109, 0x8a0, 1),
226 MTK_PIN_IES_SMT_SPEC(110, 110, 0x8a0, 2),
227 MTK_PIN_IES_SMT_SPEC(111, 111, 0x890, 13),
228 MTK_PIN_IES_SMT_SPEC(112, 112, 0x890, 14),
229 MTK_PIN_IES_SMT_SPEC(113, 113, 0x890, 15),
230 MTK_PIN_IES_SMT_SPEC(114, 114, 0x8a0, 0),
231 MTK_PIN_IES_SMT_SPEC(115, 115, 0x8a0, 1),
232 MTK_PIN_IES_SMT_SPEC(116, 116, 0x8a0, 2),
233 MTK_PIN_IES_SMT_SPEC(117, 117, 0x8a0, 3),
234 MTK_PIN_IES_SMT_SPEC(118, 118, 0x8a0, 4),
235 MTK_PIN_IES_SMT_SPEC(119, 119, 0x8a0, 5),
236 MTK_PIN_IES_SMT_SPEC(120, 120, 0x8a0, 3),
237 MTK_PIN_IES_SMT_SPEC(121, 121, 0x8a0, 4),
238 MTK_PIN_IES_SMT_SPEC(122, 122, 0x8a0, 5),
239 MTK_PIN_IES_SMT_SPEC(123, 126, 0x8a0, 6),
240 MTK_PIN_IES_SMT_SPEC(127, 130, 0x8a0, 7),
241 MTK_PIN_IES_SMT_SPEC(131, 135, 0x8a0, 8),
242 MTK_PIN_IES_SMT_SPEC(136, 142, 0x890, 1),
243 MTK_PIN_IES_SMT_SPEC(143, 147, 0x8a0, 9),
244 MTK_PIN_IES_SMT_SPEC(148, 152, 0x8a0, 10),
245 MTK_PIN_IES_SMT_SPEC(153, 156, 0x8a0, 11),
246 MTK_PIN_IES_SMT_SPEC(157, 160, 0x8a0, 12),
247 MTK_PIN_IES_SMT_SPEC(161, 164, 0x8a0, 13),
248 MTK_PIN_IES_SMT_SPEC(165, 168, 0x8a0, 14),
249 MTK_PIN_IES_SMT_SPEC(169, 170, 0x8a0, 15),
250 MTK_PIN_IES_SMT_SPEC(171, 172, 0x8b0, 0),
251 MTK_PIN_IES_SMT_SPEC(173, 173, 0x8b0, 1),
252 MTK_PIN_IES_SMT_SPEC(174, 175, 0x8b0, 2),
253 MTK_PIN_IES_SMT_SPEC(176, 176, 0x8b0, 1),
254 MTK_PIN_IES_SMT_SPEC(177, 177, 0x8b0, 3),
255 MTK_PIN_IES_SMT_SPEC(178, 178, 0x8b0, 4),
256 MTK_PIN_IES_SMT_SPEC(179, 179, 0x8b0, 3),
257 MTK_PIN_IES_SMT_SPEC(180, 180, 0x8b0, 4),
258 MTK_PIN_IES_SMT_SPEC(181, 181, 0x8b0, 5),
259 MTK_PIN_IES_SMT_SPEC(182, 182, 0x8b0, 6),
260 MTK_PIN_IES_SMT_SPEC(183, 183, 0x8b0, 5),
261 MTK_PIN_IES_SMT_SPEC(184, 184, 0x8b0, 6),
262 MTK_PIN_IES_SMT_SPEC(185, 186, 0x8b0, 7),
263 MTK_PIN_IES_SMT_SPEC(187, 187, 0x8b0, 8),
264 MTK_PIN_IES_SMT_SPEC(188, 188, 0x8b0, 9),
265 MTK_PIN_IES_SMT_SPEC(189, 189, 0x8b0, 8),
266 MTK_PIN_IES_SMT_SPEC(190, 190, 0x8b0, 9),
267 MTK_PIN_IES_SMT_SPEC(191, 191, 0x8b0, 10),
268 MTK_PIN_IES_SMT_SPEC(192, 192, 0x8b0, 11),
269 MTK_PIN_IES_SMT_SPEC(193, 194, 0x8b0, 10),
270 MTK_PIN_IES_SMT_SPEC(195, 195, 0x8b0, 11),
271 MTK_PIN_IES_SMT_SPEC(196, 199, 0x8b0, 12),
272 MTK_PIN_IES_SMT_SPEC(200, 203, 0x8b0, 13),
273 MTK_PIN_IES_SMT_SPEC(204, 206, 0x8b0, 14),
274 MTK_PIN_IES_SMT_SPEC(207, 209, 0x8b0, 15)
275 };
276
277 static const struct mtk_drv_group_desc mt2712_drv_grp[] = {
278 /* 0E4E8SR 4/8/12/16 */
279 MTK_DRV_GRP(4, 16, 1, 2, 4),
280 /* 0E2E4SR 2/4/6/8 */
281 MTK_DRV_GRP(2, 8, 1, 2, 2),
282 /* E8E4E2 2/4/6/8/10/12/14/16 */
283 MTK_DRV_GRP(2, 16, 0, 2, 2)
284 };
285
286 static const struct mtk_pin_drv_grp mt2712_pin_drv[] = {
287 MTK_PIN_DRV_GRP(0, 0xc10, 4, 0),
288 MTK_PIN_DRV_GRP(1, 0xc10, 4, 0),
289 MTK_PIN_DRV_GRP(2, 0xc10, 4, 0),
290 MTK_PIN_DRV_GRP(3, 0xc10, 4, 0),
291
292 MTK_PIN_DRV_GRP(4, 0xc00, 12, 0),
293 MTK_PIN_DRV_GRP(5, 0xc00, 12, 0),
294 MTK_PIN_DRV_GRP(6, 0xc00, 12, 0),
295 MTK_PIN_DRV_GRP(7, 0xc00, 12, 0),
296
297 MTK_PIN_DRV_GRP(8, 0xc10, 0, 0),
298 MTK_PIN_DRV_GRP(9, 0xc10, 0, 0),
299 MTK_PIN_DRV_GRP(10, 0xc10, 0, 0),
300 MTK_PIN_DRV_GRP(11, 0xc10, 0, 0),
301
302 MTK_PIN_DRV_GRP(12, 0xb60, 0, 0),
303
304 MTK_PIN_DRV_GRP(13, 0xb60, 4, 0),
305
306 MTK_PIN_DRV_GRP(14, 0xb60, 0, 0),
307
308 MTK_PIN_DRV_GRP(15, 0xb60, 4, 0),
309
310 MTK_PIN_DRV_GRP(18, 0xb40, 0, 1),
311 MTK_PIN_DRV_GRP(19, 0xb40, 0, 1),
312 MTK_PIN_DRV_GRP(20, 0xb40, 0, 1),
313 MTK_PIN_DRV_GRP(21, 0xb40, 0, 1),
314 MTK_PIN_DRV_GRP(22, 0xb40, 0, 1),
315 MTK_PIN_DRV_GRP(23, 0xb40, 0, 1),
316
317 MTK_PIN_DRV_GRP(24, 0xb40, 4, 0),
318
319 MTK_PIN_DRV_GRP(25, 0xb40, 8, 0),
320
321 MTK_PIN_DRV_GRP(26, 0xb40, 12, 0),
322
323 MTK_PIN_DRV_GRP(27, 0xb50, 0, 0),
324
325 MTK_PIN_DRV_GRP(28, 0xb40, 12, 0),
326 MTK_PIN_DRV_GRP(29, 0xb40, 12, 0),
327
328 MTK_PIN_DRV_GRP(30, 0xf50, 8, 2),
329 MTK_PIN_DRV_GRP(31, 0xf50, 8, 2),
330 MTK_PIN_DRV_GRP(32, 0xf50, 8, 2),
331 MTK_PIN_DRV_GRP(33, 0xf50, 8, 2),
332 MTK_PIN_DRV_GRP(34, 0xf50, 8, 2),
333 MTK_PIN_DRV_GRP(35, 0xf50, 8, 2),
334 MTK_PIN_DRV_GRP(36, 0xf50, 8, 2),
335
336 MTK_PIN_DRV_GRP(37, 0xc40, 8, 2),
337
338 MTK_PIN_DRV_GRP(38, 0xc60, 8, 2),
339 MTK_PIN_DRV_GRP(39, 0xc60, 8, 2),
340 MTK_PIN_DRV_GRP(40, 0xc60, 8, 2),
341 MTK_PIN_DRV_GRP(41, 0xc60, 8, 2),
342 MTK_PIN_DRV_GRP(42, 0xc60, 8, 2),
343 MTK_PIN_DRV_GRP(43, 0xc60, 8, 2),
344 MTK_PIN_DRV_GRP(44, 0xc60, 8, 2),
345 MTK_PIN_DRV_GRP(45, 0xc60, 8, 2),
346
347 MTK_PIN_DRV_GRP(46, 0xc50, 8, 2),
348
349 MTK_PIN_DRV_GRP(47, 0xda0, 8, 2),
350
351 MTK_PIN_DRV_GRP(48, 0xd90, 8, 2),
352
353 MTK_PIN_DRV_GRP(49, 0xd60, 8, 2),
354 MTK_PIN_DRV_GRP(50, 0xd60, 8, 2),
355 MTK_PIN_DRV_GRP(51, 0xd60, 8, 2),
356 MTK_PIN_DRV_GRP(52, 0xd60, 8, 2),
357
358 MTK_PIN_DRV_GRP(53, 0xd50, 8, 2),
359
360 MTK_PIN_DRV_GRP(54, 0xd80, 8, 2),
361
362 MTK_PIN_DRV_GRP(55, 0xe00, 8, 2),
363
364 MTK_PIN_DRV_GRP(56, 0xd40, 8, 2),
365
366 MTK_PIN_DRV_GRP(63, 0xc80, 8, 2),
367
368 MTK_PIN_DRV_GRP(64, 0xca0, 8, 2),
369 MTK_PIN_DRV_GRP(65, 0xca0, 8, 2),
370 MTK_PIN_DRV_GRP(66, 0xca0, 8, 2),
371
372 MTK_PIN_DRV_GRP(67, 0xcd0, 8, 2),
373
374 MTK_PIN_DRV_GRP(68, 0xca0, 8, 2),
375
376 MTK_PIN_DRV_GRP(69, 0xc90, 8, 2),
377
378 MTK_PIN_DRV_GRP(70, 0xcc0, 8, 2),
379
380 MTK_PIN_DRV_GRP(71, 0xb60, 8, 1),
381 MTK_PIN_DRV_GRP(72, 0xb60, 8, 1),
382 MTK_PIN_DRV_GRP(73, 0xb60, 8, 1),
383 MTK_PIN_DRV_GRP(74, 0xb60, 8, 1),
384
385 MTK_PIN_DRV_GRP(75, 0xb60, 12, 1),
386 MTK_PIN_DRV_GRP(76, 0xb60, 12, 1),
387 MTK_PIN_DRV_GRP(77, 0xb60, 12, 1),
388
389 MTK_PIN_DRV_GRP(78, 0xb70, 0, 1),
390 MTK_PIN_DRV_GRP(79, 0xb70, 0, 1),
391 MTK_PIN_DRV_GRP(80, 0xb70, 0, 1),
392 MTK_PIN_DRV_GRP(81, 0xb70, 0, 1),
393
394 MTK_PIN_DRV_GRP(82, 0xb60, 12, 1),
395 MTK_PIN_DRV_GRP(83, 0xb60, 12, 1),
396 MTK_PIN_DRV_GRP(84, 0xb60, 12, 1),
397 MTK_PIN_DRV_GRP(85, 0xb60, 12, 1),
398 MTK_PIN_DRV_GRP(86, 0xb60, 12, 1),
399 MTK_PIN_DRV_GRP(87, 0xb60, 12, 1),
400 MTK_PIN_DRV_GRP(88, 0xb60, 12, 1),
401
402 MTK_PIN_DRV_GRP(89, 0xce0, 8, 2),
403
404 MTK_PIN_DRV_GRP(90, 0xd00, 8, 2),
405 MTK_PIN_DRV_GRP(91, 0xd00, 8, 2),
406 MTK_PIN_DRV_GRP(92, 0xd00, 8, 2),
407 MTK_PIN_DRV_GRP(93, 0xd00, 8, 2),
408
409 MTK_PIN_DRV_GRP(94, 0xd20, 8, 2),
410
411 MTK_PIN_DRV_GRP(95, 0xcf0, 8, 2),
412
413 MTK_PIN_DRV_GRP(96, 0xd30, 8, 2),
414
415 MTK_PIN_DRV_GRP(97, 0xb70, 4, 0),
416 MTK_PIN_DRV_GRP(98, 0xb70, 4, 0),
417 MTK_PIN_DRV_GRP(99, 0xb70, 4, 0),
418 MTK_PIN_DRV_GRP(100, 0xb70, 4, 0),
419
420 MTK_PIN_DRV_GRP(101, 0xb70, 8, 0),
421 MTK_PIN_DRV_GRP(102, 0xb70, 8, 0),
422 MTK_PIN_DRV_GRP(103, 0xb70, 8, 0),
423 MTK_PIN_DRV_GRP(104, 0xb70, 8, 0),
424
425 MTK_PIN_DRV_GRP(135, 0xb40, 0, 1),
426 MTK_PIN_DRV_GRP(136, 0xb40, 0, 1),
427 MTK_PIN_DRV_GRP(137, 0xb40, 0, 1),
428 MTK_PIN_DRV_GRP(138, 0xb40, 0, 1),
429 MTK_PIN_DRV_GRP(139, 0xb40, 0, 1),
430 MTK_PIN_DRV_GRP(140, 0xb40, 0, 1),
431 MTK_PIN_DRV_GRP(141, 0xb40, 0, 1),
432 MTK_PIN_DRV_GRP(142, 0xb40, 0, 1),
433
434 MTK_PIN_DRV_GRP(143, 0xba0, 12, 0),
435 MTK_PIN_DRV_GRP(144, 0xba0, 12, 0),
436 MTK_PIN_DRV_GRP(145, 0xba0, 12, 0),
437 MTK_PIN_DRV_GRP(146, 0xba0, 12, 0),
438 MTK_PIN_DRV_GRP(147, 0xba0, 12, 0),
439
440 MTK_PIN_DRV_GRP(148, 0xbb0, 0, 0),
441 MTK_PIN_DRV_GRP(149, 0xbb0, 0, 0),
442 MTK_PIN_DRV_GRP(150, 0xbb0, 0, 0),
443 MTK_PIN_DRV_GRP(151, 0xbb0, 0, 0),
444 MTK_PIN_DRV_GRP(152, 0xbb0, 0, 0),
445
446 MTK_PIN_DRV_GRP(153, 0xbb0, 4, 0),
447 MTK_PIN_DRV_GRP(154, 0xbb0, 4, 0),
448 MTK_PIN_DRV_GRP(155, 0xbb0, 4, 0),
449 MTK_PIN_DRV_GRP(156, 0xbb0, 4, 0),
450
451 MTK_PIN_DRV_GRP(157, 0xbb0, 8, 0),
452 MTK_PIN_DRV_GRP(158, 0xbb0, 8, 0),
453 MTK_PIN_DRV_GRP(159, 0xbb0, 8, 0),
454 MTK_PIN_DRV_GRP(160, 0xbb0, 8, 0),
455
456 MTK_PIN_DRV_GRP(161, 0xbb0, 12, 0),
457 MTK_PIN_DRV_GRP(162, 0xbb0, 12, 0),
458 MTK_PIN_DRV_GRP(163, 0xbb0, 12, 0),
459 MTK_PIN_DRV_GRP(164, 0xbb0, 12, 0),
460
461 MTK_PIN_DRV_GRP(165, 0xbc0, 0, 0),
462 MTK_PIN_DRV_GRP(166, 0xbc0, 0, 0),
463 MTK_PIN_DRV_GRP(167, 0xbc0, 0, 0),
464 MTK_PIN_DRV_GRP(168, 0xbc0, 0, 0),
465
466 MTK_PIN_DRV_GRP(169, 0xbc0, 4, 0),
467 MTK_PIN_DRV_GRP(170, 0xbc0, 4, 0),
468
469 MTK_PIN_DRV_GRP(171, 0xbc0, 8, 0),
470 MTK_PIN_DRV_GRP(172, 0xbc0, 8, 0),
471
472 MTK_PIN_DRV_GRP(173, 0xbc0, 12, 0),
473
474 MTK_PIN_DRV_GRP(174, 0xbd0, 0, 0),
475 MTK_PIN_DRV_GRP(175, 0xbd0, 0, 0),
476
477 MTK_PIN_DRV_GRP(176, 0xbc0, 12, 0),
478
479 MTK_PIN_DRV_GRP(177, 0xbd0, 4, 0),
480
481 MTK_PIN_DRV_GRP(178, 0xbd0, 8, 0),
482
483 MTK_PIN_DRV_GRP(179, 0xbd0, 4, 0),
484
485 MTK_PIN_DRV_GRP(180, 0xbd0, 8, 0),
486
487 MTK_PIN_DRV_GRP(181, 0xbd0, 12, 0),
488
489 MTK_PIN_DRV_GRP(182, 0xbe0, 0, 0),
490
491 MTK_PIN_DRV_GRP(183, 0xbd0, 12, 0),
492
493 MTK_PIN_DRV_GRP(184, 0xbe0, 0, 0),
494
495 MTK_PIN_DRV_GRP(185, 0xbe0, 4, 0),
496
497 MTK_PIN_DRV_GRP(186, 0xbe0, 8, 0),
498
499 MTK_PIN_DRV_GRP(187, 0xbe0, 12, 0),
500
501 MTK_PIN_DRV_GRP(188, 0xbf0, 0, 0),
502
503 MTK_PIN_DRV_GRP(189, 0xbe0, 12, 0),
504
505 MTK_PIN_DRV_GRP(190, 0xbf0, 0, 0),
506
507 MTK_PIN_DRV_GRP(191, 0xbf0, 4, 0),
508
509 MTK_PIN_DRV_GRP(192, 0xbf0, 8, 0),
510
511 MTK_PIN_DRV_GRP(193, 0xbf0, 4, 0),
512 MTK_PIN_DRV_GRP(194, 0xbf0, 4, 0),
513
514 MTK_PIN_DRV_GRP(195, 0xbf0, 8, 0),
515
516 MTK_PIN_DRV_GRP(196, 0xbf0, 12, 0),
517 MTK_PIN_DRV_GRP(197, 0xbf0, 12, 0),
518 MTK_PIN_DRV_GRP(198, 0xbf0, 12, 0),
519 MTK_PIN_DRV_GRP(199, 0xbf0, 12, 0),
520
521 MTK_PIN_DRV_GRP(200, 0xc00, 0, 0),
522 MTK_PIN_DRV_GRP(201, 0xc00, 0, 0),
523 MTK_PIN_DRV_GRP(202, 0xc00, 0, 0),
524 MTK_PIN_DRV_GRP(203, 0xc00, 0, 0),
525
526 MTK_PIN_DRV_GRP(204, 0xc00, 4, 0),
527 MTK_PIN_DRV_GRP(205, 0xc00, 4, 0),
528 MTK_PIN_DRV_GRP(206, 0xc00, 4, 0),
529
530 MTK_PIN_DRV_GRP(207, 0xc00, 8, 0),
531 MTK_PIN_DRV_GRP(208, 0xc00, 8, 0),
532 MTK_PIN_DRV_GRP(209, 0xc00, 8, 0),
533 };
534
535 static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = {
536 .pins = mtk_pins_mt2712,
537 .npins = ARRAY_SIZE(mtk_pins_mt2712),
538 .grp_desc = mt2712_drv_grp,
539 .n_grp_cls = ARRAY_SIZE(mt2712_drv_grp),
540 .pin_drv_grp = mt2712_pin_drv,
541 .n_pin_drv_grps = ARRAY_SIZE(mt2712_pin_drv),
542 .spec_ies = mt2712_ies_set,
543 .n_spec_ies = ARRAY_SIZE(mt2712_ies_set),
544 .spec_pupd = mt2712_spec_pupd,
545 .n_spec_pupd = ARRAY_SIZE(mt2712_spec_pupd),
546 .spec_smt = mt2712_smt_set,
547 .n_spec_smt = ARRAY_SIZE(mt2712_smt_set),
548 .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
549 .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
550 .dir_offset = 0x0000,
551 .pullen_offset = 0x0100,
552 .pullsel_offset = 0x0200,
553 .dout_offset = 0x0300,
554 .din_offset = 0x0400,
555 .pinmux_offset = 0x0500,
556 .type1_start = 210,
557 .type1_end = 210,
558 .port_shf = 4,
559 .port_mask = 0xf,
560 .port_align = 4,
561 .mode_mask = 0xf,
562 .mode_per_reg = 5,
563 .mode_shf = 4,
564 .eint_hw = {
565 .port_mask = 0xf,
566 .ports = 8,
567 .ap_num = 229,
568 .db_cnt = 40,
569 .db_time = debounce_time_mt2701,
570 },
571 };
572
573 static const struct of_device_id mt2712_pctrl_match[] = {
574 { .compatible = "mediatek,mt2712-pinctrl", .data = &mt2712_pinctrl_data },
575 { }
576 };
577 MODULE_DEVICE_TABLE(of, mt2712_pctrl_match);
578
579 static struct platform_driver mtk_pinctrl_driver = {
580 .probe = mtk_pctrl_common_probe,
581 .driver = {
582 .name = "mediatek-mt2712-pinctrl",
583 .of_match_table = mt2712_pctrl_match,
584 .pm = &mtk_eint_pm_ops,
585 },
586 };
587
mtk_pinctrl_init(void)588 static int __init mtk_pinctrl_init(void)
589 {
590 return platform_driver_register(&mtk_pinctrl_driver);
591 }
592
593 arch_initcall(mtk_pinctrl_init);
594
