1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2005, Intec Automation Inc.
4 * Copyright (C) 2014, Freescale Semiconductor, Inc.
5 */
6
7 #include <linux/mtd/spi-nor.h>
8
9 #include "core.h"
10
11 static int
mx25l25635_post_bfpt_fixups(struct spi_nor * nor,const struct sfdp_parameter_header * bfpt_header,const struct sfdp_bfpt * bfpt)12 mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
13 const struct sfdp_parameter_header *bfpt_header,
14 const struct sfdp_bfpt *bfpt)
15 {
16 /*
17 * MX25L25635F supports 4B opcodes but MX25L25635E does not.
18 * Unfortunately, Macronix has re-used the same JEDEC ID for both
19 * variants which prevents us from defining a new entry in the parts
20 * table.
21 * We need a way to differentiate MX25L25635E and MX25L25635F, and it
22 * seems that the F version advertises support for Fast Read 4-4-4 in
23 * its BFPT table.
24 */
25 if (bfpt->dwords[SFDP_DWORD(5)] & BFPT_DWORD5_FAST_READ_4_4_4)
26 nor->flags |= SNOR_F_4B_OPCODES;
27
28 return 0;
29 }
30
31 static const struct spi_nor_fixups mx25l25635_fixups = {
32 .post_bfpt = mx25l25635_post_bfpt_fixups,
33 };
34
35 static const struct flash_info macronix_nor_parts[] = {
36 /* Macronix */
37 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1)
38 NO_SFDP_FLAGS(SECT_4K) },
39 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4)
40 NO_SFDP_FLAGS(SECT_4K) },
41 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8)
42 NO_SFDP_FLAGS(SECT_4K) },
43 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16) },
44 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32)
45 NO_SFDP_FLAGS(SECT_4K) },
46 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64)
47 NO_SFDP_FLAGS(SECT_4K) },
48 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64)
49 NO_SFDP_FLAGS(SECT_4K) },
50 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128)
51 NO_SFDP_FLAGS(SECT_4K) },
52 { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4)
53 NO_SFDP_FLAGS(SECT_4K) },
54 { "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64)
55 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
56 SPI_NOR_QUAD_READ) },
57 { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8)
58 NO_SFDP_FLAGS(SECT_4K) },
59 { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16)
60 NO_SFDP_FLAGS(SECT_4K) },
61 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128)
62 NO_SFDP_FLAGS(SECT_4K) },
63 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256)
64 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP)
65 NO_SFDP_FLAGS(SECT_4K) },
66 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256) },
67 { "mx25r1635f", INFO(0xc22815, 0, 64 * 1024, 32)
68 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
69 SPI_NOR_QUAD_READ) },
70 { "mx25r3235f", INFO(0xc22816, 0, 64 * 1024, 64)
71 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
72 SPI_NOR_QUAD_READ) },
73 { "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256)
74 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
75 SPI_NOR_QUAD_READ) },
76 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512)
77 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
78 .fixups = &mx25l25635_fixups },
79 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512)
80 NO_SFDP_FLAGS(SECT_4K)
81 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
82 { "mx25u51245g", INFO(0xc2253a, 0, 64 * 1024, 1024)
83 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
84 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
85 { "mx25uw51245g", INFOB(0xc2813a, 0, 0, 0, 4)
86 PARSE_SFDP
87 FLAGS(SPI_NOR_RWW) },
88 { "mx25v8035f", INFO(0xc22314, 0, 64 * 1024, 16)
89 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
90 SPI_NOR_QUAD_READ) },
91 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512) },
92 { "mx66l51235f", INFO(0xc2201a, 0, 64 * 1024, 1024)
93 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
94 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
95 { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024)
96 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
97 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
98 { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048)
99 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
100 SPI_NOR_QUAD_READ) },
101 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048)
102 NO_SFDP_FLAGS(SPI_NOR_QUAD_READ) },
103 { "mx66u2g45g", INFO(0xc2253c, 0, 64 * 1024, 4096)
104 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
105 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
106 };
107
macronix_nor_default_init(struct spi_nor * nor)108 static void macronix_nor_default_init(struct spi_nor *nor)
109 {
110 nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
111 }
112
macronix_nor_late_init(struct spi_nor * nor)113 static int macronix_nor_late_init(struct spi_nor *nor)
114 {
115 if (!nor->params->set_4byte_addr_mode)
116 nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_en4b_ex4b;
117
118 return 0;
119 }
120
121 static const struct spi_nor_fixups macronix_nor_fixups = {
122 .default_init = macronix_nor_default_init,
123 .late_init = macronix_nor_late_init,
124 };
125
126 const struct spi_nor_manufacturer spi_nor_macronix = {
127 .name = "macronix",
128 .parts = macronix_nor_parts,
129 .nparts = ARRAY_SIZE(macronix_nor_parts),
130 .fixups = ¯onix_nor_fixups,
131 };
132
