1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: PC Chen <pc.chen@mediatek.com>
5 * Tiffany Lin <tiffany.lin@mediatek.com>
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/slab.h>
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_platform.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regmap.h>
19 #include <media/v4l2-event.h>
20 #include <media/v4l2-mem2mem.h>
21 #include <media/videobuf2-dma-contig.h>
22 #include <media/v4l2-device.h>
23
24 #include "mtk_vcodec_dec.h"
25 #include "mtk_vcodec_dec_hw.h"
26 #include "mtk_vcodec_dec_pm.h"
27 #include "../common/mtk_vcodec_intr.h"
28
mtk_vcodec_get_hw_count(struct mtk_vcodec_dec_ctx * ctx,struct mtk_vcodec_dec_dev * dev)29 static int mtk_vcodec_get_hw_count(struct mtk_vcodec_dec_ctx *ctx, struct mtk_vcodec_dec_dev *dev)
30 {
31 switch (dev->vdec_pdata->hw_arch) {
32 case MTK_VDEC_PURE_SINGLE_CORE:
33 return MTK_VDEC_ONE_CORE;
34 case MTK_VDEC_LAT_SINGLE_CORE:
35 return MTK_VDEC_ONE_LAT_ONE_CORE;
36 default:
37 mtk_v4l2_vdec_err(ctx, "hw arch %d not supported", dev->vdec_pdata->hw_arch);
38 return MTK_VDEC_NO_HW;
39 }
40 }
41
mtk_vcodec_is_hw_active(struct mtk_vcodec_dec_dev * dev)42 static bool mtk_vcodec_is_hw_active(struct mtk_vcodec_dec_dev *dev)
43 {
44 u32 cg_status;
45
46 if (dev->vdecsys_regmap)
47 return !regmap_test_bits(dev->vdecsys_regmap, VDEC_HW_ACTIVE_ADDR,
48 VDEC_HW_ACTIVE_MASK);
49
50 cg_status = readl(dev->reg_base[VDEC_SYS] + VDEC_HW_ACTIVE_ADDR);
51 return !FIELD_GET(VDEC_HW_ACTIVE_MASK, cg_status);
52 }
53
mtk_vcodec_dec_irq_handler(int irq,void * priv)54 static irqreturn_t mtk_vcodec_dec_irq_handler(int irq, void *priv)
55 {
56 struct mtk_vcodec_dec_dev *dev = priv;
57 struct mtk_vcodec_dec_ctx *ctx;
58 unsigned int dec_done_status = 0;
59 void __iomem *vdec_misc_addr = dev->reg_base[VDEC_MISC] +
60 VDEC_IRQ_CFG_REG;
61
62 ctx = mtk_vcodec_get_curr_ctx(dev, MTK_VDEC_CORE);
63
64 if (!mtk_vcodec_is_hw_active(dev)) {
65 mtk_v4l2_vdec_err(ctx, "DEC ISR, VDEC active is not 0x0");
66 return IRQ_HANDLED;
67 }
68
69 dec_done_status = readl(vdec_misc_addr);
70 ctx->irq_status = dec_done_status;
71 if ((dec_done_status & MTK_VDEC_IRQ_STATUS_DEC_SUCCESS) !=
72 MTK_VDEC_IRQ_STATUS_DEC_SUCCESS)
73 return IRQ_HANDLED;
74
75 /* clear interrupt */
76 writel((readl(vdec_misc_addr) | VDEC_IRQ_CFG),
77 dev->reg_base[VDEC_MISC] + VDEC_IRQ_CFG_REG);
78 writel((readl(vdec_misc_addr) & ~VDEC_IRQ_CLR),
79 dev->reg_base[VDEC_MISC] + VDEC_IRQ_CFG_REG);
80
81 wake_up_dec_ctx(ctx, MTK_INST_IRQ_RECEIVED, 0);
82
83 mtk_v4l2_vdec_dbg(3, ctx, "wake up ctx %d, dec_done_status=%x", ctx->id, dec_done_status);
84
85 return IRQ_HANDLED;
86 }
87
mtk_vcodec_get_reg_bases(struct mtk_vcodec_dec_dev * dev)88 static int mtk_vcodec_get_reg_bases(struct mtk_vcodec_dec_dev *dev)
89 {
90 struct platform_device *pdev = dev->plat_dev;
91 int reg_num, i;
92 struct resource *res;
93 bool has_vdecsys_reg;
94 int num_max_vdec_regs;
95 static const char * const mtk_dec_reg_names[] = {
96 "misc",
97 "ld",
98 "top",
99 "cm",
100 "ad",
101 "av",
102 "pp",
103 "hwd",
104 "hwq",
105 "hwb",
106 "hwg"
107 };
108
109 /*
110 * If we have reg-names in devicetree, this means that we're on a new
111 * register organization, which implies that the VDEC_SYS iospace gets
112 * R/W through a syscon (regmap).
113 * Here we try to get the "misc" iostart only to check if we have reg-names
114 */
115 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "misc");
116 if (res)
117 has_vdecsys_reg = false;
118 else
119 has_vdecsys_reg = true;
120
121 num_max_vdec_regs = has_vdecsys_reg ? NUM_MAX_VDEC_REG_BASE :
122 ARRAY_SIZE(mtk_dec_reg_names);
123
124 /* Sizeof(u32) * 4 bytes for each register base. */
125 reg_num = of_property_count_elems_of_size(pdev->dev.of_node, "reg",
126 sizeof(u32) * 4);
127 if (reg_num <= 0 || reg_num > num_max_vdec_regs) {
128 dev_err(&pdev->dev, "Invalid register property size: %d\n", reg_num);
129 return -EINVAL;
130 }
131
132 if (has_vdecsys_reg) {
133 for (i = 0; i < reg_num; i++) {
134 dev->reg_base[i] = devm_platform_ioremap_resource(pdev, i);
135 if (IS_ERR(dev->reg_base[i]))
136 return PTR_ERR(dev->reg_base[i]);
137
138 dev_dbg(&pdev->dev, "reg[%d] base=%p", i, dev->reg_base[i]);
139 }
140 } else {
141 for (i = 0; i < reg_num; i++) {
142 dev->reg_base[i+1] = devm_platform_ioremap_resource_byname(pdev, mtk_dec_reg_names[i]);
143 if (IS_ERR(dev->reg_base[i+1]))
144 return PTR_ERR(dev->reg_base[i+1]);
145
146 dev_dbg(&pdev->dev, "reg[%d] base=%p", i + 1, dev->reg_base[i + 1]);
147 }
148
149 dev->vdecsys_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
150 "mediatek,vdecsys");
151 if (IS_ERR(dev->vdecsys_regmap)) {
152 dev_err(&pdev->dev, "Missing mediatek,vdecsys property");
153 return PTR_ERR(dev->vdecsys_regmap);
154 }
155 }
156
157 return 0;
158 }
159
mtk_vcodec_init_dec_resources(struct mtk_vcodec_dec_dev * dev)160 static int mtk_vcodec_init_dec_resources(struct mtk_vcodec_dec_dev *dev)
161 {
162 struct platform_device *pdev = dev->plat_dev;
163 int ret;
164
165 ret = mtk_vcodec_get_reg_bases(dev);
166 if (ret)
167 return ret;
168
169 if (dev->vdec_pdata->is_subdev_supported)
170 return 0;
171
172 dev->dec_irq = platform_get_irq(pdev, 0);
173 if (dev->dec_irq < 0)
174 return dev->dec_irq;
175
176 irq_set_status_flags(dev->dec_irq, IRQ_NOAUTOEN);
177 ret = devm_request_irq(&pdev->dev, dev->dec_irq,
178 mtk_vcodec_dec_irq_handler, 0, pdev->name, dev);
179 if (ret) {
180 dev_err(&pdev->dev, "failed to install dev->dec_irq %d (%d)",
181 dev->dec_irq, ret);
182 return ret;
183 }
184
185 ret = mtk_vcodec_init_dec_clk(pdev, &dev->pm);
186 if (ret < 0) {
187 dev_err(&pdev->dev, "failed to get mt vcodec clock source");
188 return ret;
189 }
190
191 pm_runtime_enable(&pdev->dev);
192 return 0;
193 }
194
fops_vcodec_open(struct file * file)195 static int fops_vcodec_open(struct file *file)
196 {
197 struct mtk_vcodec_dec_dev *dev = video_drvdata(file);
198 struct mtk_vcodec_dec_ctx *ctx = NULL;
199 int ret = 0, i, hw_count;
200 struct vb2_queue *src_vq;
201
202 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
203 if (!ctx)
204 return -ENOMEM;
205
206 mutex_lock(&dev->dev_mutex);
207 ctx->id = dev->id_counter++;
208 v4l2_fh_init(&ctx->fh, video_devdata(file));
209 file->private_data = &ctx->fh;
210 v4l2_fh_add(&ctx->fh);
211 INIT_LIST_HEAD(&ctx->list);
212 ctx->dev = dev;
213 if (ctx->dev->vdec_pdata->is_subdev_supported) {
214 hw_count = mtk_vcodec_get_hw_count(ctx, dev);
215 if (!hw_count || !dev->subdev_prob_done) {
216 ret = -EINVAL;
217 goto err_ctrls_setup;
218 }
219
220 ret = dev->subdev_prob_done(dev);
221 if (ret)
222 goto err_ctrls_setup;
223
224 for (i = 0; i < hw_count; i++)
225 init_waitqueue_head(&ctx->queue[i]);
226 } else {
227 init_waitqueue_head(&ctx->queue[0]);
228 }
229 mutex_init(&ctx->lock);
230
231 ctx->type = MTK_INST_DECODER;
232 ret = dev->vdec_pdata->ctrls_setup(ctx);
233 if (ret) {
234 mtk_v4l2_vdec_err(ctx, "Failed to setup mt vcodec controls");
235 goto err_ctrls_setup;
236 }
237 ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev_dec, ctx,
238 &mtk_vcodec_dec_queue_init);
239 if (IS_ERR((__force void *)ctx->m2m_ctx)) {
240 ret = PTR_ERR((__force void *)ctx->m2m_ctx);
241 mtk_v4l2_vdec_err(ctx, "Failed to v4l2_m2m_ctx_init() (%d)", ret);
242 goto err_m2m_ctx_init;
243 }
244 src_vq = v4l2_m2m_get_vq(ctx->m2m_ctx,
245 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
246 ctx->empty_flush_buf.vb.vb2_buf.vb2_queue = src_vq;
247 mtk_vcodec_dec_set_default_params(ctx);
248
249 if (v4l2_fh_is_singular(&ctx->fh)) {
250 /*
251 * Does nothing if firmware was already loaded.
252 */
253 ret = mtk_vcodec_fw_load_firmware(dev->fw_handler);
254 if (ret < 0) {
255 /*
256 * Return 0 if downloading firmware successfully,
257 * otherwise it is failed
258 */
259 mtk_v4l2_vdec_err(ctx, "failed to load firmware!");
260 goto err_load_fw;
261 }
262
263 dev->dec_capability =
264 mtk_vcodec_fw_get_vdec_capa(dev->fw_handler);
265
266 mtk_v4l2_vdec_dbg(0, ctx, "decoder capability %x", dev->dec_capability);
267 }
268
269 ctx->dev->vdec_pdata->init_vdec_params(ctx);
270
271 list_add(&ctx->list, &dev->ctx_list);
272 mtk_vcodec_dbgfs_create(ctx);
273
274 mutex_unlock(&dev->dev_mutex);
275 mtk_v4l2_vdec_dbg(0, ctx, "%s decoder [%d]", dev_name(&dev->plat_dev->dev), ctx->id);
276 return ret;
277
278 /* Deinit when failure occurred */
279 err_load_fw:
280 v4l2_m2m_ctx_release(ctx->m2m_ctx);
281 err_m2m_ctx_init:
282 v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
283 err_ctrls_setup:
284 v4l2_fh_del(&ctx->fh);
285 v4l2_fh_exit(&ctx->fh);
286 kfree(ctx);
287 mutex_unlock(&dev->dev_mutex);
288
289 return ret;
290 }
291
fops_vcodec_release(struct file * file)292 static int fops_vcodec_release(struct file *file)
293 {
294 struct mtk_vcodec_dec_dev *dev = video_drvdata(file);
295 struct mtk_vcodec_dec_ctx *ctx = fh_to_dec_ctx(file->private_data);
296
297 mtk_v4l2_vdec_dbg(0, ctx, "[%d] decoder", ctx->id);
298 mutex_lock(&dev->dev_mutex);
299
300 /*
301 * Call v4l2_m2m_ctx_release before mtk_vcodec_dec_release. First, it
302 * makes sure the worker thread is not running after vdec_if_deinit.
303 * Second, the decoder will be flushed and all the buffers will be
304 * returned in stop_streaming.
305 */
306 v4l2_m2m_ctx_release(ctx->m2m_ctx);
307 mtk_vcodec_dec_release(ctx);
308
309 v4l2_fh_del(&ctx->fh);
310 v4l2_fh_exit(&ctx->fh);
311 v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
312
313 mtk_vcodec_dbgfs_remove(dev, ctx->id);
314 list_del_init(&ctx->list);
315 kfree(ctx);
316 mutex_unlock(&dev->dev_mutex);
317 return 0;
318 }
319
320 static const struct v4l2_file_operations mtk_vcodec_fops = {
321 .owner = THIS_MODULE,
322 .open = fops_vcodec_open,
323 .release = fops_vcodec_release,
324 .poll = v4l2_m2m_fop_poll,
325 .unlocked_ioctl = video_ioctl2,
326 .mmap = v4l2_m2m_fop_mmap,
327 };
328
mtk_vcodec_probe(struct platform_device * pdev)329 static int mtk_vcodec_probe(struct platform_device *pdev)
330 {
331 struct mtk_vcodec_dec_dev *dev;
332 struct video_device *vfd_dec;
333 phandle rproc_phandle;
334 enum mtk_vcodec_fw_type fw_type;
335 int i, ret;
336
337 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
338 if (!dev)
339 return -ENOMEM;
340
341 INIT_LIST_HEAD(&dev->ctx_list);
342 dev->plat_dev = pdev;
343
344 dev->vdec_pdata = of_device_get_match_data(&pdev->dev);
345 if (!of_property_read_u32(pdev->dev.of_node, "mediatek,vpu",
346 &rproc_phandle)) {
347 fw_type = VPU;
348 } else if (!of_property_read_u32(pdev->dev.of_node, "mediatek,scp",
349 &rproc_phandle)) {
350 fw_type = SCP;
351 } else {
352 dev_dbg(&pdev->dev, "Could not get vdec IPI device");
353 return -ENODEV;
354 }
355 dma_set_max_seg_size(&pdev->dev, UINT_MAX);
356
357 dev->fw_handler = mtk_vcodec_fw_select(dev, fw_type, DECODER);
358 if (IS_ERR(dev->fw_handler))
359 return PTR_ERR(dev->fw_handler);
360
361 ret = mtk_vcodec_init_dec_resources(dev);
362 if (ret) {
363 dev_err(&pdev->dev, "Failed to init dec resources");
364 goto err_dec_pm;
365 }
366
367 if (IS_VDEC_LAT_ARCH(dev->vdec_pdata->hw_arch)) {
368 dev->core_workqueue =
369 alloc_ordered_workqueue("core-decoder",
370 WQ_MEM_RECLAIM | WQ_FREEZABLE);
371 if (!dev->core_workqueue) {
372 dev_dbg(&pdev->dev, "Failed to create core workqueue");
373 ret = -EINVAL;
374 goto err_res;
375 }
376 }
377
378 for (i = 0; i < MTK_VDEC_HW_MAX; i++)
379 mutex_init(&dev->dec_mutex[i]);
380 mutex_init(&dev->dev_mutex);
381 spin_lock_init(&dev->irqlock);
382
383 snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name), "%s",
384 "[/MTK_V4L2_VDEC]");
385
386 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
387 if (ret) {
388 dev_err(&pdev->dev, "v4l2_device_register err=%d", ret);
389 goto err_core_workq;
390 }
391
392 vfd_dec = video_device_alloc();
393 if (!vfd_dec) {
394 dev_err(&pdev->dev, "Failed to allocate video device");
395 ret = -ENOMEM;
396 goto err_dec_alloc;
397 }
398 vfd_dec->fops = &mtk_vcodec_fops;
399 vfd_dec->ioctl_ops = &mtk_vdec_ioctl_ops;
400 vfd_dec->release = video_device_release;
401 vfd_dec->lock = &dev->dev_mutex;
402 vfd_dec->v4l2_dev = &dev->v4l2_dev;
403 vfd_dec->vfl_dir = VFL_DIR_M2M;
404 vfd_dec->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE |
405 V4L2_CAP_STREAMING;
406
407 snprintf(vfd_dec->name, sizeof(vfd_dec->name), "%s",
408 MTK_VCODEC_DEC_NAME);
409 video_set_drvdata(vfd_dec, dev);
410 dev->vfd_dec = vfd_dec;
411 platform_set_drvdata(pdev, dev);
412
413 dev->m2m_dev_dec = v4l2_m2m_init(&mtk_vdec_m2m_ops);
414 if (IS_ERR((__force void *)dev->m2m_dev_dec)) {
415 dev_err(&pdev->dev, "Failed to init mem2mem dec device");
416 ret = PTR_ERR((__force void *)dev->m2m_dev_dec);
417 goto err_dec_alloc;
418 }
419
420 dev->decode_workqueue =
421 alloc_ordered_workqueue(MTK_VCODEC_DEC_NAME,
422 WQ_MEM_RECLAIM | WQ_FREEZABLE);
423 if (!dev->decode_workqueue) {
424 dev_err(&pdev->dev, "Failed to create decode workqueue");
425 ret = -EINVAL;
426 goto err_event_workq;
427 }
428
429 if (dev->vdec_pdata->is_subdev_supported) {
430 ret = of_platform_populate(pdev->dev.of_node, NULL, NULL,
431 &pdev->dev);
432 if (ret) {
433 dev_err(&pdev->dev, "Main device of_platform_populate failed.");
434 goto err_reg_cont;
435 }
436 } else {
437 set_bit(MTK_VDEC_CORE, dev->subdev_bitmap);
438 }
439
440 atomic_set(&dev->dec_active_cnt, 0);
441 memset(dev->vdec_racing_info, 0, sizeof(dev->vdec_racing_info));
442 mutex_init(&dev->dec_racing_info_mutex);
443
444 ret = video_register_device(vfd_dec, VFL_TYPE_VIDEO, -1);
445 if (ret) {
446 dev_err(&pdev->dev, "Failed to register video device");
447 goto err_reg_cont;
448 }
449
450 if (dev->vdec_pdata->uses_stateless_api) {
451 v4l2_disable_ioctl(vfd_dec, VIDIOC_DECODER_CMD);
452 v4l2_disable_ioctl(vfd_dec, VIDIOC_TRY_DECODER_CMD);
453
454 dev->mdev_dec.dev = &pdev->dev;
455 strscpy(dev->mdev_dec.model, MTK_VCODEC_DEC_NAME,
456 sizeof(dev->mdev_dec.model));
457
458 media_device_init(&dev->mdev_dec);
459 dev->mdev_dec.ops = &mtk_vcodec_media_ops;
460 dev->v4l2_dev.mdev = &dev->mdev_dec;
461
462 ret = v4l2_m2m_register_media_controller(dev->m2m_dev_dec, dev->vfd_dec,
463 MEDIA_ENT_F_PROC_VIDEO_DECODER);
464 if (ret) {
465 dev_err(&pdev->dev, "Failed to register media controller");
466 goto err_dec_mem_init;
467 }
468
469 ret = media_device_register(&dev->mdev_dec);
470 if (ret) {
471 dev_err(&pdev->dev, "Failed to register media device");
472 goto err_media_reg;
473 }
474
475 dev_dbg(&pdev->dev, "media registered as /dev/media%d", vfd_dec->minor);
476 }
477
478 mtk_vcodec_dbgfs_init(dev, false);
479 dev_dbg(&pdev->dev, "decoder registered as /dev/video%d", vfd_dec->minor);
480
481 return 0;
482
483 err_media_reg:
484 v4l2_m2m_unregister_media_controller(dev->m2m_dev_dec);
485 err_dec_mem_init:
486 video_unregister_device(vfd_dec);
487 err_reg_cont:
488 if (dev->vdec_pdata->uses_stateless_api)
489 media_device_cleanup(&dev->mdev_dec);
490 destroy_workqueue(dev->decode_workqueue);
491 err_event_workq:
492 v4l2_m2m_release(dev->m2m_dev_dec);
493 err_dec_alloc:
494 v4l2_device_unregister(&dev->v4l2_dev);
495 err_core_workq:
496 if (IS_VDEC_LAT_ARCH(dev->vdec_pdata->hw_arch))
497 destroy_workqueue(dev->core_workqueue);
498 err_res:
499 if (!dev->vdec_pdata->is_subdev_supported)
500 pm_runtime_disable(dev->pm.dev);
501 err_dec_pm:
502 mtk_vcodec_fw_release(dev->fw_handler);
503 return ret;
504 }
505
506 static const struct of_device_id mtk_vcodec_match[] = {
507 {
508 .compatible = "mediatek,mt8173-vcodec-dec",
509 .data = &mtk_vdec_8173_pdata,
510 },
511 {
512 .compatible = "mediatek,mt8183-vcodec-dec",
513 .data = &mtk_vdec_8183_pdata,
514 },
515 {
516 .compatible = "mediatek,mt8192-vcodec-dec",
517 .data = &mtk_lat_sig_core_pdata,
518 },
519 {
520 .compatible = "mediatek,mt8186-vcodec-dec",
521 .data = &mtk_vdec_single_core_pdata,
522 },
523 {
524 .compatible = "mediatek,mt8195-vcodec-dec",
525 .data = &mtk_lat_sig_core_pdata,
526 },
527 {
528 .compatible = "mediatek,mt8188-vcodec-dec",
529 .data = &mtk_lat_sig_core_pdata,
530 },
531 {},
532 };
533
534 MODULE_DEVICE_TABLE(of, mtk_vcodec_match);
535
mtk_vcodec_dec_remove(struct platform_device * pdev)536 static void mtk_vcodec_dec_remove(struct platform_device *pdev)
537 {
538 struct mtk_vcodec_dec_dev *dev = platform_get_drvdata(pdev);
539
540 destroy_workqueue(dev->decode_workqueue);
541
542 if (media_devnode_is_registered(dev->mdev_dec.devnode)) {
543 media_device_unregister(&dev->mdev_dec);
544 v4l2_m2m_unregister_media_controller(dev->m2m_dev_dec);
545 media_device_cleanup(&dev->mdev_dec);
546 }
547
548 if (dev->m2m_dev_dec)
549 v4l2_m2m_release(dev->m2m_dev_dec);
550
551 if (dev->vfd_dec)
552 video_unregister_device(dev->vfd_dec);
553
554 mtk_vcodec_dbgfs_deinit(&dev->dbgfs);
555 v4l2_device_unregister(&dev->v4l2_dev);
556 if (!dev->vdec_pdata->is_subdev_supported)
557 pm_runtime_disable(dev->pm.dev);
558 mtk_vcodec_fw_release(dev->fw_handler);
559 }
560
561 static struct platform_driver mtk_vcodec_dec_driver = {
562 .probe = mtk_vcodec_probe,
563 .remove_new = mtk_vcodec_dec_remove,
564 .driver = {
565 .name = MTK_VCODEC_DEC_NAME,
566 .of_match_table = mtk_vcodec_match,
567 },
568 };
569
570 module_platform_driver(mtk_vcodec_dec_driver);
571
572 MODULE_LICENSE("GPL v2");
573 MODULE_DESCRIPTION("Mediatek video codec V4L2 decoder driver");
574
