1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
4 * processor hardware monitoring
5 *
6 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
7 * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
8 *
9 * Implementation notes:
10 * - CCD register address information as well as the calculation to
11 * convert raw register values is from https://github.com/ocerman/zenpower.
12 * The information is not confirmed from chip datasheets, but experiments
13 * suggest that it provides reasonable temperature values.
14 */
15
16 #include <linux/bitops.h>
17 #include <linux/err.h>
18 #include <linux/hwmon.h>
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/pci_ids.h>
23 #include <asm/amd_nb.h>
24 #include <asm/processor.h>
25
26 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
27 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
28 MODULE_LICENSE("GPL");
29
30 static bool force;
31 module_param(force, bool, 0444);
32 MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
33
34 /* Provide lock for writing to NB_SMU_IND_ADDR */
35 static DEFINE_MUTEX(nb_smu_ind_mutex);
36
37 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
38 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
39 #endif
40
41 /* CPUID function 0x80000001, ebx */
42 #define CPUID_PKGTYPE_MASK GENMASK(31, 28)
43 #define CPUID_PKGTYPE_F 0x00000000
44 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
45
46 /* DRAM controller (PCI function 2) */
47 #define REG_DCT0_CONFIG_HIGH 0x094
48 #define DDR3_MODE BIT(8)
49
50 /* miscellaneous (PCI function 3) */
51 #define REG_HARDWARE_THERMAL_CONTROL 0x64
52 #define HTC_ENABLE BIT(0)
53
54 #define REG_REPORTED_TEMPERATURE 0xa4
55
56 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8
57 #define NB_CAP_HTC BIT(10)
58
59 /*
60 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
61 * and REG_REPORTED_TEMPERATURE have been moved to
62 * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
63 * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
64 */
65 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
66 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
67
68 /* Common for Zen CPU families (Family 17h and 18h and 19h and 1Ah) */
69 #define ZEN_REPORTED_TEMP_CTRL_BASE 0x00059800
70
71 #define ZEN_CCD_TEMP(offset, x) (ZEN_REPORTED_TEMP_CTRL_BASE + \
72 (offset) + ((x) * 4))
73 #define ZEN_CCD_TEMP_VALID BIT(11)
74 #define ZEN_CCD_TEMP_MASK GENMASK(10, 0)
75
76 #define ZEN_CUR_TEMP_SHIFT 21
77 #define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19)
78 #define ZEN_CUR_TEMP_TJ_SEL_MASK GENMASK(17, 16)
79
80 /*
81 * AMD's Industrial processor 3255 supports temperature from -40 deg to 105 deg Celsius.
82 * Use the model name to identify 3255 CPUs and set a flag to display negative temperature.
83 * Do not round off to zero for negative Tctl or Tdie values if the flag is set
84 */
85 #define AMD_I3255_STR "3255"
86
87 struct k10temp_data {
88 struct pci_dev *pdev;
89 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
90 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
91 int temp_offset;
92 u32 temp_adjust_mask;
93 u32 show_temp;
94 bool is_zen;
95 u32 ccd_offset;
96 bool disp_negative;
97 };
98
99 #define TCTL_BIT 0
100 #define TDIE_BIT 1
101 #define TCCD_BIT(x) ((x) + 2)
102
103 #define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel))
104 #define HAVE_TDIE(d) HAVE_TEMP(d, TDIE_BIT)
105
106 struct tctl_offset {
107 u8 model;
108 char const *id;
109 int offset;
110 };
111
112 static const struct tctl_offset tctl_offset_table[] = {
113 { 0x17, "AMD Ryzen 5 1600X", 20000 },
114 { 0x17, "AMD Ryzen 7 1700X", 20000 },
115 { 0x17, "AMD Ryzen 7 1800X", 20000 },
116 { 0x17, "AMD Ryzen 7 2700X", 10000 },
117 { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
118 { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
119 };
120
read_htcreg_pci(struct pci_dev * pdev,u32 * regval)121 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
122 {
123 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
124 }
125
read_tempreg_pci(struct pci_dev * pdev,u32 * regval)126 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
127 {
128 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
129 }
130
amd_nb_index_read(struct pci_dev * pdev,unsigned int devfn,unsigned int base,int offset,u32 * val)131 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
132 unsigned int base, int offset, u32 *val)
133 {
134 mutex_lock(&nb_smu_ind_mutex);
135 pci_bus_write_config_dword(pdev->bus, devfn,
136 base, offset);
137 pci_bus_read_config_dword(pdev->bus, devfn,
138 base + 4, val);
139 mutex_unlock(&nb_smu_ind_mutex);
140 }
141
read_htcreg_nb_f15(struct pci_dev * pdev,u32 * regval)142 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
143 {
144 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
145 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
146 }
147
read_tempreg_nb_f15(struct pci_dev * pdev,u32 * regval)148 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
149 {
150 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
151 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
152 }
153
read_tempreg_nb_zen(struct pci_dev * pdev,u32 * regval)154 static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval)
155 {
156 amd_smn_read(amd_pci_dev_to_node_id(pdev),
157 ZEN_REPORTED_TEMP_CTRL_BASE, regval);
158 }
159
get_raw_temp(struct k10temp_data * data)160 static long get_raw_temp(struct k10temp_data *data)
161 {
162 u32 regval;
163 long temp;
164
165 data->read_tempreg(data->pdev, ®val);
166 temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125;
167 if ((regval & data->temp_adjust_mask) ||
168 (regval & ZEN_CUR_TEMP_TJ_SEL_MASK) == ZEN_CUR_TEMP_TJ_SEL_MASK)
169 temp -= 49000;
170 return temp;
171 }
172
173 static const char *k10temp_temp_label[] = {
174 "Tctl",
175 "Tdie",
176 "Tccd1",
177 "Tccd2",
178 "Tccd3",
179 "Tccd4",
180 "Tccd5",
181 "Tccd6",
182 "Tccd7",
183 "Tccd8",
184 "Tccd9",
185 "Tccd10",
186 "Tccd11",
187 "Tccd12",
188 };
189
k10temp_read_labels(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,const char ** str)190 static int k10temp_read_labels(struct device *dev,
191 enum hwmon_sensor_types type,
192 u32 attr, int channel, const char **str)
193 {
194 switch (type) {
195 case hwmon_temp:
196 *str = k10temp_temp_label[channel];
197 break;
198 default:
199 return -EOPNOTSUPP;
200 }
201 return 0;
202 }
203
k10temp_read_temp(struct device * dev,u32 attr,int channel,long * val)204 static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
205 long *val)
206 {
207 struct k10temp_data *data = dev_get_drvdata(dev);
208 u32 regval;
209
210 switch (attr) {
211 case hwmon_temp_input:
212 switch (channel) {
213 case 0: /* Tctl */
214 *val = get_raw_temp(data);
215 if (*val < 0 && !data->disp_negative)
216 *val = 0;
217 break;
218 case 1: /* Tdie */
219 *val = get_raw_temp(data) - data->temp_offset;
220 if (*val < 0 && !data->disp_negative)
221 *val = 0;
222 break;
223 case 2 ... 13: /* Tccd{1-12} */
224 amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
225 ZEN_CCD_TEMP(data->ccd_offset, channel - 2),
226 ®val);
227 *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000;
228 break;
229 default:
230 return -EOPNOTSUPP;
231 }
232 break;
233 case hwmon_temp_max:
234 *val = 70 * 1000;
235 break;
236 case hwmon_temp_crit:
237 data->read_htcreg(data->pdev, ®val);
238 *val = ((regval >> 16) & 0x7f) * 500 + 52000;
239 break;
240 case hwmon_temp_crit_hyst:
241 data->read_htcreg(data->pdev, ®val);
242 *val = (((regval >> 16) & 0x7f)
243 - ((regval >> 24) & 0xf)) * 500 + 52000;
244 break;
245 default:
246 return -EOPNOTSUPP;
247 }
248 return 0;
249 }
250
k10temp_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)251 static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
252 u32 attr, int channel, long *val)
253 {
254 switch (type) {
255 case hwmon_temp:
256 return k10temp_read_temp(dev, attr, channel, val);
257 default:
258 return -EOPNOTSUPP;
259 }
260 }
261
k10temp_is_visible(const void * _data,enum hwmon_sensor_types type,u32 attr,int channel)262 static umode_t k10temp_is_visible(const void *_data,
263 enum hwmon_sensor_types type,
264 u32 attr, int channel)
265 {
266 const struct k10temp_data *data = _data;
267 struct pci_dev *pdev = data->pdev;
268 u32 reg;
269
270 switch (type) {
271 case hwmon_temp:
272 switch (attr) {
273 case hwmon_temp_input:
274 if (!HAVE_TEMP(data, channel))
275 return 0;
276 break;
277 case hwmon_temp_max:
278 if (channel || data->is_zen)
279 return 0;
280 break;
281 case hwmon_temp_crit:
282 case hwmon_temp_crit_hyst:
283 if (channel || !data->read_htcreg)
284 return 0;
285
286 pci_read_config_dword(pdev,
287 REG_NORTHBRIDGE_CAPABILITIES,
288 ®);
289 if (!(reg & NB_CAP_HTC))
290 return 0;
291
292 data->read_htcreg(data->pdev, ®);
293 if (!(reg & HTC_ENABLE))
294 return 0;
295 break;
296 case hwmon_temp_label:
297 /* Show temperature labels only on Zen CPUs */
298 if (!data->is_zen || !HAVE_TEMP(data, channel))
299 return 0;
300 break;
301 default:
302 return 0;
303 }
304 break;
305 default:
306 return 0;
307 }
308 return 0444;
309 }
310
has_erratum_319(struct pci_dev * pdev)311 static bool has_erratum_319(struct pci_dev *pdev)
312 {
313 u32 pkg_type, reg_dram_cfg;
314
315 if (boot_cpu_data.x86 != 0x10)
316 return false;
317
318 /*
319 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
320 * may be unreliable.
321 */
322 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
323 if (pkg_type == CPUID_PKGTYPE_F)
324 return true;
325 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
326 return false;
327
328 /* DDR3 memory implies socket AM3, which is good */
329 pci_bus_read_config_dword(pdev->bus,
330 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
331 REG_DCT0_CONFIG_HIGH, ®_dram_cfg);
332 if (reg_dram_cfg & DDR3_MODE)
333 return false;
334
335 /*
336 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
337 * memory. We blacklist all the cores which do exist in socket AM2+
338 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
339 * and AM3 formats, but that's the best we can do.
340 */
341 return boot_cpu_data.x86_model < 4 ||
342 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
343 }
344
345 static const struct hwmon_channel_info * const k10temp_info[] = {
346 HWMON_CHANNEL_INFO(temp,
347 HWMON_T_INPUT | HWMON_T_MAX |
348 HWMON_T_CRIT | HWMON_T_CRIT_HYST |
349 HWMON_T_LABEL,
350 HWMON_T_INPUT | HWMON_T_LABEL,
351 HWMON_T_INPUT | HWMON_T_LABEL,
352 HWMON_T_INPUT | HWMON_T_LABEL,
353 HWMON_T_INPUT | HWMON_T_LABEL,
354 HWMON_T_INPUT | HWMON_T_LABEL,
355 HWMON_T_INPUT | HWMON_T_LABEL,
356 HWMON_T_INPUT | HWMON_T_LABEL,
357 HWMON_T_INPUT | HWMON_T_LABEL,
358 HWMON_T_INPUT | HWMON_T_LABEL,
359 HWMON_T_INPUT | HWMON_T_LABEL,
360 HWMON_T_INPUT | HWMON_T_LABEL,
361 HWMON_T_INPUT | HWMON_T_LABEL,
362 HWMON_T_INPUT | HWMON_T_LABEL),
363 NULL
364 };
365
366 static const struct hwmon_ops k10temp_hwmon_ops = {
367 .is_visible = k10temp_is_visible,
368 .read = k10temp_read,
369 .read_string = k10temp_read_labels,
370 };
371
372 static const struct hwmon_chip_info k10temp_chip_info = {
373 .ops = &k10temp_hwmon_ops,
374 .info = k10temp_info,
375 };
376
k10temp_get_ccd_support(struct pci_dev * pdev,struct k10temp_data * data,int limit)377 static void k10temp_get_ccd_support(struct pci_dev *pdev,
378 struct k10temp_data *data, int limit)
379 {
380 u32 regval;
381 int i;
382
383 for (i = 0; i < limit; i++) {
384 amd_smn_read(amd_pci_dev_to_node_id(pdev),
385 ZEN_CCD_TEMP(data->ccd_offset, i), ®val);
386 if (regval & ZEN_CCD_TEMP_VALID)
387 data->show_temp |= BIT(TCCD_BIT(i));
388 }
389 }
390
k10temp_probe(struct pci_dev * pdev,const struct pci_device_id * id)391 static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
392 {
393 int unreliable = has_erratum_319(pdev);
394 struct device *dev = &pdev->dev;
395 struct k10temp_data *data;
396 struct device *hwmon_dev;
397 int i;
398
399 if (unreliable) {
400 if (!force) {
401 dev_err(dev,
402 "unreliable CPU thermal sensor; monitoring disabled\n");
403 return -ENODEV;
404 }
405 dev_warn(dev,
406 "unreliable CPU thermal sensor; check erratum 319\n");
407 }
408
409 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
410 if (!data)
411 return -ENOMEM;
412
413 data->pdev = pdev;
414 data->show_temp |= BIT(TCTL_BIT); /* Always show Tctl */
415
416 if (boot_cpu_data.x86 == 0x17 &&
417 strstr(boot_cpu_data.x86_model_id, AMD_I3255_STR)) {
418 data->disp_negative = true;
419 }
420
421 if (boot_cpu_data.x86 == 0x15 &&
422 ((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
423 (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
424 data->read_htcreg = read_htcreg_nb_f15;
425 data->read_tempreg = read_tempreg_nb_f15;
426 } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
427 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
428 data->read_tempreg = read_tempreg_nb_zen;
429 data->is_zen = true;
430
431 switch (boot_cpu_data.x86_model) {
432 case 0x1: /* Zen */
433 case 0x8: /* Zen+ */
434 case 0x11: /* Zen APU */
435 case 0x18: /* Zen+ APU */
436 data->ccd_offset = 0x154;
437 k10temp_get_ccd_support(pdev, data, 4);
438 break;
439 case 0x31: /* Zen2 Threadripper */
440 case 0x60: /* Renoir */
441 case 0x68: /* Lucienne */
442 case 0x71: /* Zen2 */
443 data->ccd_offset = 0x154;
444 k10temp_get_ccd_support(pdev, data, 8);
445 break;
446 case 0xa0 ... 0xaf:
447 data->ccd_offset = 0x300;
448 k10temp_get_ccd_support(pdev, data, 8);
449 break;
450 }
451 } else if (boot_cpu_data.x86 == 0x19) {
452 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
453 data->read_tempreg = read_tempreg_nb_zen;
454 data->is_zen = true;
455
456 switch (boot_cpu_data.x86_model) {
457 case 0x0 ... 0x1: /* Zen3 SP3/TR */
458 case 0x21: /* Zen3 Ryzen Desktop */
459 case 0x50 ... 0x5f: /* Green Sardine */
460 data->ccd_offset = 0x154;
461 k10temp_get_ccd_support(pdev, data, 8);
462 break;
463 case 0x40 ... 0x4f: /* Yellow Carp */
464 data->ccd_offset = 0x300;
465 k10temp_get_ccd_support(pdev, data, 8);
466 break;
467 case 0x60 ... 0x6f:
468 case 0x70 ... 0x7f:
469 data->ccd_offset = 0x308;
470 k10temp_get_ccd_support(pdev, data, 8);
471 break;
472 case 0x10 ... 0x1f:
473 case 0xa0 ... 0xaf:
474 data->ccd_offset = 0x300;
475 k10temp_get_ccd_support(pdev, data, 12);
476 break;
477 }
478 } else if (boot_cpu_data.x86 == 0x1a) {
479 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
480 data->read_tempreg = read_tempreg_nb_zen;
481 data->is_zen = true;
482 } else {
483 data->read_htcreg = read_htcreg_pci;
484 data->read_tempreg = read_tempreg_pci;
485 }
486
487 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
488 const struct tctl_offset *entry = &tctl_offset_table[i];
489
490 if (boot_cpu_data.x86 == entry->model &&
491 strstr(boot_cpu_data.x86_model_id, entry->id)) {
492 data->show_temp |= BIT(TDIE_BIT); /* show Tdie */
493 data->temp_offset = entry->offset;
494 break;
495 }
496 }
497
498 hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
499 &k10temp_chip_info,
500 NULL);
501 return PTR_ERR_OR_ZERO(hwmon_dev);
502 }
503
504 static const struct pci_device_id k10temp_id_table[] = {
505 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
506 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
507 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
508 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
509 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
510 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
511 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
512 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
513 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
514 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
515 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
516 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
517 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
518 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
519 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
520 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) },
521 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
522 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
523 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
524 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
525 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
526 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
527 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) },
528 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) },
529 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) },
530 { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
531 {}
532 };
533 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
534
535 static struct pci_driver k10temp_driver = {
536 .name = "k10temp",
537 .id_table = k10temp_id_table,
538 .probe = k10temp_probe,
539 };
540
541 module_pci_driver(k10temp_driver);
542
