1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. 5 * 6 * Parts of this file were based on sources as follows: 7 * 8 * Copyright (c) 2006-2008 Intel Corporation 9 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie> 10 * Copyright (C) 2011 Texas Instruments 11 */ 12 13 #ifndef _PL111_DRM_H_ 14 #define _PL111_DRM_H_ 15 16 #include <linux/clk-provider.h> 17 #include <linux/interrupt.h> 18 19 #include <drm/drm_bridge.h> 20 #include <drm/drm_connector.h> 21 #include <drm/drm_encoder.h> 22 #include <drm/drm_gem.h> 23 #include <drm/drm_panel.h> 24 #include <drm/drm_simple_kms_helper.h> 25 26 /* 27 * CLCD Controller Internal Register addresses 28 */ 29 #define CLCD_TIM0 0x00000000 30 #define CLCD_TIM1 0x00000004 31 #define CLCD_TIM2 0x00000008 32 #define CLCD_TIM3 0x0000000c 33 #define CLCD_UBAS 0x00000010 34 #define CLCD_LBAS 0x00000014 35 36 #define CLCD_PL110_IENB 0x00000018 37 #define CLCD_PL110_CNTL 0x0000001c 38 #define CLCD_PL110_STAT 0x00000020 39 #define CLCD_PL110_INTR 0x00000024 40 #define CLCD_PL110_UCUR 0x00000028 41 #define CLCD_PL110_LCUR 0x0000002C 42 43 #define CLCD_PL111_CNTL 0x00000018 44 #define CLCD_PL111_IENB 0x0000001c 45 #define CLCD_PL111_RIS 0x00000020 46 #define CLCD_PL111_MIS 0x00000024 47 #define CLCD_PL111_ICR 0x00000028 48 #define CLCD_PL111_UCUR 0x0000002c 49 #define CLCD_PL111_LCUR 0x00000030 50 51 #define CLCD_PALL 0x00000200 52 #define CLCD_PALETTE 0x00000200 53 54 #define TIM2_PCD_LO_MASK GENMASK(4, 0) 55 #define TIM2_PCD_LO_BITS 5 56 #define TIM2_CLKSEL (1 << 5) 57 #define TIM2_ACB_MASK GENMASK(10, 6) 58 #define TIM2_IVS (1 << 11) 59 #define TIM2_IHS (1 << 12) 60 #define TIM2_IPC (1 << 13) 61 #define TIM2_IOE (1 << 14) 62 #define TIM2_BCD (1 << 26) 63 #define TIM2_PCD_HI_MASK GENMASK(31, 27) 64 #define TIM2_PCD_HI_BITS 5 65 #define TIM2_PCD_HI_SHIFT 27 66 67 #define CNTL_LCDEN (1 << 0) 68 #define CNTL_LCDBPP1 (0 << 1) 69 #define CNTL_LCDBPP2 (1 << 1) 70 #define CNTL_LCDBPP4 (2 << 1) 71 #define CNTL_LCDBPP8 (3 << 1) 72 #define CNTL_LCDBPP16 (4 << 1) 73 #define CNTL_LCDBPP16_565 (6 << 1) 74 #define CNTL_LCDBPP16_444 (7 << 1) 75 #define CNTL_LCDBPP24 (5 << 1) 76 #define CNTL_LCDBW (1 << 4) 77 #define CNTL_LCDTFT (1 << 5) 78 #define CNTL_LCDMONO8 (1 << 6) 79 #define CNTL_LCDDUAL (1 << 7) 80 #define CNTL_BGR (1 << 8) 81 #define CNTL_BEBO (1 << 9) 82 #define CNTL_BEPO (1 << 10) 83 #define CNTL_LCDPWR (1 << 11) 84 #define CNTL_LCDVCOMP(x) ((x) << 12) 85 #define CNTL_LDMAFIFOTIME (1 << 15) 86 #define CNTL_WATERMARK (1 << 16) 87 88 /* ST Microelectronics variant bits */ 89 #define CNTL_ST_1XBPP_444 0x0 90 #define CNTL_ST_1XBPP_5551 (1 << 17) 91 #define CNTL_ST_1XBPP_565 (1 << 18) 92 #define CNTL_ST_CDWID_12 0x0 93 #define CNTL_ST_CDWID_16 (1 << 19) 94 #define CNTL_ST_CDWID_18 (1 << 20) 95 #define CNTL_ST_CDWID_24 ((1 << 19) | (1 << 20)) 96 #define CNTL_ST_CEAEN (1 << 21) 97 #define CNTL_ST_LCDBPP24_PACKED (6 << 1) 98 99 #define CLCD_IRQ_NEXTBASE_UPDATE BIT(2) 100 101 struct drm_minor; 102 103 /** 104 * struct pl111_variant_data - encodes IP differences 105 * @name: the name of this variant 106 * @is_pl110: this is the early PL110 variant 107 * @is_lcdc: this is the ST Microelectronics Nomadik LCDC variant 108 * @external_bgr: this is the Versatile Pl110 variant with external 109 * BGR/RGB routing 110 * @broken_clockdivider: the clock divider is broken and we need to 111 * use the supplied clock directly 112 * @broken_vblank: the vblank IRQ is broken on this variant 113 * @st_bitmux_control: this variant is using the ST Micro bitmux 114 * extensions to the control register 115 * @formats: array of supported pixel formats on this variant 116 * @nformats: the length of the array of supported pixel formats 117 * @fb_depth: desired depth per pixel on the default framebuffer 118 */ 119 struct pl111_variant_data { 120 const char *name; 121 bool is_pl110; 122 bool is_lcdc; 123 bool external_bgr; 124 bool broken_clockdivider; 125 bool broken_vblank; 126 bool st_bitmux_control; 127 const u32 *formats; 128 unsigned int nformats; 129 unsigned int fb_depth; 130 }; 131 132 struct pl111_drm_dev_private { 133 struct drm_device *drm; 134 135 struct drm_connector *connector; 136 struct drm_panel *panel; 137 struct drm_bridge *bridge; 138 struct drm_simple_display_pipe pipe; 139 140 void *regs; 141 u32 memory_bw; 142 u32 ienb; 143 u32 ctrl; 144 /* The pixel clock (a reference to our clock divider off of CLCDCLK). */ 145 struct clk *clk; 146 /* pl111's internal clock divider. */ 147 struct clk_hw clk_div; 148 /* Lock to sync access to CLCD_TIM2 between the common clock 149 * subsystem and pl111_display_enable(). 150 */ 151 spinlock_t tim2_lock; 152 const struct pl111_variant_data *variant; 153 void (*variant_display_enable) (struct drm_device *drm, u32 format); 154 void (*variant_display_disable) (struct drm_device *drm); 155 bool use_device_memory; 156 }; 157 158 int pl111_display_init(struct drm_device *dev); 159 irqreturn_t pl111_irq(int irq, void *data); 160 void pl111_debugfs_init(struct drm_minor *minor); 161 162 #endif /* _PL111_DRM_H_ */ 163
