1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
3 /* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */
4 /* Copyright 2019 Collabora ltd. */
5 #include <linux/bitfield.h>
6 #include <linux/bitmap.h>
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 
15 #include "panfrost_device.h"
16 #include "panfrost_features.h"
17 #include "panfrost_issues.h"
18 #include "panfrost_gpu.h"
19 #include "panfrost_perfcnt.h"
20 #include "panfrost_regs.h"
21 
panfrost_gpu_irq_handler(int irq,void * data)22 static irqreturn_t panfrost_gpu_irq_handler(int irq, void *data)
23 {
24 	struct panfrost_device *pfdev = data;
25 	u32 state = gpu_read(pfdev, GPU_INT_STAT);
26 	u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS);
27 
28 	if (!state)
29 		return IRQ_NONE;
30 
31 	if (state & GPU_IRQ_MASK_ERROR) {
32 		u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32;
33 		address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO);
34 
35 		dev_warn(pfdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx\n",
36 			 fault_status, panfrost_exception_name(fault_status & 0xFF),
37 			 address);
38 
39 		if (state & GPU_IRQ_MULTIPLE_FAULT)
40 			dev_warn(pfdev->dev, "There were multiple GPU faults - some have not been reported\n");
41 
42 		gpu_write(pfdev, GPU_INT_MASK, 0);
43 	}
44 
45 	if (state & GPU_IRQ_PERFCNT_SAMPLE_COMPLETED)
46 		panfrost_perfcnt_sample_done(pfdev);
47 
48 	if (state & GPU_IRQ_CLEAN_CACHES_COMPLETED)
49 		panfrost_perfcnt_clean_cache_done(pfdev);
50 
51 	gpu_write(pfdev, GPU_INT_CLEAR, state);
52 
53 	return IRQ_HANDLED;
54 }
55 
panfrost_gpu_soft_reset(struct panfrost_device * pfdev)56 int panfrost_gpu_soft_reset(struct panfrost_device *pfdev)
57 {
58 	int ret;
59 	u32 val;
60 
61 	gpu_write(pfdev, GPU_INT_MASK, 0);
62 	gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED);
63 	gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET);
64 
65 	ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT,
66 		val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000);
67 
68 	if (ret) {
69 		dev_err(pfdev->dev, "gpu soft reset timed out\n");
70 		return ret;
71 	}
72 
73 	gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL);
74 	gpu_write(pfdev, GPU_INT_MASK, GPU_IRQ_MASK_ALL);
75 
76 	return 0;
77 }
78 
panfrost_gpu_amlogic_quirk(struct panfrost_device * pfdev)79 void panfrost_gpu_amlogic_quirk(struct panfrost_device *pfdev)
80 {
81 	/*
82 	 * The Amlogic integrated Mali-T820, Mali-G31 & Mali-G52 needs
83 	 * these undocumented bits in GPU_PWR_OVERRIDE1 to be set in order
84 	 * to operate correctly.
85 	 */
86 	gpu_write(pfdev, GPU_PWR_KEY, GPU_PWR_KEY_UNLOCK);
87 	gpu_write(pfdev, GPU_PWR_OVERRIDE1, 0xfff | (0x20 << 16));
88 }
89 
panfrost_gpu_init_quirks(struct panfrost_device * pfdev)90 static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev)
91 {
92 	u32 quirks = 0;
93 
94 	if (panfrost_has_hw_issue(pfdev, HW_ISSUE_8443) ||
95 	    panfrost_has_hw_issue(pfdev, HW_ISSUE_11035))
96 		quirks |= SC_LS_PAUSEBUFFER_DISABLE;
97 
98 	if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10327))
99 		quirks |= SC_SDC_DISABLE_OQ_DISCARD;
100 
101 	if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10797))
102 		quirks |= SC_ENABLE_TEXGRD_FLAGS;
103 
104 	if (!panfrost_has_hw_issue(pfdev, GPUCORE_1619)) {
105 		if (panfrost_model_cmp(pfdev, 0x750) < 0) /* T60x, T62x, T72x */
106 			quirks |= SC_LS_ATTR_CHECK_DISABLE;
107 		else if (panfrost_model_cmp(pfdev, 0x880) <= 0) /* T76x, T8xx */
108 			quirks |= SC_LS_ALLOW_ATTR_TYPES;
109 	}
110 
111 	if (panfrost_has_hw_issue(pfdev, HW_ISSUE_TTRX_2968_TTRX_3162))
112 		quirks |= SC_VAR_ALGORITHM;
113 
114 	if (panfrost_has_hw_feature(pfdev, HW_FEATURE_TLS_HASHING))
115 		quirks |= SC_TLS_HASH_ENABLE;
116 
117 	if (quirks)
118 		gpu_write(pfdev, GPU_SHADER_CONFIG, quirks);
119 
120 
121 	quirks = gpu_read(pfdev, GPU_TILER_CONFIG);
122 
123 	/* Set tiler clock gate override if required */
124 	if (panfrost_has_hw_issue(pfdev, HW_ISSUE_T76X_3953))
125 		quirks |= TC_CLOCK_GATE_OVERRIDE;
126 
127 	gpu_write(pfdev, GPU_TILER_CONFIG, quirks);
128 
129 
130 	quirks = 0;
131 	if ((panfrost_model_eq(pfdev, 0x860) || panfrost_model_eq(pfdev, 0x880)) &&
132 	    pfdev->features.revision >= 0x2000)
133 		quirks |= JM_MAX_JOB_THROTTLE_LIMIT << JM_JOB_THROTTLE_LIMIT_SHIFT;
134 	else if (panfrost_model_eq(pfdev, 0x6000) &&
135 		 pfdev->features.coherency_features == COHERENCY_ACE)
136 		quirks |= (COHERENCY_ACE_LITE | COHERENCY_ACE) <<
137 			   JM_FORCE_COHERENCY_FEATURES_SHIFT;
138 
139 	if (panfrost_has_hw_feature(pfdev, HW_FEATURE_IDVS_GROUP_SIZE))
140 		quirks |= JM_DEFAULT_IDVS_GROUP_SIZE << JM_IDVS_GROUP_SIZE_SHIFT;
141 
142 	if (quirks)
143 		gpu_write(pfdev, GPU_JM_CONFIG, quirks);
144 
145 	/* Here goes platform specific quirks */
146 	if (pfdev->comp->vendor_quirk)
147 		pfdev->comp->vendor_quirk(pfdev);
148 }
149 
150 #define MAX_HW_REVS 6
151 
152 struct panfrost_model {
153 	const char *name;
154 	u32 id;
155 	u32 id_mask;
156 	u64 features;
157 	u64 issues;
158 	struct {
159 		u32 revision;
160 		u64 issues;
161 	} revs[MAX_HW_REVS];
162 };
163 
164 #define GPU_MODEL(_name, _id, ...) \
165 {\
166 	.name = __stringify(_name),				\
167 	.id = _id,						\
168 	.features = hw_features_##_name,			\
169 	.issues = hw_issues_##_name,				\
170 	.revs = { __VA_ARGS__ },				\
171 }
172 
173 #define GPU_REV_EXT(name, _rev, _p, _s, stat) \
174 {\
175 	.revision = (_rev) << 12 | (_p) << 4 | (_s),		\
176 	.issues = hw_issues_##name##_r##_rev##p##_p##stat,	\
177 }
178 #define GPU_REV(name, r, p) GPU_REV_EXT(name, r, p, 0, )
179 
180 static const struct panfrost_model gpu_models[] = {
181 	/* T60x has an oddball version */
182 	GPU_MODEL(t600, 0x600,
183 		GPU_REV_EXT(t600, 0, 0, 1, _15dev0)),
184 	GPU_MODEL(t620, 0x620,
185 		GPU_REV(t620, 0, 1), GPU_REV(t620, 1, 0)),
186 	GPU_MODEL(t720, 0x720),
187 	GPU_MODEL(t760, 0x750,
188 		GPU_REV(t760, 0, 0), GPU_REV(t760, 0, 1),
189 		GPU_REV_EXT(t760, 0, 1, 0, _50rel0),
190 		GPU_REV(t760, 0, 2), GPU_REV(t760, 0, 3)),
191 	GPU_MODEL(t820, 0x820),
192 	GPU_MODEL(t830, 0x830),
193 	GPU_MODEL(t860, 0x860),
194 	GPU_MODEL(t880, 0x880),
195 
196 	GPU_MODEL(g71, 0x6000,
197 		GPU_REV_EXT(g71, 0, 0, 1, _05dev0)),
198 	GPU_MODEL(g72, 0x6001),
199 	GPU_MODEL(g51, 0x7000),
200 	GPU_MODEL(g76, 0x7001),
201 	GPU_MODEL(g52, 0x7002),
202 	GPU_MODEL(g31, 0x7003,
203 		GPU_REV(g31, 1, 0)),
204 
205 	GPU_MODEL(g57, 0x9001,
206 		GPU_REV(g57, 0, 0)),
207 
208 	/* MediaTek MT8192 has a Mali-G57 with a different GPU ID from the
209 	 * standard. Arm's driver does not appear to handle this model.
210 	 * ChromeOS has a hack downstream for it. Treat it as equivalent to
211 	 * standard Mali-G57 for now.
212 	 */
213 	GPU_MODEL(g57, 0x9003,
214 		GPU_REV(g57, 0, 0)),
215 };
216 
panfrost_gpu_init_features(struct panfrost_device * pfdev)217 static void panfrost_gpu_init_features(struct panfrost_device *pfdev)
218 {
219 	u32 gpu_id, num_js, major, minor, status, rev;
220 	const char *name = "unknown";
221 	u64 hw_feat = 0;
222 	u64 hw_issues = hw_issues_all;
223 	const struct panfrost_model *model;
224 	int i;
225 
226 	pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES);
227 	pfdev->features.core_features = gpu_read(pfdev, GPU_CORE_FEATURES);
228 	pfdev->features.tiler_features = gpu_read(pfdev, GPU_TILER_FEATURES);
229 	pfdev->features.mem_features = gpu_read(pfdev, GPU_MEM_FEATURES);
230 	pfdev->features.mmu_features = gpu_read(pfdev, GPU_MMU_FEATURES);
231 	pfdev->features.thread_features = gpu_read(pfdev, GPU_THREAD_FEATURES);
232 	pfdev->features.max_threads = gpu_read(pfdev, GPU_THREAD_MAX_THREADS);
233 	pfdev->features.thread_max_workgroup_sz = gpu_read(pfdev, GPU_THREAD_MAX_WORKGROUP_SIZE);
234 	pfdev->features.thread_max_barrier_sz = gpu_read(pfdev, GPU_THREAD_MAX_BARRIER_SIZE);
235 	pfdev->features.coherency_features = gpu_read(pfdev, GPU_COHERENCY_FEATURES);
236 	pfdev->features.afbc_features = gpu_read(pfdev, GPU_AFBC_FEATURES);
237 	for (i = 0; i < 4; i++)
238 		pfdev->features.texture_features[i] = gpu_read(pfdev, GPU_TEXTURE_FEATURES(i));
239 
240 	pfdev->features.as_present = gpu_read(pfdev, GPU_AS_PRESENT);
241 
242 	pfdev->features.js_present = gpu_read(pfdev, GPU_JS_PRESENT);
243 	num_js = hweight32(pfdev->features.js_present);
244 	for (i = 0; i < num_js; i++)
245 		pfdev->features.js_features[i] = gpu_read(pfdev, GPU_JS_FEATURES(i));
246 
247 	pfdev->features.shader_present = gpu_read(pfdev, GPU_SHADER_PRESENT_LO);
248 	pfdev->features.shader_present |= (u64)gpu_read(pfdev, GPU_SHADER_PRESENT_HI) << 32;
249 
250 	pfdev->features.tiler_present = gpu_read(pfdev, GPU_TILER_PRESENT_LO);
251 	pfdev->features.tiler_present |= (u64)gpu_read(pfdev, GPU_TILER_PRESENT_HI) << 32;
252 
253 	pfdev->features.l2_present = gpu_read(pfdev, GPU_L2_PRESENT_LO);
254 	pfdev->features.l2_present |= (u64)gpu_read(pfdev, GPU_L2_PRESENT_HI) << 32;
255 	pfdev->features.nr_core_groups = hweight64(pfdev->features.l2_present);
256 
257 	pfdev->features.stack_present = gpu_read(pfdev, GPU_STACK_PRESENT_LO);
258 	pfdev->features.stack_present |= (u64)gpu_read(pfdev, GPU_STACK_PRESENT_HI) << 32;
259 
260 	pfdev->features.thread_tls_alloc = gpu_read(pfdev, GPU_THREAD_TLS_ALLOC);
261 
262 	gpu_id = gpu_read(pfdev, GPU_ID);
263 	pfdev->features.revision = gpu_id & 0xffff;
264 	pfdev->features.id = gpu_id >> 16;
265 
266 	/* The T60x has an oddball ID value. Fix it up to the standard Midgard
267 	 * format so we (and userspace) don't have to special case it.
268 	 */
269 	if (pfdev->features.id == 0x6956)
270 		pfdev->features.id = 0x0600;
271 
272 	major = (pfdev->features.revision >> 12) & 0xf;
273 	minor = (pfdev->features.revision >> 4) & 0xff;
274 	status = pfdev->features.revision & 0xf;
275 	rev = pfdev->features.revision;
276 
277 	gpu_id = pfdev->features.id;
278 
279 	for (model = gpu_models; model->name; model++) {
280 		int best = -1;
281 
282 		if (!panfrost_model_eq(pfdev, model->id))
283 			continue;
284 
285 		name = model->name;
286 		hw_feat = model->features;
287 		hw_issues |= model->issues;
288 		for (i = 0; i < MAX_HW_REVS; i++) {
289 			if (model->revs[i].revision == rev) {
290 				best = i;
291 				break;
292 			} else if (model->revs[i].revision == (rev & ~0xf))
293 				best = i;
294 		}
295 
296 		if (best >= 0)
297 			hw_issues |= model->revs[best].issues;
298 
299 		break;
300 	}
301 
302 	bitmap_from_u64(pfdev->features.hw_features, hw_feat);
303 	bitmap_from_u64(pfdev->features.hw_issues, hw_issues);
304 
305 	dev_info(pfdev->dev, "mali-%s id 0x%x major 0x%x minor 0x%x status 0x%x",
306 		 name, gpu_id, major, minor, status);
307 	dev_info(pfdev->dev, "features: %64pb, issues: %64pb",
308 		 pfdev->features.hw_features,
309 		 pfdev->features.hw_issues);
310 
311 	dev_info(pfdev->dev, "Features: L2:0x%08x Shader:0x%08x Tiler:0x%08x Mem:0x%0x MMU:0x%08x AS:0x%x JS:0x%x",
312 		 pfdev->features.l2_features,
313 		 pfdev->features.core_features,
314 		 pfdev->features.tiler_features,
315 		 pfdev->features.mem_features,
316 		 pfdev->features.mmu_features,
317 		 pfdev->features.as_present,
318 		 pfdev->features.js_present);
319 
320 	dev_info(pfdev->dev, "shader_present=0x%0llx l2_present=0x%0llx",
321 		 pfdev->features.shader_present, pfdev->features.l2_present);
322 }
323 
panfrost_gpu_power_on(struct panfrost_device * pfdev)324 void panfrost_gpu_power_on(struct panfrost_device *pfdev)
325 {
326 	int ret;
327 	u32 val;
328 	u64 core_mask = U64_MAX;
329 
330 	panfrost_gpu_init_quirks(pfdev);
331 
332 	if (pfdev->features.l2_present != 1) {
333 		/*
334 		 * Only support one core group now.
335 		 * ~(l2_present - 1) unsets all bits in l2_present except
336 		 * the bottom bit. (l2_present - 2) has all the bits in
337 		 * the first core group set. AND them together to generate
338 		 * a mask of cores in the first core group.
339 		 */
340 		core_mask = ~(pfdev->features.l2_present - 1) &
341 			     (pfdev->features.l2_present - 2);
342 		dev_info_once(pfdev->dev, "using only 1st core group (%lu cores from %lu)\n",
343 			      hweight64(core_mask),
344 			      hweight64(pfdev->features.shader_present));
345 	}
346 	gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present & core_mask);
347 	ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO,
348 		val, val == (pfdev->features.l2_present & core_mask),
349 		100, 20000);
350 	if (ret)
351 		dev_err(pfdev->dev, "error powering up gpu L2");
352 
353 	gpu_write(pfdev, SHADER_PWRON_LO,
354 		  pfdev->features.shader_present & core_mask);
355 	ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO,
356 		val, val == (pfdev->features.shader_present & core_mask),
357 		100, 20000);
358 	if (ret)
359 		dev_err(pfdev->dev, "error powering up gpu shader");
360 
361 	gpu_write(pfdev, TILER_PWRON_LO, pfdev->features.tiler_present);
362 	ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO,
363 		val, val == pfdev->features.tiler_present, 100, 1000);
364 	if (ret)
365 		dev_err(pfdev->dev, "error powering up gpu tiler");
366 }
367 
panfrost_gpu_power_off(struct panfrost_device * pfdev)368 void panfrost_gpu_power_off(struct panfrost_device *pfdev)
369 {
370 	gpu_write(pfdev, TILER_PWROFF_LO, 0);
371 	gpu_write(pfdev, SHADER_PWROFF_LO, 0);
372 	gpu_write(pfdev, L2_PWROFF_LO, 0);
373 }
374 
panfrost_gpu_init(struct panfrost_device * pfdev)375 int panfrost_gpu_init(struct panfrost_device *pfdev)
376 {
377 	int err, irq;
378 
379 	err = panfrost_gpu_soft_reset(pfdev);
380 	if (err)
381 		return err;
382 
383 	panfrost_gpu_init_features(pfdev);
384 
385 	err = dma_set_mask_and_coherent(pfdev->dev,
386 		DMA_BIT_MASK(FIELD_GET(0xff00, pfdev->features.mmu_features)));
387 	if (err)
388 		return err;
389 
390 	dma_set_max_seg_size(pfdev->dev, UINT_MAX);
391 
392 	irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "gpu");
393 	if (irq <= 0)
394 		return -ENODEV;
395 
396 	err = devm_request_irq(pfdev->dev, irq, panfrost_gpu_irq_handler,
397 			       IRQF_SHARED, KBUILD_MODNAME "-gpu", pfdev);
398 	if (err) {
399 		dev_err(pfdev->dev, "failed to request gpu irq");
400 		return err;
401 	}
402 
403 	panfrost_gpu_power_on(pfdev);
404 
405 	return 0;
406 }
407 
panfrost_gpu_fini(struct panfrost_device * pfdev)408 void panfrost_gpu_fini(struct panfrost_device *pfdev)
409 {
410 	panfrost_gpu_power_off(pfdev);
411 }
412 
panfrost_gpu_get_latest_flush_id(struct panfrost_device * pfdev)413 u32 panfrost_gpu_get_latest_flush_id(struct panfrost_device *pfdev)
414 {
415 	u32 flush_id;
416 
417 	if (panfrost_has_hw_feature(pfdev, HW_FEATURE_FLUSH_REDUCTION)) {
418 		/* Flush reduction only makes sense when the GPU is kept powered on between jobs */
419 		if (pm_runtime_get_if_in_use(pfdev->dev)) {
420 			flush_id = gpu_read(pfdev, GPU_LATEST_FLUSH_ID);
421 			pm_runtime_put(pfdev->dev);
422 			return flush_id;
423 		}
424 	}
425 
426 	return 0;
427 }
428