1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/string_helpers.h>
29
30 #include <drm/display/drm_scdc_helper.h>
31 #include <drm/drm_privacy_screen_consumer.h>
32
33 #include "i915_drv.h"
34 #include "i915_reg.h"
35 #include "icl_dsi.h"
36 #include "intel_audio.h"
37 #include "intel_audio_regs.h"
38 #include "intel_backlight.h"
39 #include "intel_combo_phy.h"
40 #include "intel_combo_phy_regs.h"
41 #include "intel_connector.h"
42 #include "intel_crtc.h"
43 #include "intel_cx0_phy.h"
44 #include "intel_cx0_phy_regs.h"
45 #include "intel_ddi.h"
46 #include "intel_ddi_buf_trans.h"
47 #include "intel_de.h"
48 #include "intel_display_power.h"
49 #include "intel_display_types.h"
50 #include "intel_dkl_phy.h"
51 #include "intel_dkl_phy_regs.h"
52 #include "intel_dp.h"
53 #include "intel_dp_aux.h"
54 #include "intel_dp_link_training.h"
55 #include "intel_dp_mst.h"
56 #include "intel_dpio_phy.h"
57 #include "intel_dsi.h"
58 #include "intel_fdi.h"
59 #include "intel_fifo_underrun.h"
60 #include "intel_gmbus.h"
61 #include "intel_hdcp.h"
62 #include "intel_hdmi.h"
63 #include "intel_hotplug.h"
64 #include "intel_hti.h"
65 #include "intel_lspcon.h"
66 #include "intel_mg_phy_regs.h"
67 #include "intel_modeset_lock.h"
68 #include "intel_pps.h"
69 #include "intel_psr.h"
70 #include "intel_quirks.h"
71 #include "intel_snps_phy.h"
72 #include "intel_tc.h"
73 #include "intel_vdsc.h"
74 #include "intel_vdsc_regs.h"
75 #include "skl_scaler.h"
76 #include "skl_universal_plane.h"
77
78 static const u8 index_to_dp_signal_levels[] = {
79 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
80 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
81 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
82 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
83 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
84 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
85 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
86 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
87 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
88 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
89 };
90
intel_ddi_hdmi_level(struct intel_encoder * encoder,const struct intel_ddi_buf_trans * trans)91 static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
92 const struct intel_ddi_buf_trans *trans)
93 {
94 int level;
95
96 level = intel_bios_hdmi_level_shift(encoder->devdata);
97 if (level < 0)
98 level = trans->hdmi_default_entry;
99
100 return level;
101 }
102
has_buf_trans_select(struct drm_i915_private * i915)103 static bool has_buf_trans_select(struct drm_i915_private *i915)
104 {
105 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915);
106 }
107
has_iboost(struct drm_i915_private * i915)108 static bool has_iboost(struct drm_i915_private *i915)
109 {
110 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915);
111 }
112
113 /*
114 * Starting with Haswell, DDI port buffers must be programmed with correct
115 * values in advance. This function programs the correct values for
116 * DP/eDP/FDI use cases.
117 */
hsw_prepare_dp_ddi_buffers(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)118 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
119 const struct intel_crtc_state *crtc_state)
120 {
121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
122 u32 iboost_bit = 0;
123 int i, n_entries;
124 enum port port = encoder->port;
125 const struct intel_ddi_buf_trans *trans;
126
127 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
128 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
129 return;
130
131 /* If we're boosting the current, set bit 31 of trans1 */
132 if (has_iboost(dev_priv) &&
133 intel_bios_dp_boost_level(encoder->devdata))
134 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
135
136 for (i = 0; i < n_entries; i++) {
137 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
138 trans->entries[i].hsw.trans1 | iboost_bit);
139 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
140 trans->entries[i].hsw.trans2);
141 }
142 }
143
144 /*
145 * Starting with Haswell, DDI port buffers must be programmed with correct
146 * values in advance. This function programs the correct values for
147 * HDMI/DVI use cases.
148 */
hsw_prepare_hdmi_ddi_buffers(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)149 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
150 const struct intel_crtc_state *crtc_state)
151 {
152 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
153 int level = intel_ddi_level(encoder, crtc_state, 0);
154 u32 iboost_bit = 0;
155 int n_entries;
156 enum port port = encoder->port;
157 const struct intel_ddi_buf_trans *trans;
158
159 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
160 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
161 return;
162
163 /* If we're boosting the current, set bit 31 of trans1 */
164 if (has_iboost(dev_priv) &&
165 intel_bios_hdmi_boost_level(encoder->devdata))
166 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
167
168 /* Entry 9 is for HDMI: */
169 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
170 trans->entries[level].hsw.trans1 | iboost_bit);
171 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
172 trans->entries[level].hsw.trans2);
173 }
174
mtl_wait_ddi_buf_idle(struct drm_i915_private * i915,enum port port)175 static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
176 {
177 int ret;
178
179 /* FIXME: find out why Bspec's 100us timeout is too short */
180 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
181 XELPDP_PORT_BUF_PHY_IDLE), 10000);
182 if (ret)
183 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",
184 port_name(port));
185 }
186
intel_wait_ddi_buf_idle(struct drm_i915_private * dev_priv,enum port port)187 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
188 enum port port)
189 {
190 if (IS_BROXTON(dev_priv)) {
191 udelay(16);
192 return;
193 }
194
195 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
196 DDI_BUF_IS_IDLE), 8))
197 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
198 port_name(port));
199 }
200
intel_wait_ddi_buf_active(struct drm_i915_private * dev_priv,enum port port)201 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
202 enum port port)
203 {
204 enum phy phy = intel_port_to_phy(dev_priv, port);
205 int timeout_us;
206 int ret;
207
208 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
209 if (DISPLAY_VER(dev_priv) < 10) {
210 usleep_range(518, 1000);
211 return;
212 }
213
214 if (DISPLAY_VER(dev_priv) >= 14) {
215 timeout_us = 10000;
216 } else if (IS_DG2(dev_priv)) {
217 timeout_us = 1200;
218 } else if (DISPLAY_VER(dev_priv) >= 12) {
219 if (intel_phy_is_tc(dev_priv, phy))
220 timeout_us = 3000;
221 else
222 timeout_us = 1000;
223 } else {
224 timeout_us = 500;
225 }
226
227 if (DISPLAY_VER(dev_priv) >= 14)
228 ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE),
229 timeout_us, 10, 10);
230 else
231 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE),
232 timeout_us, 10, 10);
233
234 if (ret)
235 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
236 port_name(port));
237 }
238
hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll * pll)239 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
240 {
241 switch (pll->info->id) {
242 case DPLL_ID_WRPLL1:
243 return PORT_CLK_SEL_WRPLL1;
244 case DPLL_ID_WRPLL2:
245 return PORT_CLK_SEL_WRPLL2;
246 case DPLL_ID_SPLL:
247 return PORT_CLK_SEL_SPLL;
248 case DPLL_ID_LCPLL_810:
249 return PORT_CLK_SEL_LCPLL_810;
250 case DPLL_ID_LCPLL_1350:
251 return PORT_CLK_SEL_LCPLL_1350;
252 case DPLL_ID_LCPLL_2700:
253 return PORT_CLK_SEL_LCPLL_2700;
254 default:
255 MISSING_CASE(pll->info->id);
256 return PORT_CLK_SEL_NONE;
257 }
258 }
259
icl_pll_to_ddi_clk_sel(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)260 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
261 const struct intel_crtc_state *crtc_state)
262 {
263 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
264 int clock = crtc_state->port_clock;
265 const enum intel_dpll_id id = pll->info->id;
266
267 switch (id) {
268 default:
269 /*
270 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
271 * here, so do warn if this get passed in
272 */
273 MISSING_CASE(id);
274 return DDI_CLK_SEL_NONE;
275 case DPLL_ID_ICL_TBTPLL:
276 switch (clock) {
277 case 162000:
278 return DDI_CLK_SEL_TBT_162;
279 case 270000:
280 return DDI_CLK_SEL_TBT_270;
281 case 540000:
282 return DDI_CLK_SEL_TBT_540;
283 case 810000:
284 return DDI_CLK_SEL_TBT_810;
285 default:
286 MISSING_CASE(clock);
287 return DDI_CLK_SEL_NONE;
288 }
289 case DPLL_ID_ICL_MGPLL1:
290 case DPLL_ID_ICL_MGPLL2:
291 case DPLL_ID_ICL_MGPLL3:
292 case DPLL_ID_ICL_MGPLL4:
293 case DPLL_ID_TGL_MGPLL5:
294 case DPLL_ID_TGL_MGPLL6:
295 return DDI_CLK_SEL_MG;
296 }
297 }
298
ddi_buf_phy_link_rate(int port_clock)299 static u32 ddi_buf_phy_link_rate(int port_clock)
300 {
301 switch (port_clock) {
302 case 162000:
303 return DDI_BUF_PHY_LINK_RATE(0);
304 case 216000:
305 return DDI_BUF_PHY_LINK_RATE(4);
306 case 243000:
307 return DDI_BUF_PHY_LINK_RATE(5);
308 case 270000:
309 return DDI_BUF_PHY_LINK_RATE(1);
310 case 324000:
311 return DDI_BUF_PHY_LINK_RATE(6);
312 case 432000:
313 return DDI_BUF_PHY_LINK_RATE(7);
314 case 540000:
315 return DDI_BUF_PHY_LINK_RATE(2);
316 case 810000:
317 return DDI_BUF_PHY_LINK_RATE(3);
318 default:
319 MISSING_CASE(port_clock);
320 return DDI_BUF_PHY_LINK_RATE(0);
321 }
322 }
323
intel_ddi_init_dp_buf_reg(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)324 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
325 const struct intel_crtc_state *crtc_state)
326 {
327 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
328 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
329 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
330 enum phy phy = intel_port_to_phy(i915, encoder->port);
331
332 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
333 intel_dp->DP = dig_port->saved_port_bits |
334 DDI_PORT_WIDTH(crtc_state->lane_count) |
335 DDI_BUF_TRANS_SELECT(0);
336
337 if (DISPLAY_VER(i915) >= 14) {
338 if (intel_dp_is_uhbr(crtc_state))
339 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
340 else
341 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
342 }
343
344 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
345 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
346 if (!intel_tc_port_in_tbt_alt_mode(dig_port))
347 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
348 }
349 }
350
icl_calc_tbt_pll_link(struct drm_i915_private * dev_priv,enum port port)351 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
352 enum port port)
353 {
354 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
355
356 switch (val) {
357 case DDI_CLK_SEL_NONE:
358 return 0;
359 case DDI_CLK_SEL_TBT_162:
360 return 162000;
361 case DDI_CLK_SEL_TBT_270:
362 return 270000;
363 case DDI_CLK_SEL_TBT_540:
364 return 540000;
365 case DDI_CLK_SEL_TBT_810:
366 return 810000;
367 default:
368 MISSING_CASE(val);
369 return 0;
370 }
371 }
372
ddi_dotclock_get(struct intel_crtc_state * pipe_config)373 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
374 {
375 /* CRT dotclock is determined via other means */
376 if (pipe_config->has_pch_encoder)
377 return;
378
379 pipe_config->hw.adjusted_mode.crtc_clock =
380 intel_crtc_dotclock(pipe_config);
381 }
382
intel_ddi_set_dp_msa(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)383 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
384 const struct drm_connector_state *conn_state)
385 {
386 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
387 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
388 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
389 u32 temp;
390
391 if (!intel_crtc_has_dp_encoder(crtc_state))
392 return;
393
394 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
395
396 temp = DP_MSA_MISC_SYNC_CLOCK;
397
398 switch (crtc_state->pipe_bpp) {
399 case 18:
400 temp |= DP_MSA_MISC_6_BPC;
401 break;
402 case 24:
403 temp |= DP_MSA_MISC_8_BPC;
404 break;
405 case 30:
406 temp |= DP_MSA_MISC_10_BPC;
407 break;
408 case 36:
409 temp |= DP_MSA_MISC_12_BPC;
410 break;
411 default:
412 MISSING_CASE(crtc_state->pipe_bpp);
413 break;
414 }
415
416 /* nonsense combination */
417 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
418 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
419
420 if (crtc_state->limited_color_range)
421 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
422
423 /*
424 * As per DP 1.2 spec section 2.3.4.3 while sending
425 * YCBCR 444 signals we should program MSA MISC1/0 fields with
426 * colorspace information.
427 */
428 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
429 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
430
431 /*
432 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
433 * of Color Encoding Format and Content Color Gamut] while sending
434 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
435 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
436 */
437 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
438 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
439
440 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
441 }
442
bdw_trans_port_sync_master_select(enum transcoder master_transcoder)443 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
444 {
445 if (master_transcoder == TRANSCODER_EDP)
446 return 0;
447 else
448 return master_transcoder + 1;
449 }
450
451 static void
intel_ddi_config_transcoder_dp2(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)452 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder,
453 const struct intel_crtc_state *crtc_state)
454 {
455 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
456 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
457 u32 val = 0;
458
459 if (intel_dp_is_uhbr(crtc_state))
460 val = TRANS_DP2_128B132B_CHANNEL_CODING;
461
462 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val);
463 }
464
465 /*
466 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
467 *
468 * Only intended to be used by intel_ddi_enable_transcoder_func() and
469 * intel_ddi_config_transcoder_func().
470 */
471 static u32
intel_ddi_transcoder_func_reg_val_get(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)472 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
473 const struct intel_crtc_state *crtc_state)
474 {
475 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
476 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
477 enum pipe pipe = crtc->pipe;
478 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
479 enum port port = encoder->port;
480 u32 temp;
481
482 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
483 temp = TRANS_DDI_FUNC_ENABLE;
484 if (DISPLAY_VER(dev_priv) >= 12)
485 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
486 else
487 temp |= TRANS_DDI_SELECT_PORT(port);
488
489 switch (crtc_state->pipe_bpp) {
490 default:
491 MISSING_CASE(crtc_state->pipe_bpp);
492 fallthrough;
493 case 18:
494 temp |= TRANS_DDI_BPC_6;
495 break;
496 case 24:
497 temp |= TRANS_DDI_BPC_8;
498 break;
499 case 30:
500 temp |= TRANS_DDI_BPC_10;
501 break;
502 case 36:
503 temp |= TRANS_DDI_BPC_12;
504 break;
505 }
506
507 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
508 temp |= TRANS_DDI_PVSYNC;
509 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
510 temp |= TRANS_DDI_PHSYNC;
511
512 if (cpu_transcoder == TRANSCODER_EDP) {
513 switch (pipe) {
514 default:
515 MISSING_CASE(pipe);
516 fallthrough;
517 case PIPE_A:
518 /* On Haswell, can only use the always-on power well for
519 * eDP when not using the panel fitter, and when not
520 * using motion blur mitigation (which we don't
521 * support). */
522 if (crtc_state->pch_pfit.force_thru)
523 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
524 else
525 temp |= TRANS_DDI_EDP_INPUT_A_ON;
526 break;
527 case PIPE_B:
528 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
529 break;
530 case PIPE_C:
531 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
532 break;
533 }
534 }
535
536 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
537 if (crtc_state->has_hdmi_sink)
538 temp |= TRANS_DDI_MODE_SELECT_HDMI;
539 else
540 temp |= TRANS_DDI_MODE_SELECT_DVI;
541
542 if (crtc_state->hdmi_scrambling)
543 temp |= TRANS_DDI_HDMI_SCRAMBLING;
544 if (crtc_state->hdmi_high_tmds_clock_ratio)
545 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
546 if (DISPLAY_VER(dev_priv) >= 14)
547 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count);
548 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
549 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
550 temp |= (crtc_state->fdi_lanes - 1) << 1;
551 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
552 if (intel_dp_is_uhbr(crtc_state))
553 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
554 else
555 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
556 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
557
558 if (DISPLAY_VER(dev_priv) >= 12) {
559 enum transcoder master;
560
561 master = crtc_state->mst_master_transcoder;
562 drm_WARN_ON(&dev_priv->drm,
563 master == INVALID_TRANSCODER);
564 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
565 }
566 } else {
567 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
568 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
569 }
570
571 if (IS_DISPLAY_VER(dev_priv, 8, 10) &&
572 crtc_state->master_transcoder != INVALID_TRANSCODER) {
573 u8 master_select =
574 bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
575
576 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
577 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
578 }
579
580 return temp;
581 }
582
intel_ddi_enable_transcoder_func(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)583 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
584 const struct intel_crtc_state *crtc_state)
585 {
586 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
587 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
588 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
589
590 if (DISPLAY_VER(dev_priv) >= 11) {
591 enum transcoder master_transcoder = crtc_state->master_transcoder;
592 u32 ctl2 = 0;
593
594 if (master_transcoder != INVALID_TRANSCODER) {
595 u8 master_select =
596 bdw_trans_port_sync_master_select(master_transcoder);
597
598 ctl2 |= PORT_SYNC_MODE_ENABLE |
599 PORT_SYNC_MODE_MASTER_SELECT(master_select);
600 }
601
602 intel_de_write(dev_priv,
603 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
604 }
605
606 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
607 intel_ddi_transcoder_func_reg_val_get(encoder,
608 crtc_state));
609 }
610
611 /*
612 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
613 * bit.
614 */
615 static void
intel_ddi_config_transcoder_func(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)616 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
617 const struct intel_crtc_state *crtc_state)
618 {
619 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
620 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
621 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
622 u32 ctl;
623
624 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
625 ctl &= ~TRANS_DDI_FUNC_ENABLE;
626 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
627 }
628
intel_ddi_disable_transcoder_func(const struct intel_crtc_state * crtc_state)629 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
630 {
631 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
632 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
633 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
634 u32 ctl;
635
636 if (DISPLAY_VER(dev_priv) >= 11)
637 intel_de_write(dev_priv,
638 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
639
640 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
641
642 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
643
644 ctl &= ~TRANS_DDI_FUNC_ENABLE;
645
646 if (IS_DISPLAY_VER(dev_priv, 8, 10))
647 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
648 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
649
650 if (DISPLAY_VER(dev_priv) >= 12) {
651 if (!intel_dp_mst_is_master_trans(crtc_state)) {
652 ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
653 TRANS_DDI_MODE_SELECT_MASK);
654 }
655 } else {
656 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
657 }
658
659 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
660
661 if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) &&
662 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
663 drm_dbg_kms(&dev_priv->drm,
664 "Quirk Increase DDI disabled time\n");
665 /* Quirk time at 100ms for reliable operation */
666 msleep(100);
667 }
668 }
669
intel_ddi_toggle_hdcp_bits(struct intel_encoder * intel_encoder,enum transcoder cpu_transcoder,bool enable,u32 hdcp_mask)670 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
671 enum transcoder cpu_transcoder,
672 bool enable, u32 hdcp_mask)
673 {
674 struct drm_device *dev = intel_encoder->base.dev;
675 struct drm_i915_private *dev_priv = to_i915(dev);
676 intel_wakeref_t wakeref;
677 int ret = 0;
678
679 wakeref = intel_display_power_get_if_enabled(dev_priv,
680 intel_encoder->power_domain);
681 if (drm_WARN_ON(dev, !wakeref))
682 return -ENXIO;
683
684 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
685 hdcp_mask, enable ? hdcp_mask : 0);
686 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
687 return ret;
688 }
689
intel_ddi_connector_get_hw_state(struct intel_connector * intel_connector)690 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
691 {
692 struct drm_device *dev = intel_connector->base.dev;
693 struct drm_i915_private *dev_priv = to_i915(dev);
694 struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
695 int type = intel_connector->base.connector_type;
696 enum port port = encoder->port;
697 enum transcoder cpu_transcoder;
698 intel_wakeref_t wakeref;
699 enum pipe pipe = 0;
700 u32 tmp;
701 bool ret;
702
703 wakeref = intel_display_power_get_if_enabled(dev_priv,
704 encoder->power_domain);
705 if (!wakeref)
706 return false;
707
708 if (!encoder->get_hw_state(encoder, &pipe)) {
709 ret = false;
710 goto out;
711 }
712
713 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
714 cpu_transcoder = TRANSCODER_EDP;
715 else
716 cpu_transcoder = (enum transcoder) pipe;
717
718 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
719
720 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
721 case TRANS_DDI_MODE_SELECT_HDMI:
722 case TRANS_DDI_MODE_SELECT_DVI:
723 ret = type == DRM_MODE_CONNECTOR_HDMIA;
724 break;
725
726 case TRANS_DDI_MODE_SELECT_DP_SST:
727 ret = type == DRM_MODE_CONNECTOR_eDP ||
728 type == DRM_MODE_CONNECTOR_DisplayPort;
729 break;
730
731 case TRANS_DDI_MODE_SELECT_DP_MST:
732 /* if the transcoder is in MST state then
733 * connector isn't connected */
734 ret = false;
735 break;
736
737 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
738 if (HAS_DP20(dev_priv))
739 /* 128b/132b */
740 ret = false;
741 else
742 /* FDI */
743 ret = type == DRM_MODE_CONNECTOR_VGA;
744 break;
745
746 default:
747 ret = false;
748 break;
749 }
750
751 out:
752 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
753
754 return ret;
755 }
756
intel_ddi_get_encoder_pipes(struct intel_encoder * encoder,u8 * pipe_mask,bool * is_dp_mst)757 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
758 u8 *pipe_mask, bool *is_dp_mst)
759 {
760 struct drm_device *dev = encoder->base.dev;
761 struct drm_i915_private *dev_priv = to_i915(dev);
762 enum port port = encoder->port;
763 intel_wakeref_t wakeref;
764 enum pipe p;
765 u32 tmp;
766 u8 mst_pipe_mask;
767
768 *pipe_mask = 0;
769 *is_dp_mst = false;
770
771 wakeref = intel_display_power_get_if_enabled(dev_priv,
772 encoder->power_domain);
773 if (!wakeref)
774 return;
775
776 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
777 if (!(tmp & DDI_BUF_CTL_ENABLE))
778 goto out;
779
780 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
781 tmp = intel_de_read(dev_priv,
782 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
783
784 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
785 default:
786 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
787 fallthrough;
788 case TRANS_DDI_EDP_INPUT_A_ON:
789 case TRANS_DDI_EDP_INPUT_A_ONOFF:
790 *pipe_mask = BIT(PIPE_A);
791 break;
792 case TRANS_DDI_EDP_INPUT_B_ONOFF:
793 *pipe_mask = BIT(PIPE_B);
794 break;
795 case TRANS_DDI_EDP_INPUT_C_ONOFF:
796 *pipe_mask = BIT(PIPE_C);
797 break;
798 }
799
800 goto out;
801 }
802
803 mst_pipe_mask = 0;
804 for_each_pipe(dev_priv, p) {
805 enum transcoder cpu_transcoder = (enum transcoder)p;
806 unsigned int port_mask, ddi_select;
807 intel_wakeref_t trans_wakeref;
808
809 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
810 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
811 if (!trans_wakeref)
812 continue;
813
814 if (DISPLAY_VER(dev_priv) >= 12) {
815 port_mask = TGL_TRANS_DDI_PORT_MASK;
816 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
817 } else {
818 port_mask = TRANS_DDI_PORT_MASK;
819 ddi_select = TRANS_DDI_SELECT_PORT(port);
820 }
821
822 tmp = intel_de_read(dev_priv,
823 TRANS_DDI_FUNC_CTL(cpu_transcoder));
824 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
825 trans_wakeref);
826
827 if ((tmp & port_mask) != ddi_select)
828 continue;
829
830 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST ||
831 (HAS_DP20(dev_priv) &&
832 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B))
833 mst_pipe_mask |= BIT(p);
834
835 *pipe_mask |= BIT(p);
836 }
837
838 if (!*pipe_mask)
839 drm_dbg_kms(&dev_priv->drm,
840 "No pipe for [ENCODER:%d:%s] found\n",
841 encoder->base.base.id, encoder->base.name);
842
843 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
844 drm_dbg_kms(&dev_priv->drm,
845 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
846 encoder->base.base.id, encoder->base.name,
847 *pipe_mask);
848 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
849 }
850
851 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
852 drm_dbg_kms(&dev_priv->drm,
853 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
854 encoder->base.base.id, encoder->base.name,
855 *pipe_mask, mst_pipe_mask);
856 else
857 *is_dp_mst = mst_pipe_mask;
858
859 out:
860 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) {
861 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
862 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
863 BXT_PHY_LANE_POWERDOWN_ACK |
864 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
865 drm_err(&dev_priv->drm,
866 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
867 encoder->base.base.id, encoder->base.name, tmp);
868 }
869
870 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
871 }
872
intel_ddi_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)873 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
874 enum pipe *pipe)
875 {
876 u8 pipe_mask;
877 bool is_mst;
878
879 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
880
881 if (is_mst || !pipe_mask)
882 return false;
883
884 *pipe = ffs(pipe_mask) - 1;
885
886 return true;
887 }
888
889 static enum intel_display_power_domain
intel_ddi_main_link_aux_domain(struct intel_digital_port * dig_port,const struct intel_crtc_state * crtc_state)890 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
891 const struct intel_crtc_state *crtc_state)
892 {
893 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
894 enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
895
896 /*
897 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
898 * DC states enabled at the same time, while for driver initiated AUX
899 * transfers we need the same AUX IOs to be powered but with DC states
900 * disabled. Accordingly use the AUX_IO_<port> power domain here which
901 * leaves DC states enabled.
902 *
903 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require
904 * AUX IO to be enabled, but all these require DC_OFF to be enabled as
905 * well, so we can acquire a wider AUX_<port> power domain reference
906 * instead of a specific AUX_IO_<port> reference without powering up any
907 * extra wells.
908 */
909 if (intel_encoder_can_psr(&dig_port->base))
910 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
911 else if (DISPLAY_VER(i915) < 14 &&
912 (intel_crtc_has_dp_encoder(crtc_state) ||
913 intel_phy_is_tc(i915, phy)))
914 return intel_aux_power_domain(dig_port);
915 else
916 return POWER_DOMAIN_INVALID;
917 }
918
919 static void
main_link_aux_power_domain_get(struct intel_digital_port * dig_port,const struct intel_crtc_state * crtc_state)920 main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
921 const struct intel_crtc_state *crtc_state)
922 {
923 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
924 enum intel_display_power_domain domain =
925 intel_ddi_main_link_aux_domain(dig_port, crtc_state);
926
927 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref);
928
929 if (domain == POWER_DOMAIN_INVALID)
930 return;
931
932 dig_port->aux_wakeref = intel_display_power_get(i915, domain);
933 }
934
935 static void
main_link_aux_power_domain_put(struct intel_digital_port * dig_port,const struct intel_crtc_state * crtc_state)936 main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
937 const struct intel_crtc_state *crtc_state)
938 {
939 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
940 enum intel_display_power_domain domain =
941 intel_ddi_main_link_aux_domain(dig_port, crtc_state);
942 intel_wakeref_t wf;
943
944 wf = fetch_and_zero(&dig_port->aux_wakeref);
945 if (!wf)
946 return;
947
948 intel_display_power_put(i915, domain, wf);
949 }
950
intel_ddi_get_power_domains(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)951 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
952 struct intel_crtc_state *crtc_state)
953 {
954 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
955 struct intel_digital_port *dig_port;
956
957 /*
958 * TODO: Add support for MST encoders. Atm, the following should never
959 * happen since fake-MST encoders don't set their get_power_domains()
960 * hook.
961 */
962 if (drm_WARN_ON(&dev_priv->drm,
963 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
964 return;
965
966 dig_port = enc_to_dig_port(encoder);
967
968 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
969 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
970 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
971 dig_port->ddi_io_power_domain);
972 }
973
974 main_link_aux_power_domain_get(dig_port, crtc_state);
975 }
976
intel_ddi_enable_transcoder_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)977 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder,
978 const struct intel_crtc_state *crtc_state)
979 {
980 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
981 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
982 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
983 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
984 u32 val;
985
986 if (cpu_transcoder == TRANSCODER_EDP)
987 return;
988
989 if (DISPLAY_VER(dev_priv) >= 13)
990 val = TGL_TRANS_CLK_SEL_PORT(phy);
991 else if (DISPLAY_VER(dev_priv) >= 12)
992 val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
993 else
994 val = TRANS_CLK_SEL_PORT(encoder->port);
995
996 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
997 }
998
intel_ddi_disable_transcoder_clock(const struct intel_crtc_state * crtc_state)999 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state)
1000 {
1001 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1002 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1003 u32 val;
1004
1005 if (cpu_transcoder == TRANSCODER_EDP)
1006 return;
1007
1008 if (DISPLAY_VER(dev_priv) >= 12)
1009 val = TGL_TRANS_CLK_SEL_DISABLED;
1010 else
1011 val = TRANS_CLK_SEL_DISABLED;
1012
1013 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
1014 }
1015
_skl_ddi_set_iboost(struct drm_i915_private * dev_priv,enum port port,u8 iboost)1016 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1017 enum port port, u8 iboost)
1018 {
1019 u32 tmp;
1020
1021 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
1022 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1023 if (iboost)
1024 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1025 else
1026 tmp |= BALANCE_LEG_DISABLE(port);
1027 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
1028 }
1029
skl_ddi_set_iboost(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int level)1030 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
1031 const struct intel_crtc_state *crtc_state,
1032 int level)
1033 {
1034 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1035 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1036 u8 iboost;
1037
1038 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1039 iboost = intel_bios_hdmi_boost_level(encoder->devdata);
1040 else
1041 iboost = intel_bios_dp_boost_level(encoder->devdata);
1042
1043 if (iboost == 0) {
1044 const struct intel_ddi_buf_trans *trans;
1045 int n_entries;
1046
1047 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1048 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1049 return;
1050
1051 iboost = trans->entries[level].hsw.i_boost;
1052 }
1053
1054 /* Make sure that the requested I_boost is valid */
1055 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1056 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
1057 return;
1058 }
1059
1060 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
1061
1062 if (encoder->port == PORT_A && dig_port->max_lanes == 4)
1063 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1064 }
1065
intel_ddi_dp_voltage_max(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)1066 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
1067 const struct intel_crtc_state *crtc_state)
1068 {
1069 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1070 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1071 int n_entries;
1072
1073 encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1074
1075 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
1076 n_entries = 1;
1077 if (drm_WARN_ON(&dev_priv->drm,
1078 n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1079 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1080
1081 return index_to_dp_signal_levels[n_entries - 1] &
1082 DP_TRAIN_VOLTAGE_SWING_MASK;
1083 }
1084
1085 /*
1086 * We assume that the full set of pre-emphasis values can be
1087 * used on all DDI platforms. Should that change we need to
1088 * rethink this code.
1089 */
intel_ddi_dp_preemph_max(struct intel_dp * intel_dp)1090 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
1091 {
1092 return DP_TRAIN_PRE_EMPH_LEVEL_3;
1093 }
1094
icl_combo_phy_loadgen_select(const struct intel_crtc_state * crtc_state,int lane)1095 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state,
1096 int lane)
1097 {
1098 if (crtc_state->port_clock > 600000)
1099 return 0;
1100
1101 if (crtc_state->lane_count == 4)
1102 return lane >= 1 ? LOADGEN_SELECT : 0;
1103 else
1104 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0;
1105 }
1106
icl_ddi_combo_vswing_program(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1107 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
1108 const struct intel_crtc_state *crtc_state)
1109 {
1110 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1111 const struct intel_ddi_buf_trans *trans;
1112 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1113 int n_entries, ln;
1114 u32 val;
1115
1116 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1117 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1118 return;
1119
1120 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
1121 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1122
1123 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
1124 intel_dp->hobl_active = is_hobl_buf_trans(trans);
1125 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
1126 intel_dp->hobl_active ? val : 0);
1127 }
1128
1129 /* Set PORT_TX_DW5 */
1130 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1131 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
1132 TAP2_DISABLE | TAP3_DISABLE);
1133 val |= SCALING_MODE_SEL(0x2);
1134 val |= RTERM_SELECT(0x6);
1135 val |= TAP3_DISABLE;
1136 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1137
1138 /* Program PORT_TX_DW2 */
1139 for (ln = 0; ln < 4; ln++) {
1140 int level = intel_ddi_level(encoder, crtc_state, ln);
1141
1142 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy),
1143 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK,
1144 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) |
1145 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) |
1146 RCOMP_SCALAR(0x98));
1147 }
1148
1149 /* Program PORT_TX_DW4 */
1150 /* We cannot write to GRP. It would overwrite individual loadgen. */
1151 for (ln = 0; ln < 4; ln++) {
1152 int level = intel_ddi_level(encoder, crtc_state, ln);
1153
1154 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1155 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK,
1156 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) |
1157 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) |
1158 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff));
1159 }
1160
1161 /* Program PORT_TX_DW7 */
1162 for (ln = 0; ln < 4; ln++) {
1163 int level = intel_ddi_level(encoder, crtc_state, ln);
1164
1165 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy),
1166 N_SCALAR_MASK,
1167 N_SCALAR(trans->entries[level].icl.dw7_n_scalar));
1168 }
1169 }
1170
icl_combo_phy_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1171 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
1172 const struct intel_crtc_state *crtc_state)
1173 {
1174 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1175 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1176 u32 val;
1177 int ln;
1178
1179 /*
1180 * 1. If port type is eDP or DP,
1181 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1182 * else clear to 0b.
1183 */
1184 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
1185 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1186 val &= ~COMMON_KEEPER_EN;
1187 else
1188 val |= COMMON_KEEPER_EN;
1189 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
1190
1191 /* 2. Program loadgen select */
1192 /*
1193 * Program PORT_TX_DW4 depending on Bit rate and used lanes
1194 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1195 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1196 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1197 */
1198 for (ln = 0; ln < 4; ln++) {
1199 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1200 LOADGEN_SELECT,
1201 icl_combo_phy_loadgen_select(crtc_state, ln));
1202 }
1203
1204 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1205 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy),
1206 0, SUS_CLOCK_CONFIG);
1207
1208 /* 4. Clear training enable to change swing values */
1209 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1210 val &= ~TX_TRAINING_EN;
1211 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1212
1213 /* 5. Program swing and de-emphasis */
1214 icl_ddi_combo_vswing_program(encoder, crtc_state);
1215
1216 /* 6. Set training enable to trigger update */
1217 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1218 val |= TX_TRAINING_EN;
1219 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1220 }
1221
icl_mg_phy_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1222 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
1223 const struct intel_crtc_state *crtc_state)
1224 {
1225 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1226 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1227 const struct intel_ddi_buf_trans *trans;
1228 int n_entries, ln;
1229
1230 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
1231 return;
1232
1233 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1234 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1235 return;
1236
1237 for (ln = 0; ln < 2; ln++) {
1238 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port),
1239 CRI_USE_FS32, 0);
1240 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port),
1241 CRI_USE_FS32, 0);
1242 }
1243
1244 /* Program MG_TX_SWINGCTRL with values from vswing table */
1245 for (ln = 0; ln < 2; ln++) {
1246 int level;
1247
1248 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1249
1250 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port),
1251 CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1252 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1253
1254 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1255
1256 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port),
1257 CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1258 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1259 }
1260
1261 /* Program MG_TX_DRVCTRL with values from vswing table */
1262 for (ln = 0; ln < 2; ln++) {
1263 int level;
1264
1265 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1266
1267 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port),
1268 CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1269 CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1270 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1271 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1272 CRI_TXDEEMPH_OVERRIDE_EN);
1273
1274 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1275
1276 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port),
1277 CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1278 CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1279 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1280 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1281 CRI_TXDEEMPH_OVERRIDE_EN);
1282
1283 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
1284 }
1285
1286 /*
1287 * Program MG_CLKHUB<LN, port being used> with value from frequency table
1288 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
1289 * values from table for which TX1 and TX2 enabled.
1290 */
1291 for (ln = 0; ln < 2; ln++) {
1292 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port),
1293 CFG_LOW_RATE_LKREN_EN,
1294 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0);
1295 }
1296
1297 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
1298 for (ln = 0; ln < 2; ln++) {
1299 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port),
1300 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1301 CFG_AMI_CK_DIV_OVERRIDE_EN,
1302 crtc_state->port_clock > 500000 ?
1303 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1304 CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1305
1306 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port),
1307 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1308 CFG_AMI_CK_DIV_OVERRIDE_EN,
1309 crtc_state->port_clock > 500000 ?
1310 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1311 CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1312 }
1313
1314 /* Program MG_TX_PISO_READLOAD with values from vswing table */
1315 for (ln = 0; ln < 2; ln++) {
1316 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
1317 0, CRI_CALCINIT);
1318 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
1319 0, CRI_CALCINIT);
1320 }
1321 }
1322
tgl_dkl_phy_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1323 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
1324 const struct intel_crtc_state *crtc_state)
1325 {
1326 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1327 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1328 const struct intel_ddi_buf_trans *trans;
1329 int n_entries, ln;
1330
1331 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
1332 return;
1333
1334 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1335 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1336 return;
1337
1338 for (ln = 0; ln < 2; ln++) {
1339 int level;
1340
1341 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
1342
1343 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1344
1345 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
1346 DKL_TX_PRESHOOT_COEFF_MASK |
1347 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1348 DKL_TX_VSWING_CONTROL_MASK,
1349 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1350 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1351 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1352
1353 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1354
1355 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
1356 DKL_TX_PRESHOOT_COEFF_MASK |
1357 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1358 DKL_TX_VSWING_CONTROL_MASK,
1359 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1360 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1361 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1362
1363 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
1364 DKL_TX_DP20BITMODE, 0);
1365
1366 if (IS_ALDERLAKE_P(dev_priv)) {
1367 u32 val;
1368
1369 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1370 if (ln == 0) {
1371 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1372 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2);
1373 } else {
1374 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3);
1375 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3);
1376 }
1377 } else {
1378 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1379 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
1380 }
1381
1382 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
1383 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
1384 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
1385 val);
1386 }
1387 }
1388 }
1389
translate_signal_level(struct intel_dp * intel_dp,u8 signal_levels)1390 static int translate_signal_level(struct intel_dp *intel_dp,
1391 u8 signal_levels)
1392 {
1393 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1394 int i;
1395
1396 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1397 if (index_to_dp_signal_levels[i] == signal_levels)
1398 return i;
1399 }
1400
1401 drm_WARN(&i915->drm, 1,
1402 "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1403 signal_levels);
1404
1405 return 0;
1406 }
1407
intel_ddi_dp_level(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int lane)1408 static int intel_ddi_dp_level(struct intel_dp *intel_dp,
1409 const struct intel_crtc_state *crtc_state,
1410 int lane)
1411 {
1412 u8 train_set = intel_dp->train_set[lane];
1413
1414 if (intel_dp_is_uhbr(crtc_state)) {
1415 return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
1416 } else {
1417 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1418 DP_TRAIN_PRE_EMPHASIS_MASK);
1419
1420 return translate_signal_level(intel_dp, signal_levels);
1421 }
1422 }
1423
intel_ddi_level(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int lane)1424 int intel_ddi_level(struct intel_encoder *encoder,
1425 const struct intel_crtc_state *crtc_state,
1426 int lane)
1427 {
1428 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1429 const struct intel_ddi_buf_trans *trans;
1430 int level, n_entries;
1431
1432 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1433 if (drm_WARN_ON_ONCE(&i915->drm, !trans))
1434 return 0;
1435
1436 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1437 level = intel_ddi_hdmi_level(encoder, trans);
1438 else
1439 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state,
1440 lane);
1441
1442 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries))
1443 level = n_entries - 1;
1444
1445 return level;
1446 }
1447
1448 static void
hsw_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1449 hsw_set_signal_levels(struct intel_encoder *encoder,
1450 const struct intel_crtc_state *crtc_state)
1451 {
1452 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1453 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1454 int level = intel_ddi_level(encoder, crtc_state, 0);
1455 enum port port = encoder->port;
1456 u32 signal_levels;
1457
1458 if (has_iboost(dev_priv))
1459 skl_ddi_set_iboost(encoder, crtc_state, level);
1460
1461 /* HDMI ignores the rest */
1462 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1463 return;
1464
1465 signal_levels = DDI_BUF_TRANS_SELECT(level);
1466
1467 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1468 signal_levels);
1469
1470 intel_dp->DP &= ~DDI_BUF_EMP_MASK;
1471 intel_dp->DP |= signal_levels;
1472
1473 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
1474 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
1475 }
1476
_icl_ddi_enable_clock(struct drm_i915_private * i915,i915_reg_t reg,u32 clk_sel_mask,u32 clk_sel,u32 clk_off)1477 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1478 u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
1479 {
1480 mutex_lock(&i915->display.dpll.lock);
1481
1482 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
1483
1484 /*
1485 * "This step and the step before must be
1486 * done with separate register writes."
1487 */
1488 intel_de_rmw(i915, reg, clk_off, 0);
1489
1490 mutex_unlock(&i915->display.dpll.lock);
1491 }
1492
_icl_ddi_disable_clock(struct drm_i915_private * i915,i915_reg_t reg,u32 clk_off)1493 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1494 u32 clk_off)
1495 {
1496 mutex_lock(&i915->display.dpll.lock);
1497
1498 intel_de_rmw(i915, reg, 0, clk_off);
1499
1500 mutex_unlock(&i915->display.dpll.lock);
1501 }
1502
_icl_ddi_is_clock_enabled(struct drm_i915_private * i915,i915_reg_t reg,u32 clk_off)1503 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
1504 u32 clk_off)
1505 {
1506 return !(intel_de_read(i915, reg) & clk_off);
1507 }
1508
1509 static struct intel_shared_dpll *
_icl_ddi_get_pll(struct drm_i915_private * i915,i915_reg_t reg,u32 clk_sel_mask,u32 clk_sel_shift)1510 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
1511 u32 clk_sel_mask, u32 clk_sel_shift)
1512 {
1513 enum intel_dpll_id id;
1514
1515 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
1516
1517 return intel_get_shared_dpll_by_id(i915, id);
1518 }
1519
adls_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1520 static void adls_ddi_enable_clock(struct intel_encoder *encoder,
1521 const struct intel_crtc_state *crtc_state)
1522 {
1523 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1524 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1525 enum phy phy = intel_port_to_phy(i915, encoder->port);
1526
1527 if (drm_WARN_ON(&i915->drm, !pll))
1528 return;
1529
1530 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1531 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1532 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
1533 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1534 }
1535
adls_ddi_disable_clock(struct intel_encoder * encoder)1536 static void adls_ddi_disable_clock(struct intel_encoder *encoder)
1537 {
1538 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1539 enum phy phy = intel_port_to_phy(i915, encoder->port);
1540
1541 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1542 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1543 }
1544
adls_ddi_is_clock_enabled(struct intel_encoder * encoder)1545 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
1546 {
1547 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1548 enum phy phy = intel_port_to_phy(i915, encoder->port);
1549
1550 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
1551 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1552 }
1553
adls_ddi_get_pll(struct intel_encoder * encoder)1554 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
1555 {
1556 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1557 enum phy phy = intel_port_to_phy(i915, encoder->port);
1558
1559 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
1560 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1561 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
1562 }
1563
rkl_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1564 static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
1565 const struct intel_crtc_state *crtc_state)
1566 {
1567 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1568 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1569 enum phy phy = intel_port_to_phy(i915, encoder->port);
1570
1571 if (drm_WARN_ON(&i915->drm, !pll))
1572 return;
1573
1574 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1575 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1576 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1577 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1578 }
1579
rkl_ddi_disable_clock(struct intel_encoder * encoder)1580 static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
1581 {
1582 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1583 enum phy phy = intel_port_to_phy(i915, encoder->port);
1584
1585 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1586 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1587 }
1588
rkl_ddi_is_clock_enabled(struct intel_encoder * encoder)1589 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1590 {
1591 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1592 enum phy phy = intel_port_to_phy(i915, encoder->port);
1593
1594 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1595 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1596 }
1597
rkl_ddi_get_pll(struct intel_encoder * encoder)1598 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
1599 {
1600 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1601 enum phy phy = intel_port_to_phy(i915, encoder->port);
1602
1603 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1604 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1605 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1606 }
1607
dg1_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1608 static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
1609 const struct intel_crtc_state *crtc_state)
1610 {
1611 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1612 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1613 enum phy phy = intel_port_to_phy(i915, encoder->port);
1614
1615 if (drm_WARN_ON(&i915->drm, !pll))
1616 return;
1617
1618 /*
1619 * If we fail this, something went very wrong: first 2 PLLs should be
1620 * used by first 2 phys and last 2 PLLs by last phys
1621 */
1622 if (drm_WARN_ON(&i915->drm,
1623 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
1624 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
1625 return;
1626
1627 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1628 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1629 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1630 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1631 }
1632
dg1_ddi_disable_clock(struct intel_encoder * encoder)1633 static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
1634 {
1635 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1636 enum phy phy = intel_port_to_phy(i915, encoder->port);
1637
1638 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1639 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1640 }
1641
dg1_ddi_is_clock_enabled(struct intel_encoder * encoder)1642 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
1643 {
1644 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1645 enum phy phy = intel_port_to_phy(i915, encoder->port);
1646
1647 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
1648 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1649 }
1650
dg1_ddi_get_pll(struct intel_encoder * encoder)1651 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
1652 {
1653 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1654 enum phy phy = intel_port_to_phy(i915, encoder->port);
1655 enum intel_dpll_id id;
1656 u32 val;
1657
1658 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
1659 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1660 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
1661 id = val;
1662
1663 /*
1664 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A
1665 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one
1666 * bit for phy C and D.
1667 */
1668 if (phy >= PHY_C)
1669 id += DPLL_ID_DG1_DPLL2;
1670
1671 return intel_get_shared_dpll_by_id(i915, id);
1672 }
1673
icl_ddi_combo_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1674 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
1675 const struct intel_crtc_state *crtc_state)
1676 {
1677 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1678 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1679 enum phy phy = intel_port_to_phy(i915, encoder->port);
1680
1681 if (drm_WARN_ON(&i915->drm, !pll))
1682 return;
1683
1684 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1685 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1686 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1687 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1688 }
1689
icl_ddi_combo_disable_clock(struct intel_encoder * encoder)1690 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
1691 {
1692 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1693 enum phy phy = intel_port_to_phy(i915, encoder->port);
1694
1695 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1696 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1697 }
1698
icl_ddi_combo_is_clock_enabled(struct intel_encoder * encoder)1699 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
1700 {
1701 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1702 enum phy phy = intel_port_to_phy(i915, encoder->port);
1703
1704 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1705 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1706 }
1707
icl_ddi_combo_get_pll(struct intel_encoder * encoder)1708 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
1709 {
1710 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1711 enum phy phy = intel_port_to_phy(i915, encoder->port);
1712
1713 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1714 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1715 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1716 }
1717
jsl_ddi_tc_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1718 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1719 const struct intel_crtc_state *crtc_state)
1720 {
1721 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1722 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1723 enum port port = encoder->port;
1724
1725 if (drm_WARN_ON(&i915->drm, !pll))
1726 return;
1727
1728 /*
1729 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
1730 * MG does not exist, but the programming is required to ungate DDIC and DDID."
1731 */
1732 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
1733
1734 icl_ddi_combo_enable_clock(encoder, crtc_state);
1735 }
1736
jsl_ddi_tc_disable_clock(struct intel_encoder * encoder)1737 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1738 {
1739 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1740 enum port port = encoder->port;
1741
1742 icl_ddi_combo_disable_clock(encoder);
1743
1744 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1745 }
1746
jsl_ddi_tc_is_clock_enabled(struct intel_encoder * encoder)1747 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1748 {
1749 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1750 enum port port = encoder->port;
1751 u32 tmp;
1752
1753 tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1754
1755 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1756 return false;
1757
1758 return icl_ddi_combo_is_clock_enabled(encoder);
1759 }
1760
icl_ddi_tc_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1761 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1762 const struct intel_crtc_state *crtc_state)
1763 {
1764 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1765 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1766 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1767 enum port port = encoder->port;
1768
1769 if (drm_WARN_ON(&i915->drm, !pll))
1770 return;
1771
1772 intel_de_write(i915, DDI_CLK_SEL(port),
1773 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
1774
1775 mutex_lock(&i915->display.dpll.lock);
1776
1777 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1778 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
1779
1780 mutex_unlock(&i915->display.dpll.lock);
1781 }
1782
icl_ddi_tc_disable_clock(struct intel_encoder * encoder)1783 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1784 {
1785 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1786 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1787 enum port port = encoder->port;
1788
1789 mutex_lock(&i915->display.dpll.lock);
1790
1791 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1792 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1793
1794 mutex_unlock(&i915->display.dpll.lock);
1795
1796 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1797 }
1798
icl_ddi_tc_is_clock_enabled(struct intel_encoder * encoder)1799 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1800 {
1801 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1802 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1803 enum port port = encoder->port;
1804 u32 tmp;
1805
1806 tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1807
1808 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1809 return false;
1810
1811 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0);
1812
1813 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1814 }
1815
icl_ddi_tc_get_pll(struct intel_encoder * encoder)1816 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
1817 {
1818 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1819 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1820 enum port port = encoder->port;
1821 enum intel_dpll_id id;
1822 u32 tmp;
1823
1824 tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1825
1826 switch (tmp & DDI_CLK_SEL_MASK) {
1827 case DDI_CLK_SEL_TBT_162:
1828 case DDI_CLK_SEL_TBT_270:
1829 case DDI_CLK_SEL_TBT_540:
1830 case DDI_CLK_SEL_TBT_810:
1831 id = DPLL_ID_ICL_TBTPLL;
1832 break;
1833 case DDI_CLK_SEL_MG:
1834 id = icl_tc_port_to_pll_id(tc_port);
1835 break;
1836 default:
1837 MISSING_CASE(tmp);
1838 fallthrough;
1839 case DDI_CLK_SEL_NONE:
1840 return NULL;
1841 }
1842
1843 return intel_get_shared_dpll_by_id(i915, id);
1844 }
1845
bxt_ddi_get_pll(struct intel_encoder * encoder)1846 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
1847 {
1848 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1849 enum intel_dpll_id id;
1850
1851 switch (encoder->port) {
1852 case PORT_A:
1853 id = DPLL_ID_SKL_DPLL0;
1854 break;
1855 case PORT_B:
1856 id = DPLL_ID_SKL_DPLL1;
1857 break;
1858 case PORT_C:
1859 id = DPLL_ID_SKL_DPLL2;
1860 break;
1861 default:
1862 MISSING_CASE(encoder->port);
1863 return NULL;
1864 }
1865
1866 return intel_get_shared_dpll_by_id(i915, id);
1867 }
1868
skl_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1869 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
1870 const struct intel_crtc_state *crtc_state)
1871 {
1872 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1873 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1874 enum port port = encoder->port;
1875
1876 if (drm_WARN_ON(&i915->drm, !pll))
1877 return;
1878
1879 mutex_lock(&i915->display.dpll.lock);
1880
1881 intel_de_rmw(i915, DPLL_CTRL2,
1882 DPLL_CTRL2_DDI_CLK_OFF(port) |
1883 DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
1884 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
1885 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1886
1887 mutex_unlock(&i915->display.dpll.lock);
1888 }
1889
skl_ddi_disable_clock(struct intel_encoder * encoder)1890 static void skl_ddi_disable_clock(struct intel_encoder *encoder)
1891 {
1892 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1893 enum port port = encoder->port;
1894
1895 mutex_lock(&i915->display.dpll.lock);
1896
1897 intel_de_rmw(i915, DPLL_CTRL2,
1898 0, DPLL_CTRL2_DDI_CLK_OFF(port));
1899
1900 mutex_unlock(&i915->display.dpll.lock);
1901 }
1902
skl_ddi_is_clock_enabled(struct intel_encoder * encoder)1903 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1904 {
1905 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1906 enum port port = encoder->port;
1907
1908 /*
1909 * FIXME Not sure if the override affects both
1910 * the PLL selection and the CLK_OFF bit.
1911 */
1912 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
1913 }
1914
skl_ddi_get_pll(struct intel_encoder * encoder)1915 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
1916 {
1917 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1918 enum port port = encoder->port;
1919 enum intel_dpll_id id;
1920 u32 tmp;
1921
1922 tmp = intel_de_read(i915, DPLL_CTRL2);
1923
1924 /*
1925 * FIXME Not sure if the override affects both
1926 * the PLL selection and the CLK_OFF bit.
1927 */
1928 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
1929 return NULL;
1930
1931 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
1932 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
1933
1934 return intel_get_shared_dpll_by_id(i915, id);
1935 }
1936
hsw_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1937 void hsw_ddi_enable_clock(struct intel_encoder *encoder,
1938 const struct intel_crtc_state *crtc_state)
1939 {
1940 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1941 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1942 enum port port = encoder->port;
1943
1944 if (drm_WARN_ON(&i915->drm, !pll))
1945 return;
1946
1947 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
1948 }
1949
hsw_ddi_disable_clock(struct intel_encoder * encoder)1950 void hsw_ddi_disable_clock(struct intel_encoder *encoder)
1951 {
1952 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1953 enum port port = encoder->port;
1954
1955 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1956 }
1957
hsw_ddi_is_clock_enabled(struct intel_encoder * encoder)1958 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
1959 {
1960 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1961 enum port port = encoder->port;
1962
1963 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
1964 }
1965
hsw_ddi_get_pll(struct intel_encoder * encoder)1966 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
1967 {
1968 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1969 enum port port = encoder->port;
1970 enum intel_dpll_id id;
1971 u32 tmp;
1972
1973 tmp = intel_de_read(i915, PORT_CLK_SEL(port));
1974
1975 switch (tmp & PORT_CLK_SEL_MASK) {
1976 case PORT_CLK_SEL_WRPLL1:
1977 id = DPLL_ID_WRPLL1;
1978 break;
1979 case PORT_CLK_SEL_WRPLL2:
1980 id = DPLL_ID_WRPLL2;
1981 break;
1982 case PORT_CLK_SEL_SPLL:
1983 id = DPLL_ID_SPLL;
1984 break;
1985 case PORT_CLK_SEL_LCPLL_810:
1986 id = DPLL_ID_LCPLL_810;
1987 break;
1988 case PORT_CLK_SEL_LCPLL_1350:
1989 id = DPLL_ID_LCPLL_1350;
1990 break;
1991 case PORT_CLK_SEL_LCPLL_2700:
1992 id = DPLL_ID_LCPLL_2700;
1993 break;
1994 default:
1995 MISSING_CASE(tmp);
1996 fallthrough;
1997 case PORT_CLK_SEL_NONE:
1998 return NULL;
1999 }
2000
2001 return intel_get_shared_dpll_by_id(i915, id);
2002 }
2003
intel_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2004 void intel_ddi_enable_clock(struct intel_encoder *encoder,
2005 const struct intel_crtc_state *crtc_state)
2006 {
2007 if (encoder->enable_clock)
2008 encoder->enable_clock(encoder, crtc_state);
2009 }
2010
intel_ddi_disable_clock(struct intel_encoder * encoder)2011 void intel_ddi_disable_clock(struct intel_encoder *encoder)
2012 {
2013 if (encoder->disable_clock)
2014 encoder->disable_clock(encoder);
2015 }
2016
intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder * encoder)2017 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2018 {
2019 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2020 u32 port_mask;
2021 bool ddi_clk_needed;
2022
2023 /*
2024 * In case of DP MST, we sanitize the primary encoder only, not the
2025 * virtual ones.
2026 */
2027 if (encoder->type == INTEL_OUTPUT_DP_MST)
2028 return;
2029
2030 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2031 u8 pipe_mask;
2032 bool is_mst;
2033
2034 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2035 /*
2036 * In the unlikely case that BIOS enables DP in MST mode, just
2037 * warn since our MST HW readout is incomplete.
2038 */
2039 if (drm_WARN_ON(&i915->drm, is_mst))
2040 return;
2041 }
2042
2043 port_mask = BIT(encoder->port);
2044 ddi_clk_needed = encoder->base.crtc;
2045
2046 if (encoder->type == INTEL_OUTPUT_DSI) {
2047 struct intel_encoder *other_encoder;
2048
2049 port_mask = intel_dsi_encoder_ports(encoder);
2050 /*
2051 * Sanity check that we haven't incorrectly registered another
2052 * encoder using any of the ports of this DSI encoder.
2053 */
2054 for_each_intel_encoder(&i915->drm, other_encoder) {
2055 if (other_encoder == encoder)
2056 continue;
2057
2058 if (drm_WARN_ON(&i915->drm,
2059 port_mask & BIT(other_encoder->port)))
2060 return;
2061 }
2062 /*
2063 * For DSI we keep the ddi clocks gated
2064 * except during enable/disable sequence.
2065 */
2066 ddi_clk_needed = false;
2067 }
2068
2069 if (ddi_clk_needed || !encoder->is_clock_enabled ||
2070 !encoder->is_clock_enabled(encoder))
2071 return;
2072
2073 drm_notice(&i915->drm,
2074 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2075 encoder->base.base.id, encoder->base.name);
2076
2077 encoder->disable_clock(encoder);
2078 }
2079
2080 static void
icl_program_mg_dp_mode(struct intel_digital_port * dig_port,const struct intel_crtc_state * crtc_state)2081 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
2082 const struct intel_crtc_state *crtc_state)
2083 {
2084 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2085 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
2086 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
2087 u32 ln0, ln1, pin_assignment;
2088 u8 width;
2089
2090 if (!intel_phy_is_tc(dev_priv, phy) ||
2091 intel_tc_port_in_tbt_alt_mode(dig_port))
2092 return;
2093
2094 if (DISPLAY_VER(dev_priv) >= 12) {
2095 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0));
2096 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1));
2097 } else {
2098 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
2099 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
2100 }
2101
2102 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2103 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2104
2105 /* DPPATC */
2106 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
2107 width = crtc_state->lane_count;
2108
2109 switch (pin_assignment) {
2110 case 0x0:
2111 drm_WARN_ON(&dev_priv->drm,
2112 !intel_tc_port_in_legacy_mode(dig_port));
2113 if (width == 1) {
2114 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2115 } else {
2116 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2117 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2118 }
2119 break;
2120 case 0x1:
2121 if (width == 4) {
2122 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2123 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2124 }
2125 break;
2126 case 0x2:
2127 if (width == 2) {
2128 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2129 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2130 }
2131 break;
2132 case 0x3:
2133 case 0x5:
2134 if (width == 1) {
2135 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2136 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2137 } else {
2138 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2139 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2140 }
2141 break;
2142 case 0x4:
2143 case 0x6:
2144 if (width == 1) {
2145 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2146 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2147 } else {
2148 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2149 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2150 }
2151 break;
2152 default:
2153 MISSING_CASE(pin_assignment);
2154 }
2155
2156 if (DISPLAY_VER(dev_priv) >= 12) {
2157 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
2158 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
2159 } else {
2160 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
2161 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
2162 }
2163 }
2164
2165 static enum transcoder
tgl_dp_tp_transcoder(const struct intel_crtc_state * crtc_state)2166 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
2167 {
2168 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2169 return crtc_state->mst_master_transcoder;
2170 else
2171 return crtc_state->cpu_transcoder;
2172 }
2173
dp_tp_ctl_reg(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2174 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
2175 const struct intel_crtc_state *crtc_state)
2176 {
2177 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2178
2179 if (DISPLAY_VER(dev_priv) >= 12)
2180 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
2181 else
2182 return DP_TP_CTL(encoder->port);
2183 }
2184
dp_tp_status_reg(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2185 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
2186 const struct intel_crtc_state *crtc_state)
2187 {
2188 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2189
2190 if (DISPLAY_VER(dev_priv) >= 12)
2191 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
2192 else
2193 return DP_TP_STATUS(encoder->port);
2194 }
2195
intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,bool enable)2196 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
2197 const struct intel_crtc_state *crtc_state,
2198 bool enable)
2199 {
2200 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2201
2202 if (!crtc_state->vrr.enable)
2203 return;
2204
2205 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
2206 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
2207 drm_dbg_kms(&i915->drm,
2208 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
2209 str_enable_disable(enable));
2210 }
2211
intel_dp_sink_set_fec_ready(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)2212 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
2213 const struct intel_crtc_state *crtc_state)
2214 {
2215 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2216
2217 if (!crtc_state->fec_enable)
2218 return;
2219
2220 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
2221 drm_dbg_kms(&i915->drm,
2222 "Failed to set FEC_READY in the sink\n");
2223 }
2224
intel_ddi_enable_fec(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2225 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2226 const struct intel_crtc_state *crtc_state)
2227 {
2228 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2229
2230 if (!crtc_state->fec_enable)
2231 return;
2232
2233 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
2234 0, DP_TP_CTL_FEC_ENABLE);
2235 }
2236
intel_ddi_disable_fec_state(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2237 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
2238 const struct intel_crtc_state *crtc_state)
2239 {
2240 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2241
2242 if (!crtc_state->fec_enable)
2243 return;
2244
2245 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
2246 DP_TP_CTL_FEC_ENABLE, 0);
2247 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2248 }
2249
intel_ddi_power_up_lanes(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2250 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
2251 const struct intel_crtc_state *crtc_state)
2252 {
2253 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2254 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2255 enum phy phy = intel_port_to_phy(i915, encoder->port);
2256
2257 if (intel_phy_is_combo(i915, phy)) {
2258 bool lane_reversal =
2259 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
2260
2261 intel_combo_phy_power_up_lanes(i915, phy, false,
2262 crtc_state->lane_count,
2263 lane_reversal);
2264 }
2265 }
2266
2267 /* Splitter enable for eDP MSO is limited to certain pipes. */
intel_ddi_splitter_pipe_mask(struct drm_i915_private * i915)2268 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
2269 {
2270 if (IS_ALDERLAKE_P(i915))
2271 return BIT(PIPE_A) | BIT(PIPE_B);
2272 else
2273 return BIT(PIPE_A);
2274 }
2275
intel_ddi_mso_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)2276 static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
2277 struct intel_crtc_state *pipe_config)
2278 {
2279 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2280 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2281 enum pipe pipe = crtc->pipe;
2282 u32 dss1;
2283
2284 if (!HAS_MSO(i915))
2285 return;
2286
2287 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
2288
2289 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
2290 if (!pipe_config->splitter.enable)
2291 return;
2292
2293 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) {
2294 pipe_config->splitter.enable = false;
2295 return;
2296 }
2297
2298 switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
2299 default:
2300 drm_WARN(&i915->drm, true,
2301 "Invalid splitter configuration, dss1=0x%08x\n", dss1);
2302 fallthrough;
2303 case SPLITTER_CONFIGURATION_2_SEGMENT:
2304 pipe_config->splitter.link_count = 2;
2305 break;
2306 case SPLITTER_CONFIGURATION_4_SEGMENT:
2307 pipe_config->splitter.link_count = 4;
2308 break;
2309 }
2310
2311 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
2312 }
2313
intel_ddi_mso_configure(const struct intel_crtc_state * crtc_state)2314 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
2315 {
2316 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2317 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2318 enum pipe pipe = crtc->pipe;
2319 u32 dss1 = 0;
2320
2321 if (!HAS_MSO(i915))
2322 return;
2323
2324 if (crtc_state->splitter.enable) {
2325 dss1 |= SPLITTER_ENABLE;
2326 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
2327 if (crtc_state->splitter.link_count == 2)
2328 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
2329 else
2330 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
2331 }
2332
2333 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
2334 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
2335 OVERLAP_PIXELS_MASK, dss1);
2336 }
2337
mtl_get_port_width(u8 lane_count)2338 static u8 mtl_get_port_width(u8 lane_count)
2339 {
2340 switch (lane_count) {
2341 case 1:
2342 return 0;
2343 case 2:
2344 return 1;
2345 case 3:
2346 return 4;
2347 case 4:
2348 return 3;
2349 default:
2350 MISSING_CASE(lane_count);
2351 return 4;
2352 }
2353 }
2354
2355 static void
mtl_ddi_enable_d2d(struct intel_encoder * encoder)2356 mtl_ddi_enable_d2d(struct intel_encoder *encoder)
2357 {
2358 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2359 enum port port = encoder->port;
2360
2361 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0,
2362 XELPDP_PORT_BUF_D2D_LINK_ENABLE);
2363
2364 if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
2365 XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) {
2366 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for PORT_BUF_CTL %c\n",
2367 port_name(port));
2368 }
2369 }
2370
mtl_port_buf_ctl_program(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2371 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
2372 const struct intel_crtc_state *crtc_state)
2373 {
2374 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2375 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2376 enum port port = encoder->port;
2377 u32 val;
2378
2379 val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
2380 val &= ~XELPDP_PORT_WIDTH_MASK;
2381 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
2382
2383 val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK;
2384 if (intel_dp_is_uhbr(crtc_state))
2385 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT;
2386 else
2387 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT;
2388
2389 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
2390 val |= XELPDP_PORT_REVERSAL;
2391
2392 intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
2393 }
2394
mtl_port_buf_ctl_io_selection(struct intel_encoder * encoder)2395 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
2396 {
2397 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2398 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2399 u32 val;
2400
2401 val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
2402 XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
2403 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port),
2404 XELPDP_PORT_BUF_IO_SELECT_TBT, val);
2405 }
2406
mtl_ddi_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2407 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2408 struct intel_encoder *encoder,
2409 const struct intel_crtc_state *crtc_state,
2410 const struct drm_connector_state *conn_state)
2411 {
2412 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2413 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2414
2415 intel_dp_set_link_params(intel_dp,
2416 crtc_state->port_clock,
2417 crtc_state->lane_count);
2418
2419 /*
2420 * We only configure what the register value will be here. Actual
2421 * enabling happens during link training farther down.
2422 */
2423 intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2424
2425 /*
2426 * 1. Enable Power Wells
2427 *
2428 * This was handled at the beginning of intel_atomic_commit_tail(),
2429 * before we called down into this function.
2430 */
2431
2432 /* 2. PMdemand was already set */
2433
2434 /* 3. Select Thunderbolt */
2435 mtl_port_buf_ctl_io_selection(encoder);
2436
2437 /* 4. Enable Panel Power if PPS is required */
2438 intel_pps_on(intel_dp);
2439
2440 /* 5. Enable the port PLL */
2441 intel_ddi_enable_clock(encoder, crtc_state);
2442
2443 /*
2444 * 6.a Configure Transcoder Clock Select to direct the Port clock to the
2445 * Transcoder.
2446 */
2447 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2448
2449 /*
2450 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings.
2451 */
2452 intel_ddi_config_transcoder_dp2(encoder, crtc_state);
2453
2454 /*
2455 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2456 * Transport Select
2457 */
2458 intel_ddi_config_transcoder_func(encoder, crtc_state);
2459
2460 /*
2461 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2462 */
2463 intel_ddi_mso_configure(crtc_state);
2464
2465 if (!is_mst)
2466 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2467
2468 intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2469 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2470 /*
2471 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2472 * in the FEC_CONFIGURATION register to 1 before initiating link
2473 * training
2474 */
2475 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2476
2477 intel_dp_check_frl_training(intel_dp);
2478 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2479
2480 /*
2481 * 6. The rest of the below are substeps under the bspec's "Enable and
2482 * Train Display Port" step. Note that steps that are specific to
2483 * MST will be handled by intel_mst_pre_enable_dp() before/after it
2484 * calls into this function. Also intel_mst_pre_enable_dp() only calls
2485 * us when active_mst_links==0, so any steps designated for "single
2486 * stream or multi-stream master transcoder" can just be performed
2487 * unconditionally here.
2488 *
2489 * mtl_ddi_prepare_link_retrain() that is called by
2490 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h,
2491 * 6.i and 6.j
2492 *
2493 * 6.k Follow DisplayPort specification training sequence (see notes for
2494 * failure handling)
2495 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2496 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2497 * (timeout after 800 us)
2498 */
2499 intel_dp_start_link_train(intel_dp, crtc_state);
2500
2501 /* 6.n Set DP_TP_CTL link training to Normal */
2502 if (!is_trans_port_sync_mode(crtc_state))
2503 intel_dp_stop_link_train(intel_dp, crtc_state);
2504
2505 /* 6.o Configure and enable FEC if needed */
2506 intel_ddi_enable_fec(encoder, crtc_state);
2507
2508 intel_dsc_dp_pps_write(encoder, crtc_state);
2509 }
2510
tgl_ddi_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2511 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2512 struct intel_encoder *encoder,
2513 const struct intel_crtc_state *crtc_state,
2514 const struct drm_connector_state *conn_state)
2515 {
2516 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2517 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2518 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2519 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2520
2521 intel_dp_set_link_params(intel_dp,
2522 crtc_state->port_clock,
2523 crtc_state->lane_count);
2524
2525 /*
2526 * We only configure what the register value will be here. Actual
2527 * enabling happens during link training farther down.
2528 */
2529 intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2530
2531 /*
2532 * 1. Enable Power Wells
2533 *
2534 * This was handled at the beginning of intel_atomic_commit_tail(),
2535 * before we called down into this function.
2536 */
2537
2538 /* 2. Enable Panel Power if PPS is required */
2539 intel_pps_on(intel_dp);
2540
2541 /*
2542 * 3. For non-TBT Type-C ports, set FIA lane count
2543 * (DFLEXDPSP.DPX4TXLATC)
2544 *
2545 * This was done before tgl_ddi_pre_enable_dp by
2546 * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
2547 */
2548
2549 /*
2550 * 4. Enable the port PLL.
2551 *
2552 * The PLL enabling itself was already done before this function by
2553 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
2554 * configure the PLL to port mapping here.
2555 */
2556 intel_ddi_enable_clock(encoder, crtc_state);
2557
2558 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
2559 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2560 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2561 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2562 dig_port->ddi_io_power_domain);
2563 }
2564
2565 /* 6. Program DP_MODE */
2566 icl_program_mg_dp_mode(dig_port, crtc_state);
2567
2568 /*
2569 * 7. The rest of the below are substeps under the bspec's "Enable and
2570 * Train Display Port" step. Note that steps that are specific to
2571 * MST will be handled by intel_mst_pre_enable_dp() before/after it
2572 * calls into this function. Also intel_mst_pre_enable_dp() only calls
2573 * us when active_mst_links==0, so any steps designated for "single
2574 * stream or multi-stream master transcoder" can just be performed
2575 * unconditionally here.
2576 */
2577
2578 /*
2579 * 7.a Configure Transcoder Clock Select to direct the Port clock to the
2580 * Transcoder.
2581 */
2582 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2583
2584 if (HAS_DP20(dev_priv))
2585 intel_ddi_config_transcoder_dp2(encoder, crtc_state);
2586
2587 /*
2588 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2589 * Transport Select
2590 */
2591 intel_ddi_config_transcoder_func(encoder, crtc_state);
2592
2593 /*
2594 * 7.c Configure & enable DP_TP_CTL with link training pattern 1
2595 * selected
2596 *
2597 * This will be handled by the intel_dp_start_link_train() farther
2598 * down this function.
2599 */
2600
2601 /* 7.e Configure voltage swing and related IO settings */
2602 encoder->set_signal_levels(encoder, crtc_state);
2603
2604 /*
2605 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
2606 * the used lanes of the DDI.
2607 */
2608 intel_ddi_power_up_lanes(encoder, crtc_state);
2609
2610 /*
2611 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2612 */
2613 intel_ddi_mso_configure(crtc_state);
2614
2615 if (!is_mst)
2616 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2617
2618 intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2619 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2620 /*
2621 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2622 * in the FEC_CONFIGURATION register to 1 before initiating link
2623 * training
2624 */
2625 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2626
2627 intel_dp_check_frl_training(intel_dp);
2628 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2629
2630 /*
2631 * 7.i Follow DisplayPort specification training sequence (see notes for
2632 * failure handling)
2633 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2634 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2635 * (timeout after 800 us)
2636 */
2637 intel_dp_start_link_train(intel_dp, crtc_state);
2638
2639 /* 7.k Set DP_TP_CTL link training to Normal */
2640 if (!is_trans_port_sync_mode(crtc_state))
2641 intel_dp_stop_link_train(intel_dp, crtc_state);
2642
2643 /* 7.l Configure and enable FEC if needed */
2644 intel_ddi_enable_fec(encoder, crtc_state);
2645
2646 intel_dsc_dp_pps_write(encoder, crtc_state);
2647 }
2648
hsw_ddi_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2649 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
2650 struct intel_encoder *encoder,
2651 const struct intel_crtc_state *crtc_state,
2652 const struct drm_connector_state *conn_state)
2653 {
2654 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2655 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2656 enum port port = encoder->port;
2657 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2658 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2659
2660 if (DISPLAY_VER(dev_priv) < 11)
2661 drm_WARN_ON(&dev_priv->drm,
2662 is_mst && (port == PORT_A || port == PORT_E));
2663 else
2664 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
2665
2666 intel_dp_set_link_params(intel_dp,
2667 crtc_state->port_clock,
2668 crtc_state->lane_count);
2669
2670 /*
2671 * We only configure what the register value will be here. Actual
2672 * enabling happens during link training farther down.
2673 */
2674 intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2675
2676 intel_pps_on(intel_dp);
2677
2678 intel_ddi_enable_clock(encoder, crtc_state);
2679
2680 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2681 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2682 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2683 dig_port->ddi_io_power_domain);
2684 }
2685
2686 icl_program_mg_dp_mode(dig_port, crtc_state);
2687
2688 if (has_buf_trans_select(dev_priv))
2689 hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
2690
2691 encoder->set_signal_levels(encoder, crtc_state);
2692
2693 intel_ddi_power_up_lanes(encoder, crtc_state);
2694
2695 if (!is_mst)
2696 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2697 intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2698 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
2699 true);
2700 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2701 intel_dp_start_link_train(intel_dp, crtc_state);
2702 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
2703 !is_trans_port_sync_mode(crtc_state))
2704 intel_dp_stop_link_train(intel_dp, crtc_state);
2705
2706 intel_ddi_enable_fec(encoder, crtc_state);
2707
2708 if (!is_mst)
2709 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2710
2711 intel_dsc_dp_pps_write(encoder, crtc_state);
2712 }
2713
intel_ddi_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2714 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
2715 struct intel_encoder *encoder,
2716 const struct intel_crtc_state *crtc_state,
2717 const struct drm_connector_state *conn_state)
2718 {
2719 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2720
2721 if (HAS_DP20(dev_priv))
2722 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
2723 crtc_state);
2724
2725 if (DISPLAY_VER(dev_priv) >= 14)
2726 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2727 else if (DISPLAY_VER(dev_priv) >= 12)
2728 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2729 else
2730 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2731
2732 /* MST will call a setting of MSA after an allocating of Virtual Channel
2733 * from MST encoder pre_enable callback.
2734 */
2735 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2736 intel_ddi_set_dp_msa(crtc_state, conn_state);
2737 }
2738
intel_ddi_pre_enable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2739 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
2740 struct intel_encoder *encoder,
2741 const struct intel_crtc_state *crtc_state,
2742 const struct drm_connector_state *conn_state)
2743 {
2744 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2745 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2746 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2747
2748 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2749 intel_ddi_enable_clock(encoder, crtc_state);
2750
2751 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2752 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2753 dig_port->ddi_io_power_domain);
2754
2755 icl_program_mg_dp_mode(dig_port, crtc_state);
2756
2757 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2758
2759 dig_port->set_infoframes(encoder,
2760 crtc_state->has_infoframe,
2761 crtc_state, conn_state);
2762 }
2763
intel_ddi_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2764 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
2765 struct intel_encoder *encoder,
2766 const struct intel_crtc_state *crtc_state,
2767 const struct drm_connector_state *conn_state)
2768 {
2769 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2770 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2771 enum pipe pipe = crtc->pipe;
2772
2773 /*
2774 * When called from DP MST code:
2775 * - conn_state will be NULL
2776 * - encoder will be the main encoder (ie. mst->primary)
2777 * - the main connector associated with this port
2778 * won't be active or linked to a crtc
2779 * - crtc_state will be the state of the first stream to
2780 * be activated on this port, and it may not be the same
2781 * stream that will be deactivated last, but each stream
2782 * should have a state that is identical when it comes to
2783 * the DP link parameteres
2784 */
2785
2786 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
2787
2788 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2789
2790 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2791 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
2792 conn_state);
2793 } else {
2794 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2795
2796 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
2797 conn_state);
2798
2799 /* FIXME precompute everything properly */
2800 /* FIXME how do we turn infoframes off again? */
2801 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp))
2802 dig_port->set_infoframes(encoder,
2803 crtc_state->has_infoframe,
2804 crtc_state, conn_state);
2805 }
2806 }
2807
2808 static void
mtl_ddi_disable_d2d_link(struct intel_encoder * encoder)2809 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
2810 {
2811 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2812 enum port port = encoder->port;
2813
2814 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
2815 XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0);
2816
2817 if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
2818 XELPDP_PORT_BUF_D2D_LINK_STATE), 100))
2819 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for PORT_BUF_CTL %c\n",
2820 port_name(port));
2821 }
2822
mtl_disable_ddi_buf(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2823 static void mtl_disable_ddi_buf(struct intel_encoder *encoder,
2824 const struct intel_crtc_state *crtc_state)
2825 {
2826 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2827 enum port port = encoder->port;
2828 u32 val;
2829
2830 /* 3.b Clear DDI_CTL_DE Enable to 0. */
2831 val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
2832 if (val & DDI_BUF_CTL_ENABLE) {
2833 val &= ~DDI_BUF_CTL_ENABLE;
2834 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
2835
2836 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */
2837 mtl_wait_ddi_buf_idle(dev_priv, port);
2838 }
2839
2840 /* 3.d Disable D2D Link */
2841 mtl_ddi_disable_d2d_link(encoder);
2842
2843 /* 3.e Disable DP_TP_CTL */
2844 if (intel_crtc_has_dp_encoder(crtc_state)) {
2845 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
2846 DP_TP_CTL_ENABLE, 0);
2847 }
2848 }
2849
disable_ddi_buf(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2850 static void disable_ddi_buf(struct intel_encoder *encoder,
2851 const struct intel_crtc_state *crtc_state)
2852 {
2853 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2854 enum port port = encoder->port;
2855 bool wait = false;
2856 u32 val;
2857
2858 val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
2859 if (val & DDI_BUF_CTL_ENABLE) {
2860 val &= ~DDI_BUF_CTL_ENABLE;
2861 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
2862 wait = true;
2863 }
2864
2865 if (intel_crtc_has_dp_encoder(crtc_state))
2866 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
2867 DP_TP_CTL_ENABLE, 0);
2868
2869 /* Disable FEC in DP Sink */
2870 intel_ddi_disable_fec_state(encoder, crtc_state);
2871
2872 if (wait)
2873 intel_wait_ddi_buf_idle(dev_priv, port);
2874 }
2875
intel_disable_ddi_buf(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2876 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
2877 const struct intel_crtc_state *crtc_state)
2878 {
2879 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2880
2881 if (DISPLAY_VER(dev_priv) >= 14) {
2882 mtl_disable_ddi_buf(encoder, crtc_state);
2883
2884 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */
2885 intel_ddi_disable_fec_state(encoder, crtc_state);
2886 } else {
2887 disable_ddi_buf(encoder, crtc_state);
2888 }
2889 }
2890
intel_ddi_post_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)2891 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
2892 struct intel_encoder *encoder,
2893 const struct intel_crtc_state *old_crtc_state,
2894 const struct drm_connector_state *old_conn_state)
2895 {
2896 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2897 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2898 struct intel_dp *intel_dp = &dig_port->dp;
2899 intel_wakeref_t wakeref;
2900 bool is_mst = intel_crtc_has_type(old_crtc_state,
2901 INTEL_OUTPUT_DP_MST);
2902
2903 if (!is_mst)
2904 intel_dp_set_infoframes(encoder, false,
2905 old_crtc_state, old_conn_state);
2906
2907 /*
2908 * Power down sink before disabling the port, otherwise we end
2909 * up getting interrupts from the sink on detecting link loss.
2910 */
2911 intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
2912
2913 if (DISPLAY_VER(dev_priv) >= 12) {
2914 if (is_mst) {
2915 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
2916
2917 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
2918 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK,
2919 0);
2920 }
2921 } else {
2922 if (!is_mst)
2923 intel_ddi_disable_transcoder_clock(old_crtc_state);
2924 }
2925
2926 intel_disable_ddi_buf(encoder, old_crtc_state);
2927
2928 /*
2929 * From TGL spec: "If single stream or multi-stream master transcoder:
2930 * Configure Transcoder Clock select to direct no clock to the
2931 * transcoder"
2932 */
2933 if (DISPLAY_VER(dev_priv) >= 12)
2934 intel_ddi_disable_transcoder_clock(old_crtc_state);
2935
2936 intel_pps_vdd_on(intel_dp);
2937 intel_pps_off(intel_dp);
2938
2939 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref);
2940
2941 if (wakeref)
2942 intel_display_power_put(dev_priv,
2943 dig_port->ddi_io_power_domain,
2944 wakeref);
2945
2946 intel_ddi_disable_clock(encoder);
2947
2948 /* De-select Thunderbolt */
2949 if (DISPLAY_VER(dev_priv) >= 14)
2950 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port),
2951 XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
2952 }
2953
intel_ddi_post_disable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)2954 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
2955 struct intel_encoder *encoder,
2956 const struct intel_crtc_state *old_crtc_state,
2957 const struct drm_connector_state *old_conn_state)
2958 {
2959 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2960 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2961 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2962 intel_wakeref_t wakeref;
2963
2964 dig_port->set_infoframes(encoder, false,
2965 old_crtc_state, old_conn_state);
2966
2967 if (DISPLAY_VER(dev_priv) < 12)
2968 intel_ddi_disable_transcoder_clock(old_crtc_state);
2969
2970 intel_disable_ddi_buf(encoder, old_crtc_state);
2971
2972 if (DISPLAY_VER(dev_priv) >= 12)
2973 intel_ddi_disable_transcoder_clock(old_crtc_state);
2974
2975 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref);
2976 if (wakeref)
2977 intel_display_power_put(dev_priv,
2978 dig_port->ddi_io_power_domain,
2979 wakeref);
2980
2981 intel_ddi_disable_clock(encoder);
2982
2983 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2984 }
2985
intel_ddi_post_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)2986 static void intel_ddi_post_disable(struct intel_atomic_state *state,
2987 struct intel_encoder *encoder,
2988 const struct intel_crtc_state *old_crtc_state,
2989 const struct drm_connector_state *old_conn_state)
2990 {
2991 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2992 struct intel_crtc *slave_crtc;
2993
2994 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
2995 intel_crtc_vblank_off(old_crtc_state);
2996
2997 intel_disable_transcoder(old_crtc_state);
2998
2999 intel_ddi_disable_transcoder_func(old_crtc_state);
3000
3001 intel_dsc_disable(old_crtc_state);
3002
3003 if (DISPLAY_VER(dev_priv) >= 9)
3004 skl_scaler_disable(old_crtc_state);
3005 else
3006 ilk_pfit_disable(old_crtc_state);
3007 }
3008
3009 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
3010 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) {
3011 const struct intel_crtc_state *old_slave_crtc_state =
3012 intel_atomic_get_old_crtc_state(state, slave_crtc);
3013
3014 intel_crtc_vblank_off(old_slave_crtc_state);
3015
3016 intel_dsc_disable(old_slave_crtc_state);
3017 skl_scaler_disable(old_slave_crtc_state);
3018 }
3019
3020 /*
3021 * When called from DP MST code:
3022 * - old_conn_state will be NULL
3023 * - encoder will be the main encoder (ie. mst->primary)
3024 * - the main connector associated with this port
3025 * won't be active or linked to a crtc
3026 * - old_crtc_state will be the state of the last stream to
3027 * be deactivated on this port, and it may not be the same
3028 * stream that was activated last, but each stream
3029 * should have a state that is identical when it comes to
3030 * the DP link parameteres
3031 */
3032
3033 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3034 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
3035 old_conn_state);
3036 else
3037 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
3038 old_conn_state);
3039 }
3040
intel_ddi_post_pll_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3041 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state,
3042 struct intel_encoder *encoder,
3043 const struct intel_crtc_state *old_crtc_state,
3044 const struct drm_connector_state *old_conn_state)
3045 {
3046 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3047 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3048 enum phy phy = intel_port_to_phy(i915, encoder->port);
3049 bool is_tc_port = intel_phy_is_tc(i915, phy);
3050
3051 main_link_aux_power_domain_put(dig_port, old_crtc_state);
3052
3053 if (is_tc_port)
3054 intel_tc_port_put_link(dig_port);
3055 }
3056
trans_port_sync_stop_link_train(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3057 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
3058 struct intel_encoder *encoder,
3059 const struct intel_crtc_state *crtc_state)
3060 {
3061 const struct drm_connector_state *conn_state;
3062 struct drm_connector *conn;
3063 int i;
3064
3065 if (!crtc_state->sync_mode_slaves_mask)
3066 return;
3067
3068 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3069 struct intel_encoder *slave_encoder =
3070 to_intel_encoder(conn_state->best_encoder);
3071 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
3072 const struct intel_crtc_state *slave_crtc_state;
3073
3074 if (!slave_crtc)
3075 continue;
3076
3077 slave_crtc_state =
3078 intel_atomic_get_new_crtc_state(state, slave_crtc);
3079
3080 if (slave_crtc_state->master_transcoder !=
3081 crtc_state->cpu_transcoder)
3082 continue;
3083
3084 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
3085 slave_crtc_state);
3086 }
3087
3088 usleep_range(200, 400);
3089
3090 intel_dp_stop_link_train(enc_to_intel_dp(encoder),
3091 crtc_state);
3092 }
3093
intel_enable_ddi_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3094 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
3095 struct intel_encoder *encoder,
3096 const struct intel_crtc_state *crtc_state,
3097 const struct drm_connector_state *conn_state)
3098 {
3099 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3100 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3101 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3102 enum port port = encoder->port;
3103
3104 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9)
3105 intel_dp_stop_link_train(intel_dp, crtc_state);
3106
3107 drm_connector_update_privacy_screen(conn_state);
3108 intel_edp_backlight_on(crtc_state, conn_state);
3109
3110 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp))
3111 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3112
3113 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3114
3115 trans_port_sync_stop_link_train(state, encoder, crtc_state);
3116 }
3117
3118 static i915_reg_t
gen9_chicken_trans_reg_by_port(struct drm_i915_private * dev_priv,enum port port)3119 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3120 enum port port)
3121 {
3122 static const enum transcoder trans[] = {
3123 [PORT_A] = TRANSCODER_EDP,
3124 [PORT_B] = TRANSCODER_A,
3125 [PORT_C] = TRANSCODER_B,
3126 [PORT_D] = TRANSCODER_C,
3127 [PORT_E] = TRANSCODER_A,
3128 };
3129
3130 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9);
3131
3132 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
3133 port = PORT_A;
3134
3135 return CHICKEN_TRANS(trans[port]);
3136 }
3137
intel_enable_ddi_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3138 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
3139 struct intel_encoder *encoder,
3140 const struct intel_crtc_state *crtc_state,
3141 const struct drm_connector_state *conn_state)
3142 {
3143 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3144 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3145 struct drm_connector *connector = conn_state->connector;
3146 enum port port = encoder->port;
3147 enum phy phy = intel_port_to_phy(dev_priv, port);
3148 u32 buf_ctl;
3149
3150 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3151 crtc_state->hdmi_high_tmds_clock_ratio,
3152 crtc_state->hdmi_scrambling))
3153 drm_dbg_kms(&dev_priv->drm,
3154 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3155 connector->base.id, connector->name);
3156
3157 if (has_buf_trans_select(dev_priv))
3158 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
3159
3160 /* e. Enable D2D Link for C10/C20 Phy */
3161 if (DISPLAY_VER(dev_priv) >= 14)
3162 mtl_ddi_enable_d2d(encoder);
3163
3164 encoder->set_signal_levels(encoder, crtc_state);
3165
3166 /* Display WA #1143: skl,kbl,cfl */
3167 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
3168 /*
3169 * For some reason these chicken bits have been
3170 * stuffed into a transcoder register, event though
3171 * the bits affect a specific DDI port rather than
3172 * a specific transcoder.
3173 */
3174 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3175 u32 val;
3176
3177 val = intel_de_read(dev_priv, reg);
3178
3179 if (port == PORT_E)
3180 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3181 DDIE_TRAINING_OVERRIDE_VALUE;
3182 else
3183 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3184 DDI_TRAINING_OVERRIDE_VALUE;
3185
3186 intel_de_write(dev_priv, reg, val);
3187 intel_de_posting_read(dev_priv, reg);
3188
3189 udelay(1);
3190
3191 if (port == PORT_E)
3192 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3193 DDIE_TRAINING_OVERRIDE_VALUE);
3194 else
3195 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3196 DDI_TRAINING_OVERRIDE_VALUE);
3197
3198 intel_de_write(dev_priv, reg, val);
3199 }
3200
3201 intel_ddi_power_up_lanes(encoder, crtc_state);
3202
3203 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3204 * are ignored so nothing special needs to be done besides
3205 * enabling the port.
3206 *
3207 * On ADL_P the PHY link rate and lane count must be programmed but
3208 * these are both 0 for HDMI.
3209 *
3210 * But MTL onwards HDMI2.1 is supported and in TMDS mode this
3211 * is filled with lane count, already set in the crtc_state.
3212 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
3213 */
3214 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
3215 if (DISPLAY_VER(dev_priv) >= 14) {
3216 u8 lane_count = mtl_get_port_width(crtc_state->lane_count);
3217 u32 port_buf = 0;
3218
3219 port_buf |= XELPDP_PORT_WIDTH(lane_count);
3220
3221 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
3222 port_buf |= XELPDP_PORT_REVERSAL;
3223
3224 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
3225 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
3226
3227 buf_ctl |= DDI_PORT_WIDTH(lane_count);
3228 } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
3229 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
3230 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
3231 }
3232
3233 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
3234
3235 intel_wait_ddi_buf_active(dev_priv, port);
3236
3237 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3238 }
3239
intel_enable_ddi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3240 static void intel_enable_ddi(struct intel_atomic_state *state,
3241 struct intel_encoder *encoder,
3242 const struct intel_crtc_state *crtc_state,
3243 const struct drm_connector_state *conn_state)
3244 {
3245 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
3246
3247 if (!intel_crtc_is_bigjoiner_slave(crtc_state))
3248 intel_ddi_enable_transcoder_func(encoder, crtc_state);
3249
3250 /* Enable/Disable DP2.0 SDP split config before transcoder */
3251 intel_audio_sdp_split_update(encoder, crtc_state);
3252
3253 intel_enable_transcoder(crtc_state);
3254
3255 intel_crtc_vblank_on(crtc_state);
3256
3257 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3258 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
3259 else
3260 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
3261
3262 /* Enable hdcp if it's desired */
3263 if (conn_state->content_protection ==
3264 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3265 intel_hdcp_enable(state, encoder, crtc_state, conn_state);
3266 }
3267
intel_disable_ddi_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3268 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
3269 struct intel_encoder *encoder,
3270 const struct intel_crtc_state *old_crtc_state,
3271 const struct drm_connector_state *old_conn_state)
3272 {
3273 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3274
3275 intel_dp->link_trained = false;
3276
3277 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
3278
3279 intel_psr_disable(intel_dp, old_crtc_state);
3280 intel_edp_backlight_off(old_conn_state);
3281 /* Disable the decompression in DP Sink */
3282 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3283 false);
3284 /* Disable Ignore_MSA bit in DP Sink */
3285 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
3286 false);
3287 }
3288
intel_disable_ddi_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3289 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
3290 struct intel_encoder *encoder,
3291 const struct intel_crtc_state *old_crtc_state,
3292 const struct drm_connector_state *old_conn_state)
3293 {
3294 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3295 struct drm_connector *connector = old_conn_state->connector;
3296
3297 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
3298
3299 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3300 false, false))
3301 drm_dbg_kms(&i915->drm,
3302 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3303 connector->base.id, connector->name);
3304 }
3305
intel_disable_ddi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3306 static void intel_disable_ddi(struct intel_atomic_state *state,
3307 struct intel_encoder *encoder,
3308 const struct intel_crtc_state *old_crtc_state,
3309 const struct drm_connector_state *old_conn_state)
3310 {
3311 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder));
3312
3313 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3314
3315 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3316 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
3317 old_conn_state);
3318 else
3319 intel_disable_ddi_dp(state, encoder, old_crtc_state,
3320 old_conn_state);
3321 }
3322
intel_ddi_update_pipe_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3323 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
3324 struct intel_encoder *encoder,
3325 const struct intel_crtc_state *crtc_state,
3326 const struct drm_connector_state *conn_state)
3327 {
3328 intel_ddi_set_dp_msa(crtc_state, conn_state);
3329
3330 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3331
3332 intel_backlight_update(state, encoder, crtc_state, conn_state);
3333 drm_connector_update_privacy_screen(conn_state);
3334 }
3335
intel_ddi_update_pipe(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3336 void intel_ddi_update_pipe(struct intel_atomic_state *state,
3337 struct intel_encoder *encoder,
3338 const struct intel_crtc_state *crtc_state,
3339 const struct drm_connector_state *conn_state)
3340 {
3341
3342 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
3343 !intel_encoder_is_mst(encoder))
3344 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3345 conn_state);
3346
3347 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3348 }
3349
intel_ddi_update_active_dpll(struct intel_atomic_state * state,struct intel_encoder * encoder,struct intel_crtc * crtc)3350 void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
3351 struct intel_encoder *encoder,
3352 struct intel_crtc *crtc)
3353 {
3354 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3355 struct intel_crtc_state *crtc_state =
3356 intel_atomic_get_new_crtc_state(state, crtc);
3357 struct intel_crtc *slave_crtc;
3358 enum phy phy = intel_port_to_phy(i915, encoder->port);
3359
3360 /* FIXME: Add MTL pll_mgr */
3361 if (DISPLAY_VER(i915) >= 14 || !intel_phy_is_tc(i915, phy))
3362 return;
3363
3364 intel_update_active_dpll(state, crtc, encoder);
3365 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
3366 intel_crtc_bigjoiner_slave_pipes(crtc_state))
3367 intel_update_active_dpll(state, slave_crtc, encoder);
3368 }
3369
3370 static void
intel_ddi_pre_pll_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3371 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
3372 struct intel_encoder *encoder,
3373 const struct intel_crtc_state *crtc_state,
3374 const struct drm_connector_state *conn_state)
3375 {
3376 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3377 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3378 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3379 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3380
3381 if (is_tc_port) {
3382 struct intel_crtc *master_crtc =
3383 to_intel_crtc(crtc_state->uapi.crtc);
3384
3385 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3386 intel_ddi_update_active_dpll(state, encoder, master_crtc);
3387 }
3388
3389 main_link_aux_power_domain_get(dig_port, crtc_state);
3390
3391 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
3392 /*
3393 * Program the lane count for static/dynamic connections on
3394 * Type-C ports. Skip this step for TBT.
3395 */
3396 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3397 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3398 bxt_ddi_phy_set_lane_optim_mask(encoder,
3399 crtc_state->lane_lat_optim_mask);
3400 }
3401
adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder * encoder)3402 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
3403 {
3404 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3405 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
3406 int ln;
3407
3408 for (ln = 0; ln < 2; ln++)
3409 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0);
3410 }
3411
mtl_ddi_prepare_link_retrain(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3412 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3413 const struct intel_crtc_state *crtc_state)
3414 {
3415 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3416 struct intel_encoder *encoder = &dig_port->base;
3417 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3418 enum port port = encoder->port;
3419 u32 dp_tp_ctl;
3420
3421 /*
3422 * TODO: To train with only a different voltage swing entry is not
3423 * necessary disable and enable port
3424 */
3425 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3426 if (dp_tp_ctl & DP_TP_CTL_ENABLE)
3427 mtl_disable_ddi_buf(encoder, crtc_state);
3428
3429 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */
3430 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3431 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3432 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3433 } else {
3434 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3435 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3436 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3437 }
3438 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3439 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3440
3441 /* 6.f Enable D2D Link */
3442 mtl_ddi_enable_d2d(encoder);
3443
3444 /* 6.g Configure voltage swing and related IO settings */
3445 encoder->set_signal_levels(encoder, crtc_state);
3446
3447 /* 6.h Configure PORT_BUF_CTL1 */
3448 mtl_port_buf_ctl_program(encoder, crtc_state);
3449
3450 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
3451 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3452 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3453 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3454
3455 /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
3456 intel_wait_ddi_buf_active(dev_priv, port);
3457 }
3458
intel_ddi_prepare_link_retrain(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3459 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3460 const struct intel_crtc_state *crtc_state)
3461 {
3462 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3463 struct intel_encoder *encoder = &dig_port->base;
3464 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3465 enum port port = encoder->port;
3466 u32 dp_tp_ctl, ddi_buf_ctl;
3467 bool wait = false;
3468
3469 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3470
3471 if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
3472 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3473 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
3474 intel_de_write(dev_priv, DDI_BUF_CTL(port),
3475 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
3476 wait = true;
3477 }
3478
3479 dp_tp_ctl &= ~DP_TP_CTL_ENABLE;
3480 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3481 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3482
3483 if (wait)
3484 intel_wait_ddi_buf_idle(dev_priv, port);
3485 }
3486
3487 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3488 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3489 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3490 } else {
3491 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3492 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3493 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3494 }
3495 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3496 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3497
3498 if (IS_ALDERLAKE_P(dev_priv) &&
3499 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
3500 adlp_tbt_to_dp_alt_switch_wa(encoder);
3501
3502 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3503 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3504 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3505
3506 intel_wait_ddi_buf_active(dev_priv, port);
3507 }
3508
intel_ddi_set_link_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,u8 dp_train_pat)3509 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
3510 const struct intel_crtc_state *crtc_state,
3511 u8 dp_train_pat)
3512 {
3513 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3514 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3515 u32 temp;
3516
3517 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3518
3519 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3520 switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3521 case DP_TRAINING_PATTERN_DISABLE:
3522 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3523 break;
3524 case DP_TRAINING_PATTERN_1:
3525 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3526 break;
3527 case DP_TRAINING_PATTERN_2:
3528 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3529 break;
3530 case DP_TRAINING_PATTERN_3:
3531 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3532 break;
3533 case DP_TRAINING_PATTERN_4:
3534 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3535 break;
3536 }
3537
3538 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
3539 }
3540
intel_ddi_set_idle_link_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3541 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
3542 const struct intel_crtc_state *crtc_state)
3543 {
3544 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3545 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3546 enum port port = encoder->port;
3547
3548 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
3549 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE);
3550
3551 /*
3552 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
3553 * reason we need to set idle transmission mode is to work around a HW
3554 * issue where we enable the pipe while not in idle link-training mode.
3555 * In this case there is requirement to wait for a minimum number of
3556 * idle patterns to be sent.
3557 */
3558 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)
3559 return;
3560
3561 if (intel_de_wait_for_set(dev_priv,
3562 dp_tp_status_reg(encoder, crtc_state),
3563 DP_TP_STATUS_IDLE_DONE, 1))
3564 drm_err(&dev_priv->drm,
3565 "Timed out waiting for DP idle patterns\n");
3566 }
3567
intel_ddi_is_audio_enabled(struct drm_i915_private * dev_priv,enum transcoder cpu_transcoder)3568 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3569 enum transcoder cpu_transcoder)
3570 {
3571 if (cpu_transcoder == TRANSCODER_EDP)
3572 return false;
3573
3574 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO))
3575 return false;
3576
3577 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
3578 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3579 }
3580
intel_ddi_compute_min_voltage_level(struct drm_i915_private * dev_priv,struct intel_crtc_state * crtc_state)3581 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3582 struct intel_crtc_state *crtc_state)
3583 {
3584 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
3585 crtc_state->min_voltage_level = 2;
3586 else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
3587 crtc_state->port_clock > 594000)
3588 crtc_state->min_voltage_level = 3;
3589 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3590 crtc_state->min_voltage_level = 1;
3591 }
3592
bdw_transcoder_master_readout(struct drm_i915_private * dev_priv,enum transcoder cpu_transcoder)3593 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
3594 enum transcoder cpu_transcoder)
3595 {
3596 u32 master_select;
3597
3598 if (DISPLAY_VER(dev_priv) >= 11) {
3599 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
3600
3601 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
3602 return INVALID_TRANSCODER;
3603
3604 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
3605 } else {
3606 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3607
3608 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
3609 return INVALID_TRANSCODER;
3610
3611 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
3612 }
3613
3614 if (master_select == 0)
3615 return TRANSCODER_EDP;
3616 else
3617 return master_select - 1;
3618 }
3619
bdw_get_trans_port_sync_config(struct intel_crtc_state * crtc_state)3620 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
3621 {
3622 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3623 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3624 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3625 enum transcoder cpu_transcoder;
3626
3627 crtc_state->master_transcoder =
3628 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
3629
3630 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
3631 enum intel_display_power_domain power_domain;
3632 intel_wakeref_t trans_wakeref;
3633
3634 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3635 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
3636 power_domain);
3637
3638 if (!trans_wakeref)
3639 continue;
3640
3641 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
3642 crtc_state->cpu_transcoder)
3643 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
3644
3645 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
3646 }
3647
3648 drm_WARN_ON(&dev_priv->drm,
3649 crtc_state->master_transcoder != INVALID_TRANSCODER &&
3650 crtc_state->sync_mode_slaves_mask);
3651 }
3652
intel_ddi_read_func_ctl(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)3653 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
3654 struct intel_crtc_state *pipe_config)
3655 {
3656 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3657 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3658 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3659 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3660 u32 temp, flags = 0;
3661
3662 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3663 if (temp & TRANS_DDI_PHSYNC)
3664 flags |= DRM_MODE_FLAG_PHSYNC;
3665 else
3666 flags |= DRM_MODE_FLAG_NHSYNC;
3667 if (temp & TRANS_DDI_PVSYNC)
3668 flags |= DRM_MODE_FLAG_PVSYNC;
3669 else
3670 flags |= DRM_MODE_FLAG_NVSYNC;
3671
3672 pipe_config->hw.adjusted_mode.flags |= flags;
3673
3674 switch (temp & TRANS_DDI_BPC_MASK) {
3675 case TRANS_DDI_BPC_6:
3676 pipe_config->pipe_bpp = 18;
3677 break;
3678 case TRANS_DDI_BPC_8:
3679 pipe_config->pipe_bpp = 24;
3680 break;
3681 case TRANS_DDI_BPC_10:
3682 pipe_config->pipe_bpp = 30;
3683 break;
3684 case TRANS_DDI_BPC_12:
3685 pipe_config->pipe_bpp = 36;
3686 break;
3687 default:
3688 break;
3689 }
3690
3691 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3692 case TRANS_DDI_MODE_SELECT_HDMI:
3693 pipe_config->has_hdmi_sink = true;
3694
3695 pipe_config->infoframes.enable |=
3696 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3697
3698 if (pipe_config->infoframes.enable)
3699 pipe_config->has_infoframe = true;
3700
3701 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3702 pipe_config->hdmi_scrambling = true;
3703 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3704 pipe_config->hdmi_high_tmds_clock_ratio = true;
3705 fallthrough;
3706 case TRANS_DDI_MODE_SELECT_DVI:
3707 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3708 if (DISPLAY_VER(dev_priv) >= 14)
3709 pipe_config->lane_count =
3710 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3711 else
3712 pipe_config->lane_count = 4;
3713 break;
3714 case TRANS_DDI_MODE_SELECT_DP_SST:
3715 if (encoder->type == INTEL_OUTPUT_EDP)
3716 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3717 else
3718 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3719 pipe_config->lane_count =
3720 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3721
3722 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
3723 &pipe_config->dp_m_n);
3724 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder,
3725 &pipe_config->dp_m2_n2);
3726
3727 if (DISPLAY_VER(dev_priv) >= 11) {
3728 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
3729
3730 pipe_config->fec_enable =
3731 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
3732
3733 drm_dbg_kms(&dev_priv->drm,
3734 "[ENCODER:%d:%s] Fec status: %u\n",
3735 encoder->base.base.id, encoder->base.name,
3736 pipe_config->fec_enable);
3737 }
3738
3739 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp))
3740 pipe_config->infoframes.enable |=
3741 intel_lspcon_infoframes_enabled(encoder, pipe_config);
3742 else
3743 pipe_config->infoframes.enable |=
3744 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3745 break;
3746 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
3747 if (!HAS_DP20(dev_priv)) {
3748 /* FDI */
3749 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3750 break;
3751 }
3752 fallthrough; /* 128b/132b */
3753 case TRANS_DDI_MODE_SELECT_DP_MST:
3754 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3755 pipe_config->lane_count =
3756 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3757
3758 if (DISPLAY_VER(dev_priv) >= 12)
3759 pipe_config->mst_master_transcoder =
3760 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
3761
3762 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
3763 &pipe_config->dp_m_n);
3764
3765 pipe_config->infoframes.enable |=
3766 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3767 break;
3768 default:
3769 break;
3770 }
3771 }
3772
intel_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)3773 static void intel_ddi_get_config(struct intel_encoder *encoder,
3774 struct intel_crtc_state *pipe_config)
3775 {
3776 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3777 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3778
3779 /* XXX: DSI transcoder paranoia */
3780 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
3781 return;
3782
3783 intel_ddi_read_func_ctl(encoder, pipe_config);
3784
3785 intel_ddi_mso_get_config(encoder, pipe_config);
3786
3787 pipe_config->has_audio =
3788 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3789
3790 if (encoder->type == INTEL_OUTPUT_EDP)
3791 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
3792
3793 ddi_dotclock_get(pipe_config);
3794
3795 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3796 pipe_config->lane_lat_optim_mask =
3797 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3798
3799 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3800
3801 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3802
3803 intel_read_infoframe(encoder, pipe_config,
3804 HDMI_INFOFRAME_TYPE_AVI,
3805 &pipe_config->infoframes.avi);
3806 intel_read_infoframe(encoder, pipe_config,
3807 HDMI_INFOFRAME_TYPE_SPD,
3808 &pipe_config->infoframes.spd);
3809 intel_read_infoframe(encoder, pipe_config,
3810 HDMI_INFOFRAME_TYPE_VENDOR,
3811 &pipe_config->infoframes.hdmi);
3812 intel_read_infoframe(encoder, pipe_config,
3813 HDMI_INFOFRAME_TYPE_DRM,
3814 &pipe_config->infoframes.drm);
3815
3816 if (DISPLAY_VER(dev_priv) >= 8)
3817 bdw_get_trans_port_sync_config(pipe_config);
3818
3819 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
3820 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
3821
3822 intel_psr_get_config(encoder, pipe_config);
3823
3824 intel_audio_codec_get_config(encoder, pipe_config);
3825 }
3826
intel_ddi_get_clock(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct intel_shared_dpll * pll)3827 void intel_ddi_get_clock(struct intel_encoder *encoder,
3828 struct intel_crtc_state *crtc_state,
3829 struct intel_shared_dpll *pll)
3830 {
3831 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3832 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3833 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3834 bool pll_active;
3835
3836 if (drm_WARN_ON(&i915->drm, !pll))
3837 return;
3838
3839 port_dpll->pll = pll;
3840 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3841 drm_WARN_ON(&i915->drm, !pll_active);
3842
3843 icl_set_active_port_dpll(crtc_state, port_dpll_id);
3844
3845 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3846 &crtc_state->dpll_hw_state);
3847 }
3848
mtl_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3849 static void mtl_ddi_get_config(struct intel_encoder *encoder,
3850 struct intel_crtc_state *crtc_state)
3851 {
3852 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3853 enum phy phy = intel_port_to_phy(i915, encoder->port);
3854 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3855
3856 if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
3857 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
3858 } else if (intel_is_c10phy(i915, phy)) {
3859 intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10);
3860 intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
3861 crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
3862 } else {
3863 intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20);
3864 intel_c20pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c20);
3865 crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20);
3866 }
3867
3868 intel_ddi_get_config(encoder, crtc_state);
3869 }
3870
dg2_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3871 static void dg2_ddi_get_config(struct intel_encoder *encoder,
3872 struct intel_crtc_state *crtc_state)
3873 {
3874 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state);
3875 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state);
3876
3877 intel_ddi_get_config(encoder, crtc_state);
3878 }
3879
adls_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3880 static void adls_ddi_get_config(struct intel_encoder *encoder,
3881 struct intel_crtc_state *crtc_state)
3882 {
3883 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));
3884 intel_ddi_get_config(encoder, crtc_state);
3885 }
3886
rkl_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3887 static void rkl_ddi_get_config(struct intel_encoder *encoder,
3888 struct intel_crtc_state *crtc_state)
3889 {
3890 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));
3891 intel_ddi_get_config(encoder, crtc_state);
3892 }
3893
dg1_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3894 static void dg1_ddi_get_config(struct intel_encoder *encoder,
3895 struct intel_crtc_state *crtc_state)
3896 {
3897 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));
3898 intel_ddi_get_config(encoder, crtc_state);
3899 }
3900
icl_ddi_combo_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3901 static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
3902 struct intel_crtc_state *crtc_state)
3903 {
3904 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));
3905 intel_ddi_get_config(encoder, crtc_state);
3906 }
3907
icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll * pll)3908 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll)
3909 {
3910 return pll->info->id == DPLL_ID_ICL_TBTPLL;
3911 }
3912
3913 static enum icl_port_dpll_id
icl_ddi_tc_port_pll_type(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3914 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
3915 const struct intel_crtc_state *crtc_state)
3916 {
3917 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3918 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3919
3920 if (drm_WARN_ON(&i915->drm, !pll))
3921 return ICL_PORT_DPLL_DEFAULT;
3922
3923 if (icl_ddi_tc_pll_is_tbt(pll))
3924 return ICL_PORT_DPLL_DEFAULT;
3925 else
3926 return ICL_PORT_DPLL_MG_PHY;
3927 }
3928
3929 enum icl_port_dpll_id
intel_ddi_port_pll_type(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3930 intel_ddi_port_pll_type(struct intel_encoder *encoder,
3931 const struct intel_crtc_state *crtc_state)
3932 {
3933 if (!encoder->port_pll_type)
3934 return ICL_PORT_DPLL_DEFAULT;
3935
3936 return encoder->port_pll_type(encoder, crtc_state);
3937 }
3938
icl_ddi_tc_get_clock(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct intel_shared_dpll * pll)3939 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
3940 struct intel_crtc_state *crtc_state,
3941 struct intel_shared_dpll *pll)
3942 {
3943 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3944 enum icl_port_dpll_id port_dpll_id;
3945 struct icl_port_dpll *port_dpll;
3946 bool pll_active;
3947
3948 if (drm_WARN_ON(&i915->drm, !pll))
3949 return;
3950
3951 if (icl_ddi_tc_pll_is_tbt(pll))
3952 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3953 else
3954 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
3955
3956 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3957
3958 port_dpll->pll = pll;
3959 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3960 drm_WARN_ON(&i915->drm, !pll_active);
3961
3962 icl_set_active_port_dpll(crtc_state, port_dpll_id);
3963
3964 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
3965 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
3966 else
3967 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3968 &crtc_state->dpll_hw_state);
3969 }
3970
icl_ddi_tc_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3971 static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
3972 struct intel_crtc_state *crtc_state)
3973 {
3974 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder));
3975 intel_ddi_get_config(encoder, crtc_state);
3976 }
3977
bxt_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3978 static void bxt_ddi_get_config(struct intel_encoder *encoder,
3979 struct intel_crtc_state *crtc_state)
3980 {
3981 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));
3982 intel_ddi_get_config(encoder, crtc_state);
3983 }
3984
skl_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3985 static void skl_ddi_get_config(struct intel_encoder *encoder,
3986 struct intel_crtc_state *crtc_state)
3987 {
3988 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));
3989 intel_ddi_get_config(encoder, crtc_state);
3990 }
3991
hsw_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3992 void hsw_ddi_get_config(struct intel_encoder *encoder,
3993 struct intel_crtc_state *crtc_state)
3994 {
3995 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));
3996 intel_ddi_get_config(encoder, crtc_state);
3997 }
3998
intel_ddi_sync_state(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3999 static void intel_ddi_sync_state(struct intel_encoder *encoder,
4000 const struct intel_crtc_state *crtc_state)
4001 {
4002 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4003 enum phy phy = intel_port_to_phy(i915, encoder->port);
4004
4005 if (intel_phy_is_tc(i915, phy))
4006 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder),
4007 crtc_state);
4008
4009 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
4010 intel_dp_sync_state(encoder, crtc_state);
4011 }
4012
intel_ddi_initial_fastset_check(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)4013 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
4014 struct intel_crtc_state *crtc_state)
4015 {
4016 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4017 enum phy phy = intel_port_to_phy(i915, encoder->port);
4018 bool fastset = true;
4019
4020 if (intel_phy_is_tc(i915, phy)) {
4021 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n",
4022 encoder->base.base.id, encoder->base.name);
4023 crtc_state->uapi.mode_changed = true;
4024 fastset = false;
4025 }
4026
4027 if (intel_crtc_has_dp_encoder(crtc_state) &&
4028 !intel_dp_initial_fastset_check(encoder, crtc_state))
4029 fastset = false;
4030
4031 return fastset;
4032 }
4033
4034 static enum intel_output_type
intel_ddi_compute_output_type(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)4035 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4036 struct intel_crtc_state *crtc_state,
4037 struct drm_connector_state *conn_state)
4038 {
4039 switch (conn_state->connector->connector_type) {
4040 case DRM_MODE_CONNECTOR_HDMIA:
4041 return INTEL_OUTPUT_HDMI;
4042 case DRM_MODE_CONNECTOR_eDP:
4043 return INTEL_OUTPUT_EDP;
4044 case DRM_MODE_CONNECTOR_DisplayPort:
4045 return INTEL_OUTPUT_DP;
4046 default:
4047 MISSING_CASE(conn_state->connector->connector_type);
4048 return INTEL_OUTPUT_UNUSED;
4049 }
4050 }
4051
intel_ddi_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)4052 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4053 struct intel_crtc_state *pipe_config,
4054 struct drm_connector_state *conn_state)
4055 {
4056 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4057 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4058 enum port port = encoder->port;
4059 int ret;
4060
4061 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
4062 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4063
4064 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4065 pipe_config->has_hdmi_sink =
4066 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state);
4067
4068 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4069 } else {
4070 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4071 }
4072
4073 if (ret)
4074 return ret;
4075
4076 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4077 pipe_config->cpu_transcoder == TRANSCODER_EDP)
4078 pipe_config->pch_pfit.force_thru =
4079 pipe_config->pch_pfit.enabled ||
4080 pipe_config->crc_enabled;
4081
4082 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4083 pipe_config->lane_lat_optim_mask =
4084 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4085
4086 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4087
4088 return 0;
4089 }
4090
mode_equal(const struct drm_display_mode * mode1,const struct drm_display_mode * mode2)4091 static bool mode_equal(const struct drm_display_mode *mode1,
4092 const struct drm_display_mode *mode2)
4093 {
4094 return drm_mode_match(mode1, mode2,
4095 DRM_MODE_MATCH_TIMINGS |
4096 DRM_MODE_MATCH_FLAGS |
4097 DRM_MODE_MATCH_3D_FLAGS) &&
4098 mode1->clock == mode2->clock; /* we want an exact match */
4099 }
4100
m_n_equal(const struct intel_link_m_n * m_n_1,const struct intel_link_m_n * m_n_2)4101 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
4102 const struct intel_link_m_n *m_n_2)
4103 {
4104 return m_n_1->tu == m_n_2->tu &&
4105 m_n_1->data_m == m_n_2->data_m &&
4106 m_n_1->data_n == m_n_2->data_n &&
4107 m_n_1->link_m == m_n_2->link_m &&
4108 m_n_1->link_n == m_n_2->link_n;
4109 }
4110
crtcs_port_sync_compatible(const struct intel_crtc_state * crtc_state1,const struct intel_crtc_state * crtc_state2)4111 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
4112 const struct intel_crtc_state *crtc_state2)
4113 {
4114 return crtc_state1->hw.active && crtc_state2->hw.active &&
4115 crtc_state1->output_types == crtc_state2->output_types &&
4116 crtc_state1->output_format == crtc_state2->output_format &&
4117 crtc_state1->lane_count == crtc_state2->lane_count &&
4118 crtc_state1->port_clock == crtc_state2->port_clock &&
4119 mode_equal(&crtc_state1->hw.adjusted_mode,
4120 &crtc_state2->hw.adjusted_mode) &&
4121 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
4122 }
4123
4124 static u8
intel_ddi_port_sync_transcoders(const struct intel_crtc_state * ref_crtc_state,int tile_group_id)4125 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
4126 int tile_group_id)
4127 {
4128 struct drm_connector *connector;
4129 const struct drm_connector_state *conn_state;
4130 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
4131 struct intel_atomic_state *state =
4132 to_intel_atomic_state(ref_crtc_state->uapi.state);
4133 u8 transcoders = 0;
4134 int i;
4135
4136 /*
4137 * We don't enable port sync on BDW due to missing w/as and
4138 * due to not having adjusted the modeset sequence appropriately.
4139 */
4140 if (DISPLAY_VER(dev_priv) < 9)
4141 return 0;
4142
4143 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
4144 return 0;
4145
4146 for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
4147 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
4148 const struct intel_crtc_state *crtc_state;
4149
4150 if (!crtc)
4151 continue;
4152
4153 if (!connector->has_tile ||
4154 connector->tile_group->id !=
4155 tile_group_id)
4156 continue;
4157 crtc_state = intel_atomic_get_new_crtc_state(state,
4158 crtc);
4159 if (!crtcs_port_sync_compatible(ref_crtc_state,
4160 crtc_state))
4161 continue;
4162 transcoders |= BIT(crtc_state->cpu_transcoder);
4163 }
4164
4165 return transcoders;
4166 }
4167
intel_ddi_compute_config_late(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)4168 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
4169 struct intel_crtc_state *crtc_state,
4170 struct drm_connector_state *conn_state)
4171 {
4172 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4173 struct drm_connector *connector = conn_state->connector;
4174 u8 port_sync_transcoders = 0;
4175
4176 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
4177 encoder->base.base.id, encoder->base.name,
4178 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
4179
4180 if (connector->has_tile)
4181 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
4182 connector->tile_group->id);
4183
4184 /*
4185 * EDP Transcoders cannot be ensalved
4186 * make them a master always when present
4187 */
4188 if (port_sync_transcoders & BIT(TRANSCODER_EDP))
4189 crtc_state->master_transcoder = TRANSCODER_EDP;
4190 else
4191 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
4192
4193 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4194 crtc_state->master_transcoder = INVALID_TRANSCODER;
4195 crtc_state->sync_mode_slaves_mask =
4196 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4197 }
4198
4199 return 0;
4200 }
4201
intel_ddi_encoder_destroy(struct drm_encoder * encoder)4202 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4203 {
4204 struct drm_i915_private *i915 = to_i915(encoder->dev);
4205 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4206 enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
4207
4208 intel_dp_encoder_flush_work(encoder);
4209 if (intel_phy_is_tc(i915, phy))
4210 intel_tc_port_cleanup(dig_port);
4211 intel_display_power_flush_work(i915);
4212
4213 drm_encoder_cleanup(encoder);
4214 kfree(dig_port->hdcp_port_data.streams);
4215 kfree(dig_port);
4216 }
4217
intel_ddi_encoder_reset(struct drm_encoder * encoder)4218 static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
4219 {
4220 struct drm_i915_private *i915 = to_i915(encoder->dev);
4221 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
4222 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4223 enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
4224
4225 intel_dp->reset_link_params = true;
4226
4227 intel_pps_encoder_reset(intel_dp);
4228
4229 if (intel_phy_is_tc(i915, phy))
4230 intel_tc_port_init_mode(dig_port);
4231 }
4232
intel_ddi_encoder_late_register(struct drm_encoder * _encoder)4233 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder)
4234 {
4235 struct intel_encoder *encoder = to_intel_encoder(_encoder);
4236
4237 intel_tc_port_link_reset(enc_to_dig_port(encoder));
4238
4239 return 0;
4240 }
4241
4242 static const struct drm_encoder_funcs intel_ddi_funcs = {
4243 .reset = intel_ddi_encoder_reset,
4244 .destroy = intel_ddi_encoder_destroy,
4245 .late_register = intel_ddi_encoder_late_register,
4246 };
4247
4248 static struct intel_connector *
intel_ddi_init_dp_connector(struct intel_digital_port * dig_port)4249 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4250 {
4251 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
4252 struct intel_connector *connector;
4253 enum port port = dig_port->base.port;
4254
4255 connector = intel_connector_alloc();
4256 if (!connector)
4257 return NULL;
4258
4259 dig_port->dp.output_reg = DDI_BUF_CTL(port);
4260 if (DISPLAY_VER(i915) >= 14)
4261 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain;
4262 else
4263 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
4264 dig_port->dp.set_link_train = intel_ddi_set_link_train;
4265 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
4266
4267 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
4268 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
4269
4270 if (!intel_dp_init_connector(dig_port, connector)) {
4271 kfree(connector);
4272 return NULL;
4273 }
4274
4275 if (dig_port->base.type == INTEL_OUTPUT_EDP) {
4276 struct drm_device *dev = dig_port->base.base.dev;
4277 struct drm_privacy_screen *privacy_screen;
4278
4279 privacy_screen = drm_privacy_screen_get(dev->dev, NULL);
4280 if (!IS_ERR(privacy_screen)) {
4281 drm_connector_attach_privacy_screen_provider(&connector->base,
4282 privacy_screen);
4283 } else if (PTR_ERR(privacy_screen) != -ENODEV) {
4284 drm_warn(dev, "Error getting privacy-screen\n");
4285 }
4286 }
4287
4288 return connector;
4289 }
4290
modeset_pipe(struct drm_crtc * crtc,struct drm_modeset_acquire_ctx * ctx)4291 static int modeset_pipe(struct drm_crtc *crtc,
4292 struct drm_modeset_acquire_ctx *ctx)
4293 {
4294 struct drm_atomic_state *state;
4295 struct drm_crtc_state *crtc_state;
4296 int ret;
4297
4298 state = drm_atomic_state_alloc(crtc->dev);
4299 if (!state)
4300 return -ENOMEM;
4301
4302 state->acquire_ctx = ctx;
4303 to_intel_atomic_state(state)->internal = true;
4304
4305 crtc_state = drm_atomic_get_crtc_state(state, crtc);
4306 if (IS_ERR(crtc_state)) {
4307 ret = PTR_ERR(crtc_state);
4308 goto out;
4309 }
4310
4311 crtc_state->connectors_changed = true;
4312
4313 ret = drm_atomic_commit(state);
4314 out:
4315 drm_atomic_state_put(state);
4316
4317 return ret;
4318 }
4319
intel_hdmi_reset_link(struct intel_encoder * encoder,struct drm_modeset_acquire_ctx * ctx)4320 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4321 struct drm_modeset_acquire_ctx *ctx)
4322 {
4323 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4324 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4325 struct intel_connector *connector = hdmi->attached_connector;
4326 struct i2c_adapter *adapter =
4327 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4328 struct drm_connector_state *conn_state;
4329 struct intel_crtc_state *crtc_state;
4330 struct intel_crtc *crtc;
4331 u8 config;
4332 int ret;
4333
4334 if (!connector || connector->base.status != connector_status_connected)
4335 return 0;
4336
4337 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4338 ctx);
4339 if (ret)
4340 return ret;
4341
4342 conn_state = connector->base.state;
4343
4344 crtc = to_intel_crtc(conn_state->crtc);
4345 if (!crtc)
4346 return 0;
4347
4348 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4349 if (ret)
4350 return ret;
4351
4352 crtc_state = to_intel_crtc_state(crtc->base.state);
4353
4354 drm_WARN_ON(&dev_priv->drm,
4355 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4356
4357 if (!crtc_state->hw.active)
4358 return 0;
4359
4360 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4361 !crtc_state->hdmi_scrambling)
4362 return 0;
4363
4364 if (conn_state->commit &&
4365 !try_wait_for_completion(&conn_state->commit->hw_done))
4366 return 0;
4367
4368 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4369 if (ret < 0) {
4370 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",
4371 connector->base.base.id, connector->base.name, ret);
4372 return 0;
4373 }
4374
4375 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4376 crtc_state->hdmi_high_tmds_clock_ratio &&
4377 !!(config & SCDC_SCRAMBLING_ENABLE) ==
4378 crtc_state->hdmi_scrambling)
4379 return 0;
4380
4381 /*
4382 * HDMI 2.0 says that one should not send scrambled data
4383 * prior to configuring the sink scrambling, and that
4384 * TMDS clock/data transmission should be suspended when
4385 * changing the TMDS clock rate in the sink. So let's
4386 * just do a full modeset here, even though some sinks
4387 * would be perfectly happy if were to just reconfigure
4388 * the SCDC settings on the fly.
4389 */
4390 return modeset_pipe(&crtc->base, ctx);
4391 }
4392
4393 static enum intel_hotplug_state
intel_ddi_hotplug(struct intel_encoder * encoder,struct intel_connector * connector)4394 intel_ddi_hotplug(struct intel_encoder *encoder,
4395 struct intel_connector *connector)
4396 {
4397 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4398 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4399 struct intel_dp *intel_dp = &dig_port->dp;
4400 enum phy phy = intel_port_to_phy(i915, encoder->port);
4401 bool is_tc = intel_phy_is_tc(i915, phy);
4402 struct drm_modeset_acquire_ctx ctx;
4403 enum intel_hotplug_state state;
4404 int ret;
4405
4406 if (intel_dp->compliance.test_active &&
4407 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
4408 intel_dp_phy_test(encoder);
4409 /* just do the PHY test and nothing else */
4410 return INTEL_HOTPLUG_UNCHANGED;
4411 }
4412
4413 state = intel_encoder_hotplug(encoder, connector);
4414
4415 if (!intel_tc_port_link_reset(dig_port)) {
4416 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) {
4417 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4418 ret = intel_hdmi_reset_link(encoder, &ctx);
4419 else
4420 ret = intel_dp_retrain_link(encoder, &ctx);
4421 }
4422
4423 drm_WARN_ON(encoder->base.dev, ret);
4424 }
4425
4426 /*
4427 * Unpowered type-c dongles can take some time to boot and be
4428 * responsible, so here giving some time to those dongles to power up
4429 * and then retrying the probe.
4430 *
4431 * On many platforms the HDMI live state signal is known to be
4432 * unreliable, so we can't use it to detect if a sink is connected or
4433 * not. Instead we detect if it's connected based on whether we can
4434 * read the EDID or not. That in turn has a problem during disconnect,
4435 * since the HPD interrupt may be raised before the DDC lines get
4436 * disconnected (due to how the required length of DDC vs. HPD
4437 * connector pins are specified) and so we'll still be able to get a
4438 * valid EDID. To solve this schedule another detection cycle if this
4439 * time around we didn't detect any change in the sink's connection
4440 * status.
4441 *
4442 * Type-c connectors which get their HPD signal deasserted then
4443 * reasserted, without unplugging/replugging the sink from the
4444 * connector, introduce a delay until the AUX channel communication
4445 * becomes functional. Retry the detection for 5 seconds on type-c
4446 * connectors to account for this delay.
4447 */
4448 if (state == INTEL_HOTPLUG_UNCHANGED &&
4449 connector->hotplug_retries < (is_tc ? 5 : 1) &&
4450 !dig_port->dp.is_mst)
4451 state = INTEL_HOTPLUG_RETRY;
4452
4453 return state;
4454 }
4455
lpt_digital_port_connected(struct intel_encoder * encoder)4456 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4457 {
4458 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4459 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];
4460
4461 return intel_de_read(dev_priv, SDEISR) & bit;
4462 }
4463
hsw_digital_port_connected(struct intel_encoder * encoder)4464 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4465 {
4466 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4467 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
4468
4469 return intel_de_read(dev_priv, DEISR) & bit;
4470 }
4471
bdw_digital_port_connected(struct intel_encoder * encoder)4472 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4473 {
4474 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4475 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
4476
4477 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
4478 }
4479
4480 static struct intel_connector *
intel_ddi_init_hdmi_connector(struct intel_digital_port * dig_port)4481 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4482 {
4483 struct intel_connector *connector;
4484 enum port port = dig_port->base.port;
4485
4486 connector = intel_connector_alloc();
4487 if (!connector)
4488 return NULL;
4489
4490 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4491 intel_hdmi_init_connector(dig_port, connector);
4492
4493 return connector;
4494 }
4495
intel_ddi_a_force_4_lanes(struct intel_digital_port * dig_port)4496 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4497 {
4498 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4499
4500 if (dig_port->base.port != PORT_A)
4501 return false;
4502
4503 if (dig_port->saved_port_bits & DDI_A_4_LANES)
4504 return false;
4505
4506 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4507 * supported configuration
4508 */
4509 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4510 return true;
4511
4512 return false;
4513 }
4514
4515 static int
intel_ddi_max_lanes(struct intel_digital_port * dig_port)4516 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4517 {
4518 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4519 enum port port = dig_port->base.port;
4520 int max_lanes = 4;
4521
4522 if (DISPLAY_VER(dev_priv) >= 11)
4523 return max_lanes;
4524
4525 if (port == PORT_A || port == PORT_E) {
4526 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4527 max_lanes = port == PORT_A ? 4 : 0;
4528 else
4529 /* Both A and E share 2 lanes */
4530 max_lanes = 2;
4531 }
4532
4533 /*
4534 * Some BIOS might fail to set this bit on port A if eDP
4535 * wasn't lit up at boot. Force this bit set when needed
4536 * so we use the proper lane count for our calculations.
4537 */
4538 if (intel_ddi_a_force_4_lanes(dig_port)) {
4539 drm_dbg_kms(&dev_priv->drm,
4540 "Forcing DDI_A_4_LANES for port A\n");
4541 dig_port->saved_port_bits |= DDI_A_4_LANES;
4542 max_lanes = 4;
4543 }
4544
4545 return max_lanes;
4546 }
4547
xelpd_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4548 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
4549 enum port port)
4550 {
4551 if (port >= PORT_D_XELPD)
4552 return HPD_PORT_D + port - PORT_D_XELPD;
4553 else if (port >= PORT_TC1)
4554 return HPD_PORT_TC1 + port - PORT_TC1;
4555 else
4556 return HPD_PORT_A + port - PORT_A;
4557 }
4558
dg1_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4559 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
4560 enum port port)
4561 {
4562 if (port >= PORT_TC1)
4563 return HPD_PORT_C + port - PORT_TC1;
4564 else
4565 return HPD_PORT_A + port - PORT_A;
4566 }
4567
tgl_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4568 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
4569 enum port port)
4570 {
4571 if (port >= PORT_TC1)
4572 return HPD_PORT_TC1 + port - PORT_TC1;
4573 else
4574 return HPD_PORT_A + port - PORT_A;
4575 }
4576
rkl_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4577 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
4578 enum port port)
4579 {
4580 if (HAS_PCH_TGP(dev_priv))
4581 return tgl_hpd_pin(dev_priv, port);
4582
4583 if (port >= PORT_TC1)
4584 return HPD_PORT_C + port - PORT_TC1;
4585 else
4586 return HPD_PORT_A + port - PORT_A;
4587 }
4588
icl_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4589 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv,
4590 enum port port)
4591 {
4592 if (port >= PORT_C)
4593 return HPD_PORT_TC1 + port - PORT_C;
4594 else
4595 return HPD_PORT_A + port - PORT_A;
4596 }
4597
ehl_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4598 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
4599 enum port port)
4600 {
4601 if (port == PORT_D)
4602 return HPD_PORT_A;
4603
4604 if (HAS_PCH_TGP(dev_priv))
4605 return icl_hpd_pin(dev_priv, port);
4606
4607 return HPD_PORT_A + port - PORT_A;
4608 }
4609
skl_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4610 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
4611 {
4612 if (HAS_PCH_TGP(dev_priv))
4613 return icl_hpd_pin(dev_priv, port);
4614
4615 return HPD_PORT_A + port - PORT_A;
4616 }
4617
intel_ddi_is_tc(struct drm_i915_private * i915,enum port port)4618 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port)
4619 {
4620 if (DISPLAY_VER(i915) >= 12)
4621 return port >= PORT_TC1;
4622 else if (DISPLAY_VER(i915) >= 11)
4623 return port >= PORT_C;
4624 else
4625 return false;
4626 }
4627
intel_ddi_encoder_suspend(struct intel_encoder * encoder)4628 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
4629 {
4630 intel_dp_encoder_suspend(encoder);
4631 }
4632
intel_ddi_tc_encoder_suspend_complete(struct intel_encoder * encoder)4633 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder)
4634 {
4635 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4636 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4637
4638 intel_tc_port_suspend(dig_port);
4639 }
4640
intel_ddi_encoder_shutdown(struct intel_encoder * encoder)4641 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
4642 {
4643 intel_dp_encoder_shutdown(encoder);
4644 intel_hdmi_encoder_shutdown(encoder);
4645 }
4646
intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder * encoder)4647 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder)
4648 {
4649 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4650 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4651
4652 intel_tc_port_cleanup(dig_port);
4653 }
4654
4655 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
4656 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
4657
port_strap_detected(struct drm_i915_private * i915,enum port port)4658 static bool port_strap_detected(struct drm_i915_private *i915, enum port port)
4659 {
4660 /* straps not used on skl+ */
4661 if (DISPLAY_VER(i915) >= 9)
4662 return true;
4663
4664 switch (port) {
4665 case PORT_A:
4666 return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
4667 case PORT_B:
4668 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED;
4669 case PORT_C:
4670 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED;
4671 case PORT_D:
4672 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED;
4673 case PORT_E:
4674 return true; /* no strap for DDI-E */
4675 default:
4676 MISSING_CASE(port);
4677 return false;
4678 }
4679 }
4680
need_aux_ch(struct intel_encoder * encoder,bool init_dp)4681 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp)
4682 {
4683 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4684 enum phy phy = intel_port_to_phy(i915, encoder->port);
4685
4686 return init_dp || intel_phy_is_tc(i915, phy);
4687 }
4688
assert_has_icl_dsi(struct drm_i915_private * i915)4689 static bool assert_has_icl_dsi(struct drm_i915_private *i915)
4690 {
4691 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) &&
4692 !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11,
4693 "Platform does not support DSI\n");
4694 }
4695
port_in_use(struct drm_i915_private * i915,enum port port)4696 static bool port_in_use(struct drm_i915_private *i915, enum port port)
4697 {
4698 struct intel_encoder *encoder;
4699
4700 for_each_intel_encoder(&i915->drm, encoder) {
4701 /* FIXME what about second port for dual link DSI? */
4702 if (encoder->port == port)
4703 return true;
4704 }
4705
4706 return false;
4707 }
4708
intel_ddi_init(struct drm_i915_private * dev_priv,const struct intel_bios_encoder_data * devdata)4709 void intel_ddi_init(struct drm_i915_private *dev_priv,
4710 const struct intel_bios_encoder_data *devdata)
4711 {
4712 struct intel_digital_port *dig_port;
4713 struct intel_encoder *encoder;
4714 bool init_hdmi, init_dp;
4715 enum port port;
4716 enum phy phy;
4717
4718 port = intel_bios_encoder_port(devdata);
4719 if (port == PORT_NONE)
4720 return;
4721
4722 if (!port_strap_detected(dev_priv, port)) {
4723 drm_dbg_kms(&dev_priv->drm,
4724 "Port %c strap not detected\n", port_name(port));
4725 return;
4726 }
4727
4728 if (!assert_port_valid(dev_priv, port))
4729 return;
4730
4731 if (port_in_use(dev_priv, port)) {
4732 drm_dbg_kms(&dev_priv->drm,
4733 "Port %c already claimed\n", port_name(port));
4734 return;
4735 }
4736
4737 if (intel_bios_encoder_supports_dsi(devdata)) {
4738 /* BXT/GLK handled elsewhere, for now at least */
4739 if (!assert_has_icl_dsi(dev_priv))
4740 return;
4741
4742 icl_dsi_init(dev_priv, devdata);
4743 return;
4744 }
4745
4746 phy = intel_port_to_phy(dev_priv, port);
4747
4748 /*
4749 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
4750 * have taken over some of the PHYs and made them unavailable to the
4751 * driver. In that case we should skip initializing the corresponding
4752 * outputs.
4753 */
4754 if (intel_hti_uses_phy(dev_priv, phy)) {
4755 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
4756 port_name(port), phy_name(phy));
4757 return;
4758 }
4759
4760 init_hdmi = intel_bios_encoder_supports_dvi(devdata) ||
4761 intel_bios_encoder_supports_hdmi(devdata);
4762 init_dp = intel_bios_encoder_supports_dp(devdata);
4763
4764 if (intel_bios_encoder_is_lspcon(devdata)) {
4765 /*
4766 * Lspcon device needs to be driven with DP connector
4767 * with special detection sequence. So make sure DP
4768 * is initialized before lspcon.
4769 */
4770 init_dp = true;
4771 init_hdmi = false;
4772 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
4773 port_name(port));
4774 }
4775
4776 if (!init_dp && !init_hdmi) {
4777 drm_dbg_kms(&dev_priv->drm,
4778 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4779 port_name(port));
4780 return;
4781 }
4782
4783 if (intel_phy_is_snps(dev_priv, phy) &&
4784 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) {
4785 drm_dbg_kms(&dev_priv->drm,
4786 "SNPS PHY %c failed to calibrate, proceeding anyway\n",
4787 phy_name(phy));
4788 }
4789
4790 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
4791 if (!dig_port)
4792 return;
4793
4794 dig_port->aux_ch = AUX_CH_NONE;
4795
4796 encoder = &dig_port->base;
4797 encoder->devdata = devdata;
4798
4799 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
4800 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4801 DRM_MODE_ENCODER_TMDS,
4802 "DDI %c/PHY %c",
4803 port_name(port - PORT_D_XELPD + PORT_D),
4804 phy_name(phy));
4805 } else if (DISPLAY_VER(dev_priv) >= 12) {
4806 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4807
4808 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4809 DRM_MODE_ENCODER_TMDS,
4810 "DDI %s%c/PHY %s%c",
4811 port >= PORT_TC1 ? "TC" : "",
4812 port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
4813 tc_port != TC_PORT_NONE ? "TC" : "",
4814 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4815 } else if (DISPLAY_VER(dev_priv) >= 11) {
4816 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4817
4818 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4819 DRM_MODE_ENCODER_TMDS,
4820 "DDI %c%s/PHY %s%c",
4821 port_name(port),
4822 port >= PORT_C ? " (TC)" : "",
4823 tc_port != TC_PORT_NONE ? "TC" : "",
4824 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4825 } else {
4826 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4827 DRM_MODE_ENCODER_TMDS,
4828 "DDI %c/PHY %c", port_name(port), phy_name(phy));
4829 }
4830
4831 mutex_init(&dig_port->hdcp_mutex);
4832 dig_port->num_hdcp_streams = 0;
4833
4834 encoder->hotplug = intel_ddi_hotplug;
4835 encoder->compute_output_type = intel_ddi_compute_output_type;
4836 encoder->compute_config = intel_ddi_compute_config;
4837 encoder->compute_config_late = intel_ddi_compute_config_late;
4838 encoder->enable = intel_enable_ddi;
4839 encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4840 encoder->pre_enable = intel_ddi_pre_enable;
4841 encoder->disable = intel_disable_ddi;
4842 encoder->post_pll_disable = intel_ddi_post_pll_disable;
4843 encoder->post_disable = intel_ddi_post_disable;
4844 encoder->update_pipe = intel_ddi_update_pipe;
4845 encoder->get_hw_state = intel_ddi_get_hw_state;
4846 encoder->sync_state = intel_ddi_sync_state;
4847 encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
4848 encoder->suspend = intel_ddi_encoder_suspend;
4849 encoder->shutdown = intel_ddi_encoder_shutdown;
4850 encoder->get_power_domains = intel_ddi_get_power_domains;
4851
4852 encoder->type = INTEL_OUTPUT_DDI;
4853 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
4854 encoder->port = port;
4855 encoder->cloneable = 0;
4856 encoder->pipe_mask = ~0;
4857
4858 if (DISPLAY_VER(dev_priv) >= 14) {
4859 encoder->enable_clock = intel_mtl_pll_enable;
4860 encoder->disable_clock = intel_mtl_pll_disable;
4861 encoder->port_pll_type = intel_mtl_port_pll_type;
4862 encoder->get_config = mtl_ddi_get_config;
4863 } else if (IS_DG2(dev_priv)) {
4864 encoder->enable_clock = intel_mpllb_enable;
4865 encoder->disable_clock = intel_mpllb_disable;
4866 encoder->get_config = dg2_ddi_get_config;
4867 } else if (IS_ALDERLAKE_S(dev_priv)) {
4868 encoder->enable_clock = adls_ddi_enable_clock;
4869 encoder->disable_clock = adls_ddi_disable_clock;
4870 encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
4871 encoder->get_config = adls_ddi_get_config;
4872 } else if (IS_ROCKETLAKE(dev_priv)) {
4873 encoder->enable_clock = rkl_ddi_enable_clock;
4874 encoder->disable_clock = rkl_ddi_disable_clock;
4875 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
4876 encoder->get_config = rkl_ddi_get_config;
4877 } else if (IS_DG1(dev_priv)) {
4878 encoder->enable_clock = dg1_ddi_enable_clock;
4879 encoder->disable_clock = dg1_ddi_disable_clock;
4880 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
4881 encoder->get_config = dg1_ddi_get_config;
4882 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
4883 if (intel_ddi_is_tc(dev_priv, port)) {
4884 encoder->enable_clock = jsl_ddi_tc_enable_clock;
4885 encoder->disable_clock = jsl_ddi_tc_disable_clock;
4886 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
4887 encoder->port_pll_type = icl_ddi_tc_port_pll_type;
4888 encoder->get_config = icl_ddi_combo_get_config;
4889 } else {
4890 encoder->enable_clock = icl_ddi_combo_enable_clock;
4891 encoder->disable_clock = icl_ddi_combo_disable_clock;
4892 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4893 encoder->get_config = icl_ddi_combo_get_config;
4894 }
4895 } else if (DISPLAY_VER(dev_priv) >= 11) {
4896 if (intel_ddi_is_tc(dev_priv, port)) {
4897 encoder->enable_clock = icl_ddi_tc_enable_clock;
4898 encoder->disable_clock = icl_ddi_tc_disable_clock;
4899 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
4900 encoder->port_pll_type = icl_ddi_tc_port_pll_type;
4901 encoder->get_config = icl_ddi_tc_get_config;
4902 } else {
4903 encoder->enable_clock = icl_ddi_combo_enable_clock;
4904 encoder->disable_clock = icl_ddi_combo_disable_clock;
4905 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4906 encoder->get_config = icl_ddi_combo_get_config;
4907 }
4908 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4909 /* BXT/GLK have fixed PLL->port mapping */
4910 encoder->get_config = bxt_ddi_get_config;
4911 } else if (DISPLAY_VER(dev_priv) == 9) {
4912 encoder->enable_clock = skl_ddi_enable_clock;
4913 encoder->disable_clock = skl_ddi_disable_clock;
4914 encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
4915 encoder->get_config = skl_ddi_get_config;
4916 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4917 encoder->enable_clock = hsw_ddi_enable_clock;
4918 encoder->disable_clock = hsw_ddi_disable_clock;
4919 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
4920 encoder->get_config = hsw_ddi_get_config;
4921 }
4922
4923 if (DISPLAY_VER(dev_priv) >= 14) {
4924 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;
4925 } else if (IS_DG2(dev_priv)) {
4926 encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
4927 } else if (DISPLAY_VER(dev_priv) >= 12) {
4928 if (intel_phy_is_combo(dev_priv, phy))
4929 encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
4930 else
4931 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels;
4932 } else if (DISPLAY_VER(dev_priv) >= 11) {
4933 if (intel_phy_is_combo(dev_priv, phy))
4934 encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
4935 else
4936 encoder->set_signal_levels = icl_mg_phy_set_signal_levels;
4937 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4938 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels;
4939 } else {
4940 encoder->set_signal_levels = hsw_set_signal_levels;
4941 }
4942
4943 intel_ddi_buf_trans_init(encoder);
4944
4945 if (DISPLAY_VER(dev_priv) >= 13)
4946 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);
4947 else if (IS_DG1(dev_priv))
4948 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
4949 else if (IS_ROCKETLAKE(dev_priv))
4950 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
4951 else if (DISPLAY_VER(dev_priv) >= 12)
4952 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
4953 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
4954 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
4955 else if (DISPLAY_VER(dev_priv) == 11)
4956 encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
4957 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
4958 encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
4959 else
4960 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
4961
4962 if (DISPLAY_VER(dev_priv) >= 11)
4963 dig_port->saved_port_bits =
4964 intel_de_read(dev_priv, DDI_BUF_CTL(port))
4965 & DDI_BUF_PORT_REVERSAL;
4966 else
4967 dig_port->saved_port_bits =
4968 intel_de_read(dev_priv, DDI_BUF_CTL(port))
4969 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4970
4971 if (intel_bios_encoder_lane_reversal(devdata))
4972 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
4973
4974 dig_port->dp.output_reg = INVALID_MMIO_REG;
4975 dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
4976
4977 if (need_aux_ch(encoder, init_dp)) {
4978 dig_port->aux_ch = intel_dp_aux_ch(encoder);
4979 if (dig_port->aux_ch == AUX_CH_NONE)
4980 goto err;
4981 }
4982
4983 if (intel_phy_is_tc(dev_priv, phy)) {
4984 bool is_legacy =
4985 !intel_bios_encoder_supports_typec_usb(devdata) &&
4986 !intel_bios_encoder_supports_tbt(devdata);
4987
4988 if (!is_legacy && init_hdmi) {
4989 is_legacy = !init_dp;
4990
4991 drm_dbg_kms(&dev_priv->drm,
4992 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n",
4993 port_name(port),
4994 str_yes_no(init_dp),
4995 is_legacy ? "legacy" : "non-legacy");
4996 }
4997
4998 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete;
4999 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete;
5000
5001 if (intel_tc_port_init(dig_port, is_legacy) < 0)
5002 goto err;
5003 }
5004
5005 drm_WARN_ON(&dev_priv->drm, port > PORT_I);
5006 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port);
5007
5008 if (DISPLAY_VER(dev_priv) >= 11) {
5009 if (intel_phy_is_tc(dev_priv, phy))
5010 dig_port->connected = intel_tc_port_connected;
5011 else
5012 dig_port->connected = lpt_digital_port_connected;
5013 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
5014 dig_port->connected = bdw_digital_port_connected;
5015 } else if (DISPLAY_VER(dev_priv) == 9) {
5016 dig_port->connected = lpt_digital_port_connected;
5017 } else if (IS_BROADWELL(dev_priv)) {
5018 if (port == PORT_A)
5019 dig_port->connected = bdw_digital_port_connected;
5020 else
5021 dig_port->connected = lpt_digital_port_connected;
5022 } else if (IS_HASWELL(dev_priv)) {
5023 if (port == PORT_A)
5024 dig_port->connected = hsw_digital_port_connected;
5025 else
5026 dig_port->connected = lpt_digital_port_connected;
5027 }
5028
5029 intel_infoframe_init(dig_port);
5030
5031 if (init_dp) {
5032 if (!intel_ddi_init_dp_connector(dig_port))
5033 goto err;
5034
5035 dig_port->hpd_pulse = intel_dp_hpd_pulse;
5036
5037 if (dig_port->dp.mso_link_count)
5038 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv);
5039 }
5040
5041 /*
5042 * In theory we don't need the encoder->type check,
5043 * but leave it just in case we have some really bad VBTs...
5044 */
5045 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
5046 if (!intel_ddi_init_hdmi_connector(dig_port))
5047 goto err;
5048 }
5049
5050 return;
5051
5052 err:
5053 drm_encoder_cleanup(&encoder->base);
5054 kfree(dig_port);
5055 }
5056
