1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/module.h>
24 #include <linux/slab.h>
25
26 #include "vega12/smu9_driver_if.h"
27 #include "vega12_processpptables.h"
28 #include "ppatomfwctrl.h"
29 #include "atomfirmware.h"
30 #include "pp_debug.h"
31 #include "cgs_common.h"
32 #include "vega12_pptable.h"
33
set_hw_cap(struct pp_hwmgr * hwmgr,bool enable,enum phm_platform_caps cap)34 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
35 enum phm_platform_caps cap)
36 {
37 if (enable)
38 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
39 else
40 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
41 }
42
get_powerplay_table(struct pp_hwmgr * hwmgr)43 static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
44 {
45 int index = GetIndexIntoMasterDataTable(powerplayinfo);
46
47 u16 size;
48 u8 frev, crev;
49 const void *table_address = hwmgr->soft_pp_table;
50
51 if (!table_address) {
52 table_address = (ATOM_Vega12_POWERPLAYTABLE *)
53 smu_atom_get_data_table(hwmgr->adev, index,
54 &size, &frev, &crev);
55
56 hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/
57 hwmgr->soft_pp_table_size = size;
58 }
59
60 return table_address;
61 }
62
check_powerplay_tables(struct pp_hwmgr * hwmgr,const ATOM_Vega12_POWERPLAYTABLE * powerplay_table)63 static int check_powerplay_tables(
64 struct pp_hwmgr *hwmgr,
65 const ATOM_Vega12_POWERPLAYTABLE *powerplay_table)
66 {
67 PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
68 ATOM_VEGA12_TABLE_REVISION_VEGA12),
69 "Unsupported PPTable format!", return -1);
70 PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
71 "Invalid PowerPlay Table!", return -1);
72
73 return 0;
74 }
75
set_platform_caps(struct pp_hwmgr * hwmgr,uint32_t powerplay_caps)76 static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
77 {
78 set_hw_cap(
79 hwmgr,
80 0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_POWERPLAY),
81 PHM_PlatformCaps_PowerPlaySupport);
82
83 set_hw_cap(
84 hwmgr,
85 0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
86 PHM_PlatformCaps_BiosPowerSourceControl);
87
88 set_hw_cap(
89 hwmgr,
90 0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_BACO),
91 PHM_PlatformCaps_BACO);
92
93 set_hw_cap(
94 hwmgr,
95 0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_BAMACO),
96 PHM_PlatformCaps_BAMACO);
97
98 return 0;
99 }
100
append_vbios_pptable(struct pp_hwmgr * hwmgr,PPTable_t * ppsmc_pptable)101 static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable)
102 {
103 struct pp_atomfwctrl_smc_dpm_parameters smc_dpm_table;
104
105 PP_ASSERT_WITH_CODE(
106 pp_atomfwctrl_get_smc_dpm_information(hwmgr, &smc_dpm_table) == 0,
107 "[appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!",
108 return -1);
109
110 ppsmc_pptable->Liquid1_I2C_address = smc_dpm_table.liquid1_i2c_address;
111 ppsmc_pptable->Liquid2_I2C_address = smc_dpm_table.liquid2_i2c_address;
112 ppsmc_pptable->Vr_I2C_address = smc_dpm_table.vr_i2c_address;
113 ppsmc_pptable->Plx_I2C_address = smc_dpm_table.plx_i2c_address;
114
115 ppsmc_pptable->Liquid_I2C_LineSCL = smc_dpm_table.liquid_i2c_linescl;
116 ppsmc_pptable->Liquid_I2C_LineSDA = smc_dpm_table.liquid_i2c_linesda;
117 ppsmc_pptable->Vr_I2C_LineSCL = smc_dpm_table.vr_i2c_linescl;
118 ppsmc_pptable->Vr_I2C_LineSDA = smc_dpm_table.vr_i2c_linesda;
119
120 ppsmc_pptable->Plx_I2C_LineSCL = smc_dpm_table.plx_i2c_linescl;
121 ppsmc_pptable->Plx_I2C_LineSDA = smc_dpm_table.plx_i2c_linesda;
122 ppsmc_pptable->VrSensorPresent = smc_dpm_table.vrsensorpresent;
123 ppsmc_pptable->LiquidSensorPresent = smc_dpm_table.liquidsensorpresent;
124
125 ppsmc_pptable->MaxVoltageStepGfx = smc_dpm_table.maxvoltagestepgfx;
126 ppsmc_pptable->MaxVoltageStepSoc = smc_dpm_table.maxvoltagestepsoc;
127
128 ppsmc_pptable->VddGfxVrMapping = smc_dpm_table.vddgfxvrmapping;
129 ppsmc_pptable->VddSocVrMapping = smc_dpm_table.vddsocvrmapping;
130 ppsmc_pptable->VddMem0VrMapping = smc_dpm_table.vddmem0vrmapping;
131 ppsmc_pptable->VddMem1VrMapping = smc_dpm_table.vddmem1vrmapping;
132
133 ppsmc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table.gfxulvphasesheddingmask;
134 ppsmc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table.soculvphasesheddingmask;
135
136 ppsmc_pptable->GfxMaxCurrent = smc_dpm_table.gfxmaxcurrent;
137 ppsmc_pptable->GfxOffset = smc_dpm_table.gfxoffset;
138 ppsmc_pptable->Padding_TelemetryGfx = smc_dpm_table.padding_telemetrygfx;
139
140 ppsmc_pptable->SocMaxCurrent = smc_dpm_table.socmaxcurrent;
141 ppsmc_pptable->SocOffset = smc_dpm_table.socoffset;
142 ppsmc_pptable->Padding_TelemetrySoc = smc_dpm_table.padding_telemetrysoc;
143
144 ppsmc_pptable->Mem0MaxCurrent = smc_dpm_table.mem0maxcurrent;
145 ppsmc_pptable->Mem0Offset = smc_dpm_table.mem0offset;
146 ppsmc_pptable->Padding_TelemetryMem0 = smc_dpm_table.padding_telemetrymem0;
147
148 ppsmc_pptable->Mem1MaxCurrent = smc_dpm_table.mem1maxcurrent;
149 ppsmc_pptable->Mem1Offset = smc_dpm_table.mem1offset;
150 ppsmc_pptable->Padding_TelemetryMem1 = smc_dpm_table.padding_telemetrymem1;
151
152 ppsmc_pptable->AcDcGpio = smc_dpm_table.acdcgpio;
153 ppsmc_pptable->AcDcPolarity = smc_dpm_table.acdcpolarity;
154 ppsmc_pptable->VR0HotGpio = smc_dpm_table.vr0hotgpio;
155 ppsmc_pptable->VR0HotPolarity = smc_dpm_table.vr0hotpolarity;
156
157 ppsmc_pptable->VR1HotGpio = smc_dpm_table.vr1hotgpio;
158 ppsmc_pptable->VR1HotPolarity = smc_dpm_table.vr1hotpolarity;
159 ppsmc_pptable->Padding1 = smc_dpm_table.padding1;
160 ppsmc_pptable->Padding2 = smc_dpm_table.padding2;
161
162 ppsmc_pptable->LedPin0 = smc_dpm_table.ledpin0;
163 ppsmc_pptable->LedPin1 = smc_dpm_table.ledpin1;
164 ppsmc_pptable->LedPin2 = smc_dpm_table.ledpin2;
165
166 ppsmc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table.pllgfxclkspreadenabled;
167 ppsmc_pptable->PllGfxclkSpreadPercent = smc_dpm_table.pllgfxclkspreadpercent;
168 ppsmc_pptable->PllGfxclkSpreadFreq = smc_dpm_table.pllgfxclkspreadfreq;
169
170 ppsmc_pptable->UclkSpreadEnabled = 0;
171 ppsmc_pptable->UclkSpreadPercent = smc_dpm_table.uclkspreadpercent;
172 ppsmc_pptable->UclkSpreadFreq = smc_dpm_table.uclkspreadfreq;
173
174 ppsmc_pptable->SocclkSpreadEnabled = 0;
175 ppsmc_pptable->SocclkSpreadPercent = smc_dpm_table.socclkspreadpercent;
176 ppsmc_pptable->SocclkSpreadFreq = smc_dpm_table.socclkspreadfreq;
177
178 ppsmc_pptable->AcgGfxclkSpreadEnabled = smc_dpm_table.acggfxclkspreadenabled;
179 ppsmc_pptable->AcgGfxclkSpreadPercent = smc_dpm_table.acggfxclkspreadpercent;
180 ppsmc_pptable->AcgGfxclkSpreadFreq = smc_dpm_table.acggfxclkspreadfreq;
181
182 ppsmc_pptable->Vr2_I2C_address = smc_dpm_table.Vr2_I2C_address;
183
184 ppsmc_pptable->Vr2_I2C_address = smc_dpm_table.Vr2_I2C_address;
185
186 return 0;
187 }
188
189 #define VEGA12_ENGINECLOCK_HARDMAX 198000
init_powerplay_table_information(struct pp_hwmgr * hwmgr,const ATOM_Vega12_POWERPLAYTABLE * powerplay_table)190 static int init_powerplay_table_information(
191 struct pp_hwmgr *hwmgr,
192 const ATOM_Vega12_POWERPLAYTABLE *powerplay_table)
193 {
194 struct phm_ppt_v3_information *pptable_information =
195 (struct phm_ppt_v3_information *)hwmgr->pptable;
196 uint32_t disable_power_control = 0;
197
198 hwmgr->thermal_controller.ucType = powerplay_table->ucThermalControllerType;
199 pptable_information->uc_thermal_controller_type = powerplay_table->ucThermalControllerType;
200
201 set_hw_cap(hwmgr,
202 ATOM_VEGA12_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
203 PHM_PlatformCaps_ThermalController);
204
205 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
206
207 if (le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX]) > VEGA12_ENGINECLOCK_HARDMAX)
208 hwmgr->platform_descriptor.overdriveLimit.engineClock = VEGA12_ENGINECLOCK_HARDMAX;
209 else
210 hwmgr->platform_descriptor.overdriveLimit.engineClock =
211 le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX]);
212 hwmgr->platform_descriptor.overdriveLimit.memoryClock =
213 le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_UCLKFMAX]);
214
215 phm_copy_overdrive_settings_limits_array(hwmgr,
216 &pptable_information->od_settings_max,
217 powerplay_table->ODSettingsMax,
218 ATOM_VEGA12_ODSETTING_COUNT);
219 phm_copy_overdrive_settings_limits_array(hwmgr,
220 &pptable_information->od_settings_min,
221 powerplay_table->ODSettingsMin,
222 ATOM_VEGA12_ODSETTING_COUNT);
223
224 /* hwmgr->platformDescriptor.minOverdriveVDDC = 0;
225 hwmgr->platformDescriptor.maxOverdriveVDDC = 0;
226 hwmgr->platformDescriptor.overdriveVDDCStep = 0; */
227
228 if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0
229 && hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0)
230 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ACOverdriveSupport);
231
232 pptable_information->us_small_power_limit1 = le16_to_cpu(powerplay_table->usSmallPowerLimit1);
233 pptable_information->us_small_power_limit2 = le16_to_cpu(powerplay_table->usSmallPowerLimit2);
234 pptable_information->us_boost_power_limit = le16_to_cpu(powerplay_table->usBoostPowerLimit);
235 pptable_information->us_od_turbo_power_limit = le16_to_cpu(powerplay_table->usODTurboPowerLimit);
236 pptable_information->us_od_powersave_power_limit = le16_to_cpu(powerplay_table->usODPowerSavePowerLimit);
237
238 pptable_information->us_software_shutdown_temp = le16_to_cpu(powerplay_table->usSoftwareShutdownTemp);
239
240 hwmgr->platform_descriptor.TDPODLimit = le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_POWERPERCENTAGE]);
241
242 disable_power_control = 0;
243 if (!disable_power_control) {
244 /* enable TDP overdrive (PowerControl) feature as well if supported */
245 if (hwmgr->platform_descriptor.TDPODLimit)
246 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
247 PHM_PlatformCaps_PowerControl);
248 }
249
250 phm_copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_max, powerplay_table->PowerSavingClockMax, ATOM_VEGA12_PPCLOCK_COUNT);
251 phm_copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_min, powerplay_table->PowerSavingClockMin, ATOM_VEGA12_PPCLOCK_COUNT);
252
253 pptable_information->smc_pptable = kmemdup(&(powerplay_table->smcPPTable),
254 sizeof(PPTable_t), GFP_KERNEL);
255 if (pptable_information->smc_pptable == NULL)
256 return -ENOMEM;
257
258 return append_vbios_pptable(hwmgr, (pptable_information->smc_pptable));
259 }
260
vega12_pp_tables_initialize(struct pp_hwmgr * hwmgr)261 static int vega12_pp_tables_initialize(struct pp_hwmgr *hwmgr)
262 {
263 int result = 0;
264 const ATOM_Vega12_POWERPLAYTABLE *powerplay_table;
265
266 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL);
267 PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
268 "Failed to allocate hwmgr->pptable!", return -ENOMEM);
269
270 powerplay_table = get_powerplay_table(hwmgr);
271 PP_ASSERT_WITH_CODE((powerplay_table != NULL),
272 "Missing PowerPlay Table!", return -1);
273
274 result = check_powerplay_tables(hwmgr, powerplay_table);
275 PP_ASSERT_WITH_CODE((result == 0),
276 "check_powerplay_tables failed", return result);
277
278 result = set_platform_caps(hwmgr,
279 le32_to_cpu(powerplay_table->ulPlatformCaps));
280 PP_ASSERT_WITH_CODE((result == 0),
281 "set_platform_caps failed", return result);
282
283 result = init_powerplay_table_information(hwmgr, powerplay_table);
284 PP_ASSERT_WITH_CODE((result == 0),
285 "init_powerplay_table_information failed", return result);
286
287 return result;
288 }
289
vega12_pp_tables_uninitialize(struct pp_hwmgr * hwmgr)290 static int vega12_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
291 {
292 struct phm_ppt_v3_information *pp_table_info =
293 (struct phm_ppt_v3_information *)(hwmgr->pptable);
294
295 kfree(pp_table_info->power_saving_clock_max);
296 pp_table_info->power_saving_clock_max = NULL;
297
298 kfree(pp_table_info->power_saving_clock_min);
299 pp_table_info->power_saving_clock_min = NULL;
300
301 kfree(pp_table_info->od_settings_max);
302 pp_table_info->od_settings_max = NULL;
303
304 kfree(pp_table_info->od_settings_min);
305 pp_table_info->od_settings_min = NULL;
306
307 kfree(pp_table_info->smc_pptable);
308 pp_table_info->smc_pptable = NULL;
309
310 kfree(hwmgr->pptable);
311 hwmgr->pptable = NULL;
312
313 return 0;
314 }
315
316 const struct pp_table_func vega12_pptable_funcs = {
317 .pptable_init = vega12_pp_tables_initialize,
318 .pptable_fini = vega12_pp_tables_uninitialize,
319 };
320
321 #if 0
322 static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
323 uint16_t classification, uint16_t classification2)
324 {
325 uint32_t result = 0;
326
327 if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT)
328 result |= PP_StateClassificationFlag_Boot;
329
330 if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL)
331 result |= PP_StateClassificationFlag_Thermal;
332
333 if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
334 result |= PP_StateClassificationFlag_LimitedPowerSource;
335
336 if (classification & ATOM_PPLIB_CLASSIFICATION_REST)
337 result |= PP_StateClassificationFlag_Rest;
338
339 if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED)
340 result |= PP_StateClassificationFlag_Forced;
341
342 if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI)
343 result |= PP_StateClassificationFlag_ACPI;
344
345 if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
346 result |= PP_StateClassificationFlag_LimitedPowerSource_2;
347
348 return result;
349 }
350
351 int vega12_get_powerplay_table_entry(struct pp_hwmgr *hwmgr,
352 uint32_t entry_index, struct pp_power_state *power_state,
353 int (*call_back_func)(struct pp_hwmgr *, void *,
354 struct pp_power_state *, void *, uint32_t))
355 {
356 int result = 0;
357 const ATOM_Vega12_State_Array *state_arrays;
358 const ATOM_Vega12_State *state_entry;
359 const ATOM_Vega12_POWERPLAYTABLE *pp_table =
360 get_powerplay_table(hwmgr);
361
362 PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!",
363 return -1;);
364 power_state->classification.bios_index = entry_index;
365
366 if (pp_table->sHeader.format_revision >=
367 ATOM_Vega12_TABLE_REVISION_VEGA12) {
368 state_arrays = (ATOM_Vega12_State_Array *)
369 (((unsigned long)pp_table) +
370 le16_to_cpu(pp_table->usStateArrayOffset));
371
372 PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0,
373 "Invalid PowerPlay Table State Array Offset.",
374 return -1);
375 PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
376 "Invalid PowerPlay Table State Array.",
377 return -1);
378 PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),
379 "Invalid PowerPlay Table State Array Entry.",
380 return -1);
381
382 state_entry = &(state_arrays->states[entry_index]);
383
384 result = call_back_func(hwmgr, (void *)state_entry, power_state,
385 (void *)pp_table,
386 make_classification_flags(hwmgr,
387 le16_to_cpu(state_entry->usClassification),
388 le16_to_cpu(state_entry->usClassification2)));
389 }
390
391 if (!result && (power_state->classification.flags &
392 PP_StateClassificationFlag_Boot))
393 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
394
395 return result;
396 }
397 #endif
398
