1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "common_baco.h"
25
26
baco_wait_register(struct pp_hwmgr * hwmgr,u32 reg,u32 mask,u32 value)27 static bool baco_wait_register(struct pp_hwmgr *hwmgr, u32 reg, u32 mask, u32 value)
28 {
29 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
30 u32 timeout = 5000, data;
31
32 do {
33 msleep(1);
34 data = RREG32(reg);
35 timeout--;
36 } while (value != (data & mask) && (timeout != 0));
37
38 if (timeout == 0)
39 return false;
40
41 return true;
42 }
43
baco_cmd_handler(struct pp_hwmgr * hwmgr,u32 command,u32 reg,u32 mask,u32 shift,u32 value,u32 timeout)44 static bool baco_cmd_handler(struct pp_hwmgr *hwmgr, u32 command, u32 reg, u32 mask,
45 u32 shift, u32 value, u32 timeout)
46 {
47 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
48 u32 data;
49 bool ret = true;
50
51 switch (command) {
52 case CMD_WRITE:
53 WREG32(reg, value << shift);
54 break;
55 case CMD_READMODIFYWRITE:
56 data = RREG32(reg);
57 data = (data & (~mask)) | (value << shift);
58 WREG32(reg, data);
59 break;
60 case CMD_WAITFOR:
61 ret = baco_wait_register(hwmgr, reg, mask, value);
62 break;
63 case CMD_DELAY_MS:
64 if (timeout)
65 /* Delay in milli Seconds */
66 msleep(timeout);
67 break;
68 case CMD_DELAY_US:
69 if (timeout)
70 /* Delay in micro Seconds */
71 udelay(timeout);
72 break;
73
74 default:
75 dev_warn(adev->dev, "Invalid BACO command.\n");
76 ret = false;
77 }
78
79 return ret;
80 }
81
baco_program_registers(struct pp_hwmgr * hwmgr,const struct baco_cmd_entry * entry,const u32 array_size)82 bool baco_program_registers(struct pp_hwmgr *hwmgr,
83 const struct baco_cmd_entry *entry,
84 const u32 array_size)
85 {
86 u32 i, reg = 0;
87
88 for (i = 0; i < array_size; i++) {
89 if ((entry[i].cmd == CMD_WRITE) ||
90 (entry[i].cmd == CMD_READMODIFYWRITE) ||
91 (entry[i].cmd == CMD_WAITFOR))
92 reg = entry[i].reg_offset;
93 if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask,
94 entry[i].shift, entry[i].val, entry[i].timeout))
95 return false;
96 }
97
98 return true;
99 }
100
soc15_baco_program_registers(struct pp_hwmgr * hwmgr,const struct soc15_baco_cmd_entry * entry,const u32 array_size)101 bool soc15_baco_program_registers(struct pp_hwmgr *hwmgr,
102 const struct soc15_baco_cmd_entry *entry,
103 const u32 array_size)
104 {
105 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
106 u32 i, reg = 0;
107
108 for (i = 0; i < array_size; i++) {
109 if ((entry[i].cmd == CMD_WRITE) ||
110 (entry[i].cmd == CMD_READMODIFYWRITE) ||
111 (entry[i].cmd == CMD_WAITFOR))
112 reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg]
113 + entry[i].reg_offset;
114 if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask,
115 entry[i].shift, entry[i].val, entry[i].timeout))
116 return false;
117 }
118
119 return true;
120 }
121
