1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dce110/dce110_hw_sequencer.h"
28 #include "dcn10/dcn10_hw_sequencer.h"
29 #include "dcn20/dcn20_hwseq.h"
30 #include "dcn21/dcn21_hwseq.h"
31 #include "dcn30/dcn30_hwseq.h"
32 #include "dcn301/dcn301_hwseq.h"
33 #include "dcn31/dcn31_hwseq.h"
34 #include "dcn314/dcn314_hwseq.h"
35
36 #include "dcn314_init.h"
37
38 static const struct hw_sequencer_funcs dcn314_funcs = {
39 .program_gamut_remap = dcn10_program_gamut_remap,
40 .init_hw = dcn31_init_hw,
41 .power_down_on_boot = dcn10_power_down_on_boot,
42 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
43 .apply_ctx_for_surface = NULL,
44 .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
45 .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
46 .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
47 .update_plane_addr = dcn20_update_plane_addr,
48 .update_dchub = dcn10_update_dchub,
49 .update_pending_status = dcn10_update_pending_status,
50 .program_output_csc = dcn20_program_output_csc,
51 .enable_accelerated_mode = dce110_enable_accelerated_mode,
52 .enable_timing_synchronization = dcn10_enable_timing_synchronization,
53 .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
54 .update_info_frame = dcn31_update_info_frame,
55 .send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
56 .enable_stream = dcn20_enable_stream,
57 .disable_stream = dce110_disable_stream,
58 .unblank_stream = dcn20_unblank_stream,
59 .blank_stream = dce110_blank_stream,
60 .enable_audio_stream = dce110_enable_audio_stream,
61 .disable_audio_stream = dce110_disable_audio_stream,
62 .disable_plane = dcn20_disable_plane,
63 .disable_pixel_data = dcn20_disable_pixel_data,
64 .pipe_control_lock = dcn20_pipe_control_lock,
65 .interdependent_update_lock = dcn10_lock_all_pipes,
66 .cursor_lock = dcn10_cursor_lock,
67 .prepare_bandwidth = dcn20_prepare_bandwidth,
68 .optimize_bandwidth = dcn20_optimize_bandwidth,
69 .update_bandwidth = dcn20_update_bandwidth,
70 .set_drr = dcn10_set_drr,
71 .get_position = dcn10_get_position,
72 .set_static_screen_control = dcn30_set_static_screen_control,
73 .setup_stereo = dcn10_setup_stereo,
74 .set_avmute = dcn30_set_avmute,
75 .log_hw_state = dcn10_log_hw_state,
76 .get_hw_state = dcn10_get_hw_state,
77 .clear_status_bits = dcn10_clear_status_bits,
78 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
79 .edp_backlight_control = dce110_edp_backlight_control,
80 .edp_power_control = dce110_edp_power_control,
81 .edp_wait_for_T12 = dce110_edp_wait_for_T12,
82 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
83 .set_cursor_position = dcn10_set_cursor_position,
84 .set_cursor_attribute = dcn10_set_cursor_attribute,
85 .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
86 .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
87 .set_clock = dcn10_set_clock,
88 .get_clock = dcn10_get_clock,
89 .program_triplebuffer = dcn20_program_triple_buffer,
90 .enable_writeback = dcn30_enable_writeback,
91 .disable_writeback = dcn30_disable_writeback,
92 .update_writeback = dcn30_update_writeback,
93 .mmhubbub_warmup = dcn30_mmhubbub_warmup,
94 .dmdata_status_done = dcn20_dmdata_status_done,
95 .program_dmdata_engine = dcn30_program_dmdata_engine,
96 .set_dmdata_attributes = dcn20_set_dmdata_attributes,
97 .init_sys_ctx = dcn31_init_sys_ctx,
98 .init_vm_ctx = dcn20_init_vm_ctx,
99 .set_flip_control_gsl = dcn20_set_flip_control_gsl,
100 .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
101 .calc_vupdate_position = dcn10_calc_vupdate_position,
102 .power_down = dce110_power_down,
103 .set_backlight_level = dcn21_set_backlight_level,
104 .set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
105 .set_pipe = dcn21_set_pipe,
106 .enable_lvds_link_output = dce110_enable_lvds_link_output,
107 .enable_tmds_link_output = dce110_enable_tmds_link_output,
108 .enable_dp_link_output = dce110_enable_dp_link_output,
109 .disable_link_output = dcn314_disable_link_output,
110 .z10_restore = dcn31_z10_restore,
111 .z10_save_init = dcn31_z10_save_init,
112 .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
113 .optimize_pwr_state = dcn21_optimize_pwr_state,
114 .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
115 .update_visual_confirm_color = dcn10_update_visual_confirm_color,
116 };
117
118 static const struct hwseq_private_funcs dcn314_private_funcs = {
119 .init_pipes = dcn10_init_pipes,
120 .update_plane_addr = dcn20_update_plane_addr,
121 .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
122 .update_mpcc = dcn20_update_mpcc,
123 .set_input_transfer_func = dcn30_set_input_transfer_func,
124 .set_output_transfer_func = dcn30_set_output_transfer_func,
125 .power_down = dce110_power_down,
126 .enable_display_power_gating = dcn10_dummy_display_power_gating,
127 .blank_pixel_data = dcn20_blank_pixel_data,
128 .reset_hw_ctx_wrap = dcn31_reset_hw_ctx_wrap,
129 .enable_stream_timing = dcn20_enable_stream_timing,
130 .edp_backlight_control = dce110_edp_backlight_control,
131 .disable_stream_gating = dcn20_disable_stream_gating,
132 .enable_stream_gating = dcn20_enable_stream_gating,
133 .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
134 .did_underflow_occur = dcn10_did_underflow_occur,
135 .init_blank = dcn20_init_blank,
136 .disable_vga = dcn20_disable_vga,
137 .bios_golden_init = dcn10_bios_golden_init,
138 .plane_atomic_disable = dcn20_plane_atomic_disable,
139 .plane_atomic_power_down = dcn10_plane_atomic_power_down,
140 .enable_power_gating_plane = dcn314_enable_power_gating_plane,
141 .dpp_root_clock_control = dcn314_dpp_root_clock_control,
142 .hubp_pg_control = dcn31_hubp_pg_control,
143 .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
144 .update_odm = dcn314_update_odm,
145 .dsc_pg_control = dcn314_dsc_pg_control,
146 .set_hdr_multiplier = dcn10_set_hdr_multiplier,
147 .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
148 .wait_for_blank_complete = dcn20_wait_for_blank_complete,
149 .dccg_init = dcn20_dccg_init,
150 .set_blend_lut = dcn30_set_blend_lut,
151 .set_shaper_3dlut = dcn20_set_shaper_3dlut,
152 .setup_hpo_hw_control = dcn31_setup_hpo_hw_control,
153 .calculate_dccg_k1_k2_values = dcn314_calculate_dccg_k1_k2_values,
154 .set_pixels_per_cycle = dcn314_set_pixels_per_cycle,
155 .resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio,
156 };
157
dcn314_hw_sequencer_construct(struct dc * dc)158 void dcn314_hw_sequencer_construct(struct dc *dc)
159 {
160 dc->hwss = dcn314_funcs;
161 dc->hwseq->funcs = dcn314_private_funcs;
162
163 }
164
