1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright(c) 2022 Intel Corporation. All rights reserved. */
3 #include <linux/device.h>
4 #include <linux/module.h>
5 #include <linux/slab.h>
6
7 #include "cxlmem.h"
8 #include "cxlpci.h"
9
10 /**
11 * DOC: cxl port
12 *
13 * The port driver enumerates dport via PCI and scans for HDM
14 * (Host-managed-Device-Memory) decoder resources via the
15 * @component_reg_phys value passed in by the agent that registered the
16 * port. All descendant ports of a CXL root port (described by platform
17 * firmware) are managed in this drivers context. Each driver instance
18 * is responsible for tearing down the driver context of immediate
19 * descendant ports. The locking for this is validated by
20 * CONFIG_PROVE_CXL_LOCKING.
21 *
22 * The primary service this driver provides is presenting APIs to other
23 * drivers to utilize the decoders, and indicating to userspace (via bind
24 * status) the connectivity of the CXL.mem protocol throughout the
25 * PCIe topology.
26 */
27
schedule_detach(void * cxlmd)28 static void schedule_detach(void *cxlmd)
29 {
30 schedule_cxl_memdev_detach(cxlmd);
31 }
32
discover_region(struct device * dev,void * root)33 static int discover_region(struct device *dev, void *root)
34 {
35 struct cxl_endpoint_decoder *cxled;
36 int rc;
37
38 if (!is_endpoint_decoder(dev))
39 return 0;
40
41 cxled = to_cxl_endpoint_decoder(dev);
42 if ((cxled->cxld.flags & CXL_DECODER_F_ENABLE) == 0)
43 return 0;
44
45 if (cxled->state != CXL_DECODER_STATE_AUTO)
46 return 0;
47
48 /*
49 * Region enumeration is opportunistic, if this add-event fails,
50 * continue to the next endpoint decoder.
51 */
52 rc = cxl_add_to_region(root, cxled);
53 if (rc)
54 dev_dbg(dev, "failed to add to region: %#llx-%#llx\n",
55 cxled->cxld.hpa_range.start, cxled->cxld.hpa_range.end);
56
57 return 0;
58 }
59
cxl_switch_port_probe(struct cxl_port * port)60 static int cxl_switch_port_probe(struct cxl_port *port)
61 {
62 struct cxl_hdm *cxlhdm;
63 int rc;
64
65 rc = devm_cxl_port_enumerate_dports(port);
66 if (rc < 0)
67 return rc;
68
69 cxlhdm = devm_cxl_setup_hdm(port, NULL);
70 if (!IS_ERR(cxlhdm))
71 return devm_cxl_enumerate_decoders(cxlhdm, NULL);
72
73 if (PTR_ERR(cxlhdm) != -ENODEV) {
74 dev_err(&port->dev, "Failed to map HDM decoder capability\n");
75 return PTR_ERR(cxlhdm);
76 }
77
78 if (rc == 1) {
79 dev_dbg(&port->dev, "Fallback to passthrough decoder\n");
80 return devm_cxl_add_passthrough_decoder(port);
81 }
82
83 dev_err(&port->dev, "HDM decoder capability not found\n");
84 return -ENXIO;
85 }
86
cxl_endpoint_port_probe(struct cxl_port * port)87 static int cxl_endpoint_port_probe(struct cxl_port *port)
88 {
89 struct cxl_endpoint_dvsec_info info = { .port = port };
90 struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
91 struct cxl_dev_state *cxlds = cxlmd->cxlds;
92 struct cxl_hdm *cxlhdm;
93 struct cxl_port *root;
94 int rc;
95
96 rc = cxl_dvsec_rr_decode(cxlds->dev, cxlds->cxl_dvsec, &info);
97 if (rc < 0)
98 return rc;
99
100 cxlhdm = devm_cxl_setup_hdm(port, &info);
101 if (IS_ERR(cxlhdm)) {
102 if (PTR_ERR(cxlhdm) == -ENODEV)
103 dev_err(&port->dev, "HDM decoder registers not found\n");
104 return PTR_ERR(cxlhdm);
105 }
106
107 /* Cache the data early to ensure is_visible() works */
108 read_cdat_data(port);
109
110 get_device(&cxlmd->dev);
111 rc = devm_add_action_or_reset(&port->dev, schedule_detach, cxlmd);
112 if (rc)
113 return rc;
114
115 rc = cxl_hdm_decode_init(cxlds, cxlhdm, &info);
116 if (rc)
117 return rc;
118
119 rc = devm_cxl_enumerate_decoders(cxlhdm, &info);
120 if (rc)
121 return rc;
122
123 /*
124 * This can't fail in practice as CXL root exit unregisters all
125 * descendant ports and that in turn synchronizes with cxl_port_probe()
126 */
127 root = find_cxl_root(port);
128
129 /*
130 * Now that all endpoint decoders are successfully enumerated, try to
131 * assemble regions from committed decoders
132 */
133 device_for_each_child(&port->dev, root, discover_region);
134 put_device(&root->dev);
135
136 return 0;
137 }
138
cxl_port_probe(struct device * dev)139 static int cxl_port_probe(struct device *dev)
140 {
141 struct cxl_port *port = to_cxl_port(dev);
142
143 if (is_cxl_endpoint(port))
144 return cxl_endpoint_port_probe(port);
145 return cxl_switch_port_probe(port);
146 }
147
CDAT_read(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buf,loff_t offset,size_t count)148 static ssize_t CDAT_read(struct file *filp, struct kobject *kobj,
149 struct bin_attribute *bin_attr, char *buf,
150 loff_t offset, size_t count)
151 {
152 struct device *dev = kobj_to_dev(kobj);
153 struct cxl_port *port = to_cxl_port(dev);
154
155 if (!port->cdat_available)
156 return -ENXIO;
157
158 if (!port->cdat.table)
159 return 0;
160
161 return memory_read_from_buffer(buf, count, &offset,
162 port->cdat.table,
163 port->cdat.length);
164 }
165
166 static BIN_ATTR_ADMIN_RO(CDAT, 0);
167
cxl_port_bin_attr_is_visible(struct kobject * kobj,struct bin_attribute * attr,int i)168 static umode_t cxl_port_bin_attr_is_visible(struct kobject *kobj,
169 struct bin_attribute *attr, int i)
170 {
171 struct device *dev = kobj_to_dev(kobj);
172 struct cxl_port *port = to_cxl_port(dev);
173
174 if ((attr == &bin_attr_CDAT) && port->cdat_available)
175 return attr->attr.mode;
176
177 return 0;
178 }
179
180 static struct bin_attribute *cxl_cdat_bin_attributes[] = {
181 &bin_attr_CDAT,
182 NULL,
183 };
184
185 static struct attribute_group cxl_cdat_attribute_group = {
186 .bin_attrs = cxl_cdat_bin_attributes,
187 .is_bin_visible = cxl_port_bin_attr_is_visible,
188 };
189
190 static const struct attribute_group *cxl_port_attribute_groups[] = {
191 &cxl_cdat_attribute_group,
192 NULL,
193 };
194
195 static struct cxl_driver cxl_port_driver = {
196 .name = "cxl_port",
197 .probe = cxl_port_probe,
198 .id = CXL_DEVICE_PORT,
199 .drv = {
200 .dev_groups = cxl_port_attribute_groups,
201 },
202 };
203
204 module_cxl_driver(cxl_port_driver);
205 MODULE_LICENSE("GPL v2");
206 MODULE_IMPORT_NS(CXL);
207 MODULE_ALIAS_CXL(CXL_DEVICE_PORT);
208
