1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright(c) 2021 Intel Corporation. All rights reserved. */
3 #include <linux/platform_device.h>
4 #include <linux/module.h>
5 #include <linux/device.h>
6 #include <linux/kernel.h>
7 #include <linux/acpi.h>
8 #include <linux/pci.h>
9 #include <asm/div64.h>
10 #include "cxlpci.h"
11 #include "cxl.h"
12
13 #define CXL_RCRB_SIZE SZ_8K
14
15 struct cxl_cxims_data {
16 int nr_maps;
17 u64 xormaps[] __counted_by(nr_maps);
18 };
19
20 /*
21 * Find a targets entry (n) in the host bridge interleave list.
22 * CXL Specification 3.0 Table 9-22
23 */
cxl_xor_calc_n(u64 hpa,struct cxl_cxims_data * cximsd,int iw,int ig)24 static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw,
25 int ig)
26 {
27 int i = 0, n = 0;
28 u8 eiw;
29
30 /* IW: 2,4,6,8,12,16 begin building 'n' using xormaps */
31 if (iw != 3) {
32 for (i = 0; i < cximsd->nr_maps; i++)
33 n |= (hweight64(hpa & cximsd->xormaps[i]) & 1) << i;
34 }
35 /* IW: 3,6,12 add a modulo calculation to 'n' */
36 if (!is_power_of_2(iw)) {
37 if (ways_to_eiw(iw, &eiw))
38 return -1;
39 hpa &= GENMASK_ULL(51, eiw + ig);
40 n |= do_div(hpa, 3) << i;
41 }
42 return n;
43 }
44
cxl_hb_xor(struct cxl_root_decoder * cxlrd,int pos)45 static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos)
46 {
47 struct cxl_cxims_data *cximsd = cxlrd->platform_data;
48 struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd;
49 struct cxl_decoder *cxld = &cxlsd->cxld;
50 int ig = cxld->interleave_granularity;
51 int iw = cxld->interleave_ways;
52 int n = 0;
53 u64 hpa;
54
55 if (dev_WARN_ONCE(&cxld->dev,
56 cxld->interleave_ways != cxlsd->nr_targets,
57 "misconfigured root decoder\n"))
58 return NULL;
59
60 hpa = cxlrd->res->start + pos * ig;
61
62 /* Entry (n) is 0 for no interleave (iw == 1) */
63 if (iw != 1)
64 n = cxl_xor_calc_n(hpa, cximsd, iw, ig);
65
66 if (n < 0)
67 return NULL;
68
69 return cxlrd->cxlsd.target[n];
70 }
71
72 struct cxl_cxims_context {
73 struct device *dev;
74 struct cxl_root_decoder *cxlrd;
75 };
76
cxl_parse_cxims(union acpi_subtable_headers * header,void * arg,const unsigned long end)77 static int cxl_parse_cxims(union acpi_subtable_headers *header, void *arg,
78 const unsigned long end)
79 {
80 struct acpi_cedt_cxims *cxims = (struct acpi_cedt_cxims *)header;
81 struct cxl_cxims_context *ctx = arg;
82 struct cxl_root_decoder *cxlrd = ctx->cxlrd;
83 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
84 struct device *dev = ctx->dev;
85 struct cxl_cxims_data *cximsd;
86 unsigned int hbig, nr_maps;
87 int rc;
88
89 rc = eig_to_granularity(cxims->hbig, &hbig);
90 if (rc)
91 return rc;
92
93 /* Does this CXIMS entry apply to the given CXL Window? */
94 if (hbig != cxld->interleave_granularity)
95 return 0;
96
97 /* IW 1,3 do not use xormaps and skip this parsing entirely */
98 if (is_power_of_2(cxld->interleave_ways))
99 /* 2, 4, 8, 16 way */
100 nr_maps = ilog2(cxld->interleave_ways);
101 else
102 /* 6, 12 way */
103 nr_maps = ilog2(cxld->interleave_ways / 3);
104
105 if (cxims->nr_xormaps < nr_maps) {
106 dev_dbg(dev, "CXIMS nr_xormaps[%d] expected[%d]\n",
107 cxims->nr_xormaps, nr_maps);
108 return -ENXIO;
109 }
110
111 cximsd = devm_kzalloc(dev, struct_size(cximsd, xormaps, nr_maps),
112 GFP_KERNEL);
113 if (!cximsd)
114 return -ENOMEM;
115 cximsd->nr_maps = nr_maps;
116 memcpy(cximsd->xormaps, cxims->xormap_list,
117 nr_maps * sizeof(*cximsd->xormaps));
118 cxlrd->platform_data = cximsd;
119
120 return 0;
121 }
122
cfmws_to_decoder_flags(int restrictions)123 static unsigned long cfmws_to_decoder_flags(int restrictions)
124 {
125 unsigned long flags = CXL_DECODER_F_ENABLE;
126
127 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2)
128 flags |= CXL_DECODER_F_TYPE2;
129 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3)
130 flags |= CXL_DECODER_F_TYPE3;
131 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE)
132 flags |= CXL_DECODER_F_RAM;
133 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM)
134 flags |= CXL_DECODER_F_PMEM;
135 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED)
136 flags |= CXL_DECODER_F_LOCK;
137
138 return flags;
139 }
140
cxl_acpi_cfmws_verify(struct device * dev,struct acpi_cedt_cfmws * cfmws)141 static int cxl_acpi_cfmws_verify(struct device *dev,
142 struct acpi_cedt_cfmws *cfmws)
143 {
144 int rc, expected_len;
145 unsigned int ways;
146
147 if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO &&
148 cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
149 dev_err(dev, "CFMWS Unknown Interleave Arithmetic: %d\n",
150 cfmws->interleave_arithmetic);
151 return -EINVAL;
152 }
153
154 if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) {
155 dev_err(dev, "CFMWS Base HPA not 256MB aligned\n");
156 return -EINVAL;
157 }
158
159 if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) {
160 dev_err(dev, "CFMWS Window Size not 256MB aligned\n");
161 return -EINVAL;
162 }
163
164 rc = eiw_to_ways(cfmws->interleave_ways, &ways);
165 if (rc) {
166 dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n",
167 cfmws->interleave_ways);
168 return -EINVAL;
169 }
170
171 expected_len = struct_size(cfmws, interleave_targets, ways);
172
173 if (cfmws->header.length < expected_len) {
174 dev_err(dev, "CFMWS length %d less than expected %d\n",
175 cfmws->header.length, expected_len);
176 return -EINVAL;
177 }
178
179 if (cfmws->header.length > expected_len)
180 dev_dbg(dev, "CFMWS length %d greater than expected %d\n",
181 cfmws->header.length, expected_len);
182
183 return 0;
184 }
185
186 /*
187 * Note, @dev must be the first member, see 'struct cxl_chbs_context'
188 * and mock_acpi_table_parse_cedt()
189 */
190 struct cxl_cfmws_context {
191 struct device *dev;
192 struct cxl_port *root_port;
193 struct resource *cxl_res;
194 int id;
195 };
196
cxl_parse_cfmws(union acpi_subtable_headers * header,void * arg,const unsigned long end)197 static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
198 const unsigned long end)
199 {
200 int target_map[CXL_DECODER_MAX_INTERLEAVE];
201 struct cxl_cfmws_context *ctx = arg;
202 struct cxl_port *root_port = ctx->root_port;
203 struct resource *cxl_res = ctx->cxl_res;
204 struct cxl_cxims_context cxims_ctx;
205 struct cxl_root_decoder *cxlrd;
206 struct device *dev = ctx->dev;
207 struct acpi_cedt_cfmws *cfmws;
208 cxl_calc_hb_fn cxl_calc_hb;
209 struct cxl_decoder *cxld;
210 unsigned int ways, i, ig;
211 struct resource *res;
212 int rc;
213
214 cfmws = (struct acpi_cedt_cfmws *) header;
215
216 rc = cxl_acpi_cfmws_verify(dev, cfmws);
217 if (rc) {
218 dev_err(dev, "CFMWS range %#llx-%#llx not registered\n",
219 cfmws->base_hpa,
220 cfmws->base_hpa + cfmws->window_size - 1);
221 return 0;
222 }
223
224 rc = eiw_to_ways(cfmws->interleave_ways, &ways);
225 if (rc)
226 return rc;
227 rc = eig_to_granularity(cfmws->granularity, &ig);
228 if (rc)
229 return rc;
230 for (i = 0; i < ways; i++)
231 target_map[i] = cfmws->interleave_targets[i];
232
233 res = kzalloc(sizeof(*res), GFP_KERNEL);
234 if (!res)
235 return -ENOMEM;
236
237 res->name = kasprintf(GFP_KERNEL, "CXL Window %d", ctx->id++);
238 if (!res->name)
239 goto err_name;
240
241 res->start = cfmws->base_hpa;
242 res->end = cfmws->base_hpa + cfmws->window_size - 1;
243 res->flags = IORESOURCE_MEM;
244
245 /* add to the local resource tracking to establish a sort order */
246 rc = insert_resource(cxl_res, res);
247 if (rc)
248 goto err_insert;
249
250 if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_MODULO)
251 cxl_calc_hb = cxl_hb_modulo;
252 else
253 cxl_calc_hb = cxl_hb_xor;
254
255 cxlrd = cxl_root_decoder_alloc(root_port, ways, cxl_calc_hb);
256 if (IS_ERR(cxlrd))
257 return 0;
258
259 cxld = &cxlrd->cxlsd.cxld;
260 cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
261 cxld->target_type = CXL_DECODER_HOSTONLYMEM;
262 cxld->hpa_range = (struct range) {
263 .start = res->start,
264 .end = res->end,
265 };
266 cxld->interleave_ways = ways;
267 /*
268 * Minimize the x1 granularity to advertise support for any
269 * valid region granularity
270 */
271 if (ways == 1)
272 ig = CXL_DECODER_MIN_GRANULARITY;
273 cxld->interleave_granularity = ig;
274
275 if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
276 if (ways != 1 && ways != 3) {
277 cxims_ctx = (struct cxl_cxims_context) {
278 .dev = dev,
279 .cxlrd = cxlrd,
280 };
281 rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CXIMS,
282 cxl_parse_cxims, &cxims_ctx);
283 if (rc < 0)
284 goto err_xormap;
285 if (!cxlrd->platform_data) {
286 dev_err(dev, "No CXIMS for HBIG %u\n", ig);
287 rc = -EINVAL;
288 goto err_xormap;
289 }
290 }
291 }
292 rc = cxl_decoder_add(cxld, target_map);
293 err_xormap:
294 if (rc)
295 put_device(&cxld->dev);
296 else
297 rc = cxl_decoder_autoremove(dev, cxld);
298 if (rc) {
299 dev_err(dev, "Failed to add decode range: %pr", res);
300 return rc;
301 }
302 dev_dbg(dev, "add: %s node: %d range [%#llx - %#llx]\n",
303 dev_name(&cxld->dev),
304 phys_to_target_node(cxld->hpa_range.start),
305 cxld->hpa_range.start, cxld->hpa_range.end);
306
307 return 0;
308
309 err_insert:
310 kfree(res->name);
311 err_name:
312 kfree(res);
313 return -ENOMEM;
314 }
315
to_cxl_host_bridge(struct device * host,struct device * dev)316 __mock struct acpi_device *to_cxl_host_bridge(struct device *host,
317 struct device *dev)
318 {
319 struct acpi_device *adev = to_acpi_device(dev);
320
321 if (!acpi_pci_find_root(adev->handle))
322 return NULL;
323
324 if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0)
325 return adev;
326 return NULL;
327 }
328
329 /* Note, @dev is used by mock_acpi_table_parse_cedt() */
330 struct cxl_chbs_context {
331 struct device *dev;
332 unsigned long long uid;
333 resource_size_t base;
334 u32 cxl_version;
335 };
336
cxl_get_chbs_iter(union acpi_subtable_headers * header,void * arg,const unsigned long end)337 static int cxl_get_chbs_iter(union acpi_subtable_headers *header, void *arg,
338 const unsigned long end)
339 {
340 struct cxl_chbs_context *ctx = arg;
341 struct acpi_cedt_chbs *chbs;
342
343 if (ctx->base != CXL_RESOURCE_NONE)
344 return 0;
345
346 chbs = (struct acpi_cedt_chbs *) header;
347
348 if (ctx->uid != chbs->uid)
349 return 0;
350
351 ctx->cxl_version = chbs->cxl_version;
352 if (!chbs->base)
353 return 0;
354
355 if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11 &&
356 chbs->length != CXL_RCRB_SIZE)
357 return 0;
358
359 ctx->base = chbs->base;
360
361 return 0;
362 }
363
cxl_get_chbs(struct device * dev,struct acpi_device * hb,struct cxl_chbs_context * ctx)364 static int cxl_get_chbs(struct device *dev, struct acpi_device *hb,
365 struct cxl_chbs_context *ctx)
366 {
367 unsigned long long uid;
368 int rc;
369
370 rc = acpi_evaluate_integer(hb->handle, METHOD_NAME__UID, NULL, &uid);
371 if (rc != AE_OK) {
372 dev_err(dev, "unable to retrieve _UID\n");
373 return -ENOENT;
374 }
375
376 dev_dbg(dev, "UID found: %lld\n", uid);
377 *ctx = (struct cxl_chbs_context) {
378 .dev = dev,
379 .uid = uid,
380 .base = CXL_RESOURCE_NONE,
381 .cxl_version = UINT_MAX,
382 };
383
384 acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbs_iter, ctx);
385
386 return 0;
387 }
388
add_host_bridge_dport(struct device * match,void * arg)389 static int add_host_bridge_dport(struct device *match, void *arg)
390 {
391 acpi_status rc;
392 struct device *bridge;
393 struct cxl_dport *dport;
394 struct cxl_chbs_context ctx;
395 struct acpi_pci_root *pci_root;
396 struct cxl_port *root_port = arg;
397 struct device *host = root_port->dev.parent;
398 struct acpi_device *hb = to_cxl_host_bridge(host, match);
399
400 if (!hb)
401 return 0;
402
403 rc = cxl_get_chbs(match, hb, &ctx);
404 if (rc)
405 return rc;
406
407 if (ctx.cxl_version == UINT_MAX) {
408 dev_warn(match, "No CHBS found for Host Bridge (UID %lld)\n",
409 ctx.uid);
410 return 0;
411 }
412
413 if (ctx.base == CXL_RESOURCE_NONE) {
414 dev_warn(match, "CHBS invalid for Host Bridge (UID %lld)\n",
415 ctx.uid);
416 return 0;
417 }
418
419 pci_root = acpi_pci_find_root(hb->handle);
420 bridge = pci_root->bus->bridge;
421
422 /*
423 * In RCH mode, bind the component regs base to the dport. In
424 * VH mode it will be bound to the CXL host bridge's port
425 * object later in add_host_bridge_uport().
426 */
427 if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
428 dev_dbg(match, "RCRB found for UID %lld: %pa\n", ctx.uid,
429 &ctx.base);
430 dport = devm_cxl_add_rch_dport(root_port, bridge, ctx.uid,
431 ctx.base);
432 } else {
433 dport = devm_cxl_add_dport(root_port, bridge, ctx.uid,
434 CXL_RESOURCE_NONE);
435 }
436
437 if (IS_ERR(dport))
438 return PTR_ERR(dport);
439
440 return 0;
441 }
442
443 /*
444 * A host bridge is a dport to a CFMWS decode and it is a uport to the
445 * dport (PCIe Root Ports) in the host bridge.
446 */
add_host_bridge_uport(struct device * match,void * arg)447 static int add_host_bridge_uport(struct device *match, void *arg)
448 {
449 struct cxl_port *root_port = arg;
450 struct device *host = root_port->dev.parent;
451 struct acpi_device *hb = to_cxl_host_bridge(host, match);
452 struct acpi_pci_root *pci_root;
453 struct cxl_dport *dport;
454 struct cxl_port *port;
455 struct device *bridge;
456 struct cxl_chbs_context ctx;
457 resource_size_t component_reg_phys;
458 int rc;
459
460 if (!hb)
461 return 0;
462
463 pci_root = acpi_pci_find_root(hb->handle);
464 bridge = pci_root->bus->bridge;
465 dport = cxl_find_dport_by_dev(root_port, bridge);
466 if (!dport) {
467 dev_dbg(host, "host bridge expected and not found\n");
468 return 0;
469 }
470
471 if (dport->rch) {
472 dev_info(bridge, "host supports CXL (restricted)\n");
473 return 0;
474 }
475
476 rc = cxl_get_chbs(match, hb, &ctx);
477 if (rc)
478 return rc;
479
480 if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
481 dev_warn(bridge,
482 "CXL CHBS version mismatch, skip port registration\n");
483 return 0;
484 }
485
486 component_reg_phys = ctx.base;
487 if (component_reg_phys != CXL_RESOURCE_NONE)
488 dev_dbg(match, "CHBCR found for UID %lld: %pa\n",
489 ctx.uid, &component_reg_phys);
490
491 rc = devm_cxl_register_pci_bus(host, bridge, pci_root->bus);
492 if (rc)
493 return rc;
494
495 port = devm_cxl_add_port(host, bridge, component_reg_phys, dport);
496 if (IS_ERR(port))
497 return PTR_ERR(port);
498
499 dev_info(bridge, "host supports CXL\n");
500
501 return 0;
502 }
503
add_root_nvdimm_bridge(struct device * match,void * data)504 static int add_root_nvdimm_bridge(struct device *match, void *data)
505 {
506 struct cxl_decoder *cxld;
507 struct cxl_port *root_port = data;
508 struct cxl_nvdimm_bridge *cxl_nvb;
509 struct device *host = root_port->dev.parent;
510
511 if (!is_root_decoder(match))
512 return 0;
513
514 cxld = to_cxl_decoder(match);
515 if (!(cxld->flags & CXL_DECODER_F_PMEM))
516 return 0;
517
518 cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port);
519 if (IS_ERR(cxl_nvb)) {
520 dev_dbg(host, "failed to register pmem\n");
521 return PTR_ERR(cxl_nvb);
522 }
523 dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev),
524 dev_name(&cxl_nvb->dev));
525 return 1;
526 }
527
528 static struct lock_class_key cxl_root_key;
529
cxl_acpi_lock_reset_class(void * dev)530 static void cxl_acpi_lock_reset_class(void *dev)
531 {
532 device_lock_reset_class(dev);
533 }
534
del_cxl_resource(struct resource * res)535 static void del_cxl_resource(struct resource *res)
536 {
537 kfree(res->name);
538 kfree(res);
539 }
540
cxl_set_public_resource(struct resource * priv,struct resource * pub)541 static void cxl_set_public_resource(struct resource *priv, struct resource *pub)
542 {
543 priv->desc = (unsigned long) pub;
544 }
545
cxl_get_public_resource(struct resource * priv)546 static struct resource *cxl_get_public_resource(struct resource *priv)
547 {
548 return (struct resource *) priv->desc;
549 }
550
remove_cxl_resources(void * data)551 static void remove_cxl_resources(void *data)
552 {
553 struct resource *res, *next, *cxl = data;
554
555 for (res = cxl->child; res; res = next) {
556 struct resource *victim = cxl_get_public_resource(res);
557
558 next = res->sibling;
559 remove_resource(res);
560
561 if (victim) {
562 remove_resource(victim);
563 kfree(victim);
564 }
565
566 del_cxl_resource(res);
567 }
568 }
569
570 /**
571 * add_cxl_resources() - reflect CXL fixed memory windows in iomem_resource
572 * @cxl_res: A standalone resource tree where each CXL window is a sibling
573 *
574 * Walk each CXL window in @cxl_res and add it to iomem_resource potentially
575 * expanding its boundaries to ensure that any conflicting resources become
576 * children. If a window is expanded it may then conflict with a another window
577 * entry and require the window to be truncated or trimmed. Consider this
578 * situation:
579 *
580 * |-- "CXL Window 0" --||----- "CXL Window 1" -----|
581 * |--------------- "System RAM" -------------|
582 *
583 * ...where platform firmware has established as System RAM resource across 2
584 * windows, but has left some portion of window 1 for dynamic CXL region
585 * provisioning. In this case "Window 0" will span the entirety of the "System
586 * RAM" span, and "CXL Window 1" is truncated to the remaining tail past the end
587 * of that "System RAM" resource.
588 */
add_cxl_resources(struct resource * cxl_res)589 static int add_cxl_resources(struct resource *cxl_res)
590 {
591 struct resource *res, *new, *next;
592
593 for (res = cxl_res->child; res; res = next) {
594 new = kzalloc(sizeof(*new), GFP_KERNEL);
595 if (!new)
596 return -ENOMEM;
597 new->name = res->name;
598 new->start = res->start;
599 new->end = res->end;
600 new->flags = IORESOURCE_MEM;
601 new->desc = IORES_DESC_CXL;
602
603 /*
604 * Record the public resource in the private cxl_res tree for
605 * later removal.
606 */
607 cxl_set_public_resource(res, new);
608
609 insert_resource_expand_to_fit(&iomem_resource, new);
610
611 next = res->sibling;
612 while (next && resource_overlaps(new, next)) {
613 if (resource_contains(new, next)) {
614 struct resource *_next = next->sibling;
615
616 remove_resource(next);
617 del_cxl_resource(next);
618 next = _next;
619 } else
620 next->start = new->end + 1;
621 }
622 }
623 return 0;
624 }
625
pair_cxl_resource(struct device * dev,void * data)626 static int pair_cxl_resource(struct device *dev, void *data)
627 {
628 struct resource *cxl_res = data;
629 struct resource *p;
630
631 if (!is_root_decoder(dev))
632 return 0;
633
634 for (p = cxl_res->child; p; p = p->sibling) {
635 struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev);
636 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
637 struct resource res = {
638 .start = cxld->hpa_range.start,
639 .end = cxld->hpa_range.end,
640 .flags = IORESOURCE_MEM,
641 };
642
643 if (resource_contains(p, &res)) {
644 cxlrd->res = cxl_get_public_resource(p);
645 break;
646 }
647 }
648
649 return 0;
650 }
651
cxl_acpi_probe(struct platform_device * pdev)652 static int cxl_acpi_probe(struct platform_device *pdev)
653 {
654 int rc;
655 struct resource *cxl_res;
656 struct cxl_port *root_port;
657 struct device *host = &pdev->dev;
658 struct acpi_device *adev = ACPI_COMPANION(host);
659 struct cxl_cfmws_context ctx;
660
661 device_lock_set_class(&pdev->dev, &cxl_root_key);
662 rc = devm_add_action_or_reset(&pdev->dev, cxl_acpi_lock_reset_class,
663 &pdev->dev);
664 if (rc)
665 return rc;
666
667 cxl_res = devm_kzalloc(host, sizeof(*cxl_res), GFP_KERNEL);
668 if (!cxl_res)
669 return -ENOMEM;
670 cxl_res->name = "CXL mem";
671 cxl_res->start = 0;
672 cxl_res->end = -1;
673 cxl_res->flags = IORESOURCE_MEM;
674
675 root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);
676 if (IS_ERR(root_port))
677 return PTR_ERR(root_port);
678
679 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
680 add_host_bridge_dport);
681 if (rc < 0)
682 return rc;
683
684 rc = devm_add_action_or_reset(host, remove_cxl_resources, cxl_res);
685 if (rc)
686 return rc;
687
688 ctx = (struct cxl_cfmws_context) {
689 .dev = host,
690 .root_port = root_port,
691 .cxl_res = cxl_res,
692 };
693 rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);
694 if (rc < 0)
695 return -ENXIO;
696
697 rc = add_cxl_resources(cxl_res);
698 if (rc)
699 return rc;
700
701 /*
702 * Populate the root decoders with their related iomem resource,
703 * if present
704 */
705 device_for_each_child(&root_port->dev, cxl_res, pair_cxl_resource);
706
707 /*
708 * Root level scanned with host-bridge as dports, now scan host-bridges
709 * for their role as CXL uports to their CXL-capable PCIe Root Ports.
710 */
711 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
712 add_host_bridge_uport);
713 if (rc < 0)
714 return rc;
715
716 if (IS_ENABLED(CONFIG_CXL_PMEM))
717 rc = device_for_each_child(&root_port->dev, root_port,
718 add_root_nvdimm_bridge);
719 if (rc < 0)
720 return rc;
721
722 /* In case PCI is scanned before ACPI re-trigger memdev attach */
723 cxl_bus_rescan();
724 return 0;
725 }
726
727 static const struct acpi_device_id cxl_acpi_ids[] = {
728 { "ACPI0017" },
729 { },
730 };
731 MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids);
732
733 static const struct platform_device_id cxl_test_ids[] = {
734 { "cxl_acpi" },
735 { },
736 };
737 MODULE_DEVICE_TABLE(platform, cxl_test_ids);
738
739 static struct platform_driver cxl_acpi_driver = {
740 .probe = cxl_acpi_probe,
741 .driver = {
742 .name = KBUILD_MODNAME,
743 .acpi_match_table = cxl_acpi_ids,
744 },
745 .id_table = cxl_test_ids,
746 };
747
cxl_acpi_init(void)748 static int __init cxl_acpi_init(void)
749 {
750 return platform_driver_register(&cxl_acpi_driver);
751 }
752
cxl_acpi_exit(void)753 static void __exit cxl_acpi_exit(void)
754 {
755 platform_driver_unregister(&cxl_acpi_driver);
756 cxl_bus_drain();
757 }
758
759 /* load before dax_hmem sees 'Soft Reserved' CXL ranges */
760 subsys_initcall(cxl_acpi_init);
761 module_exit(cxl_acpi_exit);
762 MODULE_LICENSE("GPL v2");
763 MODULE_IMPORT_NS(CXL);
764 MODULE_IMPORT_NS(ACPI);
765
