1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4  */
5 
6 #include <linux/clk-provider.h>
7 #include <linux/mod_devicetable.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11 
12 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
13 
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-regmap-mux.h"
20 #include "clk-regmap-phy-mux.h"
21 #include "reset.h"
22 
23 enum {
24 	DT_XO,
25 	DT_SLEEP_CLK,
26 	DT_PCIE_2LANE_PHY_PIPE_CLK,
27 	DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
28 	DT_USB_PCIE_WRAPPER_PIPE_CLK,
29 };
30 
31 enum {
32 	P_PCIE3X2_PIPE,
33 	P_PCIE3X1_0_PIPE,
34 	P_PCIE3X1_1_PIPE,
35 	P_USB3PHY_0_PIPE,
36 	P_CORE_BI_PLL_TEST_SE,
37 	P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,
38 	P_GPLL0_OUT_AUX,
39 	P_GPLL0_OUT_MAIN,
40 	P_GPLL2_OUT_AUX,
41 	P_GPLL2_OUT_MAIN,
42 	P_GPLL4_OUT_AUX,
43 	P_GPLL4_OUT_MAIN,
44 	P_SLEEP_CLK,
45 	P_XO,
46 };
47 
48 static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
49 
50 static struct clk_alpha_pll gpll0_main = {
51 	.offset = 0x20000,
52 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
53 	.clkr = {
54 		.enable_reg = 0xb000,
55 		.enable_mask = BIT(0),
56 		.hw.init = &(const struct clk_init_data) {
57 			.name = "gpll0_main",
58 			.parent_data = &gcc_parent_data_xo,
59 			.num_parents = 1,
60 			.ops = &clk_alpha_pll_stromer_ops,
61 		},
62 	},
63 };
64 
65 static struct clk_fixed_factor gpll0_div2 = {
66 	.mult = 1,
67 	.div = 2,
68 	.hw.init = &(struct clk_init_data) {
69 		.name = "gpll0_div2",
70 		.parent_hws = (const struct clk_hw *[]) {
71 				&gpll0_main.clkr.hw },
72 		.num_parents = 1,
73 		.ops = &clk_fixed_factor_ops,
74 		.flags = CLK_SET_RATE_PARENT,
75 	},
76 };
77 
78 static struct clk_alpha_pll_postdiv gpll0 = {
79 	.offset = 0x20000,
80 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
81 	.width = 4,
82 	.clkr.hw.init = &(struct clk_init_data) {
83 		.name = "gpll0",
84 		.parent_hws = (const struct clk_hw *[]) {
85 				&gpll0_main.clkr.hw },
86 		.num_parents = 1,
87 		.ops = &clk_alpha_pll_postdiv_ro_ops,
88 		.flags = CLK_SET_RATE_PARENT,
89 	},
90 };
91 
92 static struct clk_alpha_pll gpll2_main = {
93 	.offset = 0x21000,
94 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
95 	.clkr = {
96 		.enable_reg = 0xb000,
97 		.enable_mask = BIT(1),
98 		.hw.init = &(const struct clk_init_data) {
99 			.name = "gpll2",
100 			.parent_data = &gcc_parent_data_xo,
101 			.num_parents = 1,
102 			.ops = &clk_alpha_pll_stromer_ops,
103 		},
104 	},
105 };
106 
107 static struct clk_alpha_pll_postdiv gpll2 = {
108 	.offset = 0x21000,
109 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
110 	.width = 4,
111 	.clkr.hw.init = &(struct clk_init_data) {
112 		.name = "gpll2_main",
113 		.parent_hws = (const struct clk_hw *[]) {
114 				&gpll2_main.clkr.hw },
115 		.num_parents = 1,
116 		.ops = &clk_alpha_pll_postdiv_ro_ops,
117 		.flags = CLK_SET_RATE_PARENT,
118 	},
119 };
120 
121 static struct clk_alpha_pll gpll4_main = {
122 	.offset = 0x22000,
123 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
124 	.clkr = {
125 		.enable_reg = 0xb000,
126 		.enable_mask = BIT(2),
127 		.hw.init = &(const struct clk_init_data) {
128 			.name = "gpll4_main",
129 			.parent_data = &gcc_parent_data_xo,
130 			.num_parents = 1,
131 			.ops = &clk_alpha_pll_stromer_ops,
132 			/*
133 			 * There are no consumers for this GPLL in kernel yet,
134 			 * (will be added soon), so the clock framework
135 			 * disables this source. But some of the clocks
136 			 * initialized by boot loaders uses this source. So we
137 			 * need to keep this clock ON. Add the
138 			 * CLK_IGNORE_UNUSED flag so the clock will not be
139 			 * disabled. Once the consumer in kernel is added, we
140 			 * can get rid of this flag.
141 			 */
142 			.flags = CLK_IGNORE_UNUSED,
143 		},
144 	},
145 };
146 
147 static struct clk_alpha_pll_postdiv gpll4 = {
148 	.offset = 0x22000,
149 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
150 	.width = 4,
151 	.clkr.hw.init = &(struct clk_init_data) {
152 		.name = "gpll4",
153 		.parent_hws = (const struct clk_hw *[]) {
154 				&gpll4_main.clkr.hw },
155 		.num_parents = 1,
156 		.ops = &clk_alpha_pll_postdiv_ro_ops,
157 		.flags = CLK_SET_RATE_PARENT,
158 	},
159 };
160 
161 static const struct parent_map gcc_parent_map_xo[] = {
162 	{ P_XO, 0 },
163 };
164 
165 static const struct parent_map gcc_parent_map_0[] = {
166 	{ P_XO, 0 },
167 	{ P_GPLL0_OUT_MAIN, 1 },
168 	{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
169 };
170 
171 static const struct clk_parent_data gcc_parent_data_0[] = {
172 	{ .index = DT_XO },
173 	{ .hw = &gpll0.clkr.hw },
174 	{ .hw = &gpll0_div2.hw },
175 };
176 
177 static const struct parent_map gcc_parent_map_1[] = {
178 	{ P_XO, 0 },
179 	{ P_GPLL0_OUT_MAIN, 1 },
180 };
181 
182 static const struct clk_parent_data gcc_parent_data_1[] = {
183 	{ .index = DT_XO },
184 	{ .hw = &gpll0.clkr.hw },
185 };
186 
187 static const struct parent_map gcc_parent_map_2[] = {
188 	{ P_XO, 0 },
189 	{ P_GPLL0_OUT_MAIN, 1 },
190 	{ P_GPLL4_OUT_MAIN, 2 },
191 };
192 
193 static const struct clk_parent_data gcc_parent_data_2[] = {
194 	{ .index = DT_XO },
195 	{ .hw = &gpll0.clkr.hw },
196 	{ .hw = &gpll4.clkr.hw },
197 };
198 
199 static const struct parent_map gcc_parent_map_3[] = {
200 	{ P_XO, 0 },
201 	{ P_GPLL0_OUT_MAIN, 1 },
202 	{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
203 	{ P_SLEEP_CLK, 6 },
204 };
205 
206 static const struct clk_parent_data gcc_parent_data_3[] = {
207 	{ .index = DT_XO },
208 	{ .hw = &gpll0.clkr.hw },
209 	{ .hw = &gpll0_div2.hw },
210 	{ .index = DT_SLEEP_CLK },
211 };
212 
213 static const struct parent_map gcc_parent_map_4[] = {
214 	{ P_XO, 0 },
215 	{ P_GPLL4_OUT_MAIN, 1 },
216 	{ P_GPLL0_OUT_AUX, 2 },
217 	{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
218 };
219 
220 static const struct clk_parent_data gcc_parent_data_4[] = {
221 	{ .index = DT_XO },
222 	{ .hw = &gpll4.clkr.hw },
223 	{ .hw = &gpll0.clkr.hw },
224 	{ .hw = &gpll0_div2.hw },
225 };
226 
227 static const struct parent_map gcc_parent_map_5[] = {
228 	{ P_XO, 0 },
229 	{ P_GPLL0_OUT_MAIN, 1 },
230 	{ P_GPLL0_OUT_AUX, 2 },
231 	{ P_SLEEP_CLK, 6 },
232 };
233 
234 static const struct clk_parent_data gcc_parent_data_5[] = {
235 	{ .index = DT_XO },
236 	{ .hw = &gpll0.clkr.hw },
237 	{ .hw = &gpll0.clkr.hw },
238 	{ .index = DT_SLEEP_CLK },
239 };
240 
241 static const struct parent_map gcc_parent_map_6[] = {
242 	{ P_XO, 0 },
243 	{ P_GPLL0_OUT_MAIN, 1 },
244 	{ P_GPLL2_OUT_AUX, 2 },
245 	{ P_GPLL4_OUT_AUX, 3 },
246 	{ P_SLEEP_CLK, 6 },
247 };
248 
249 static const struct clk_parent_data gcc_parent_data_6[] = {
250 	{ .index = DT_XO },
251 	{ .hw = &gpll0.clkr.hw },
252 	{ .hw = &gpll2.clkr.hw },
253 	{ .hw = &gpll4.clkr.hw },
254 	{ .index = DT_SLEEP_CLK },
255 };
256 
257 static const struct parent_map gcc_parent_map_7[] = {
258 	{ P_XO, 0 },
259 	{ P_GPLL0_OUT_MAIN, 1 },
260 	{ P_GPLL2_OUT_AUX, 2 },
261 };
262 
263 static const struct clk_parent_data gcc_parent_data_7[] = {
264 	{ .index = DT_XO },
265 	{ .hw = &gpll0.clkr.hw },
266 	{ .hw = &gpll2.clkr.hw },
267 };
268 
269 static const struct parent_map gcc_parent_map_8[] = {
270 	{ P_XO, 0 },
271 	{ P_GPLL0_OUT_MAIN, 1 },
272 	{ P_GPLL2_OUT_MAIN, 2 },
273 	{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
274 };
275 
276 static const struct clk_parent_data gcc_parent_data_8[] = {
277 	{ .index = DT_XO },
278 	{ .hw = &gpll0.clkr.hw },
279 	{ .hw = &gpll2.clkr.hw },
280 	{ .hw = &gpll0_div2.hw },
281 };
282 
283 static const struct parent_map gcc_parent_map_9[] = {
284 	{ P_SLEEP_CLK, 6 },
285 };
286 
287 static const struct clk_parent_data gcc_parent_data_9[] = {
288 	{ .index = DT_SLEEP_CLK },
289 };
290 
291 static const struct parent_map gcc_parent_map_10[] = {
292 	{ P_XO, 0 },
293 	{ P_GPLL0_OUT_MAIN, 1 },
294 	{ P_GPLL4_OUT_MAIN, 2 },
295 	{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 3 },
296 };
297 
298 static const struct clk_parent_data gcc_parent_data_10[] = {
299 	{ .index = DT_XO },
300 	{ .hw = &gpll0.clkr.hw },
301 	{ .hw = &gpll4.clkr.hw },
302 	{ .hw = &gpll0_div2.hw },
303 };
304 
305 static const struct parent_map gcc_parent_map_11[] = {
306 	{ P_XO, 0 },
307 	{ P_GPLL0_OUT_AUX, 2 },
308 	{ P_SLEEP_CLK, 6 },
309 };
310 
311 static const struct clk_parent_data gcc_parent_data_11[] = {
312 	{ .index = DT_XO },
313 	{ .hw = &gpll0.clkr.hw },
314 	{ .index = DT_SLEEP_CLK },
315 };
316 
317 static const struct parent_map gcc_parent_map_12[] = {
318 	{ P_XO, 0 },
319 	{ P_GPLL4_OUT_AUX, 1 },
320 	{ P_GPLL0_OUT_MAIN, 3 },
321 	{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
322 };
323 
324 static const struct clk_parent_data gcc_parent_data_12[] = {
325 	{ .index = DT_XO },
326 	{ .hw = &gpll4.clkr.hw },
327 	{ .hw = &gpll0.clkr.hw },
328 	{ .hw = &gpll0_div2.hw },
329 };
330 
331 static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = {
332 	F(24000000, P_XO, 1, 0, 0),
333 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
334 	{ }
335 };
336 
337 static struct clk_rcg2 gcc_adss_pwm_clk_src = {
338 	.cmd_rcgr = 0x1c004,
339 	.mnd_width = 0,
340 	.hid_width = 5,
341 	.parent_map = gcc_parent_map_1,
342 	.freq_tbl = ftbl_gcc_adss_pwm_clk_src,
343 	.clkr.hw.init = &(const struct clk_init_data) {
344 		.name = "gcc_adss_pwm_clk_src",
345 		.parent_data = gcc_parent_data_1,
346 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
347 		.ops = &clk_rcg2_ops,
348 	},
349 };
350 
351 static const struct freq_tbl ftbl_gcc_apss_axi_clk_src[] = {
352 	F(480000000, P_GPLL4_OUT_AUX, 2.5, 0, 0),
353 	F(533333333, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
354 	{ }
355 };
356 
357 static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
358 	F(960000, P_XO, 1, 1, 25),
359 	F(4800000, P_XO, 5, 0, 0),
360 	F(9600000, P_XO, 2.5, 0, 0),
361 	F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
362 	F(24000000, P_XO, 1, 0, 0),
363 	F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
364 	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
365 	{ }
366 };
367 
368 static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = {
369 	.cmd_rcgr = 0x2004,
370 	.mnd_width = 8,
371 	.hid_width = 5,
372 	.parent_map = gcc_parent_map_0,
373 	.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
374 	.clkr.hw.init = &(const struct clk_init_data) {
375 		.name = "gcc_blsp1_qup1_spi_apps_clk_src",
376 		.parent_data = gcc_parent_data_0,
377 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
378 		.ops = &clk_rcg2_ops,
379 	},
380 };
381 
382 static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = {
383 	.cmd_rcgr = 0x3004,
384 	.mnd_width = 8,
385 	.hid_width = 5,
386 	.parent_map = gcc_parent_map_0,
387 	.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
388 	.clkr.hw.init = &(const struct clk_init_data) {
389 		.name = "gcc_blsp1_qup2_spi_apps_clk_src",
390 		.parent_data = gcc_parent_data_0,
391 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
392 		.ops = &clk_rcg2_ops,
393 	},
394 };
395 
396 static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = {
397 	.cmd_rcgr = 0x4004,
398 	.mnd_width = 8,
399 	.hid_width = 5,
400 	.parent_map = gcc_parent_map_0,
401 	.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
402 	.clkr.hw.init = &(const struct clk_init_data) {
403 		.name = "gcc_blsp1_qup3_spi_apps_clk_src",
404 		.parent_data = gcc_parent_data_0,
405 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
406 		.ops = &clk_rcg2_ops,
407 	},
408 };
409 
410 static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = {
411 	F(3686400, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 144, 15625),
412 	F(7372800, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 288, 15625),
413 	F(14745600, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 576, 15625),
414 	F(24000000, P_XO, 1, 0, 0),
415 	F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
416 	F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
417 	F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
418 	F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
419 	F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
420 	F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
421 	F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
422 	F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
423 	F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
424 	F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
425 	{ }
426 };
427 
428 static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = {
429 	.cmd_rcgr = 0x202c,
430 	.mnd_width = 16,
431 	.hid_width = 5,
432 	.parent_map = gcc_parent_map_0,
433 	.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
434 	.clkr.hw.init = &(const struct clk_init_data) {
435 		.name = "gcc_blsp1_uart1_apps_clk_src",
436 		.parent_data = gcc_parent_data_0,
437 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
438 		.ops = &clk_rcg2_ops,
439 	},
440 };
441 
442 static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = {
443 	.cmd_rcgr = 0x302c,
444 	.mnd_width = 16,
445 	.hid_width = 5,
446 	.parent_map = gcc_parent_map_0,
447 	.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
448 	.clkr.hw.init = &(const struct clk_init_data) {
449 		.name = "gcc_blsp1_uart2_apps_clk_src",
450 		.parent_data = gcc_parent_data_0,
451 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
452 		.ops = &clk_rcg2_ops,
453 	},
454 };
455 
456 static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = {
457 	.cmd_rcgr = 0x402c,
458 	.mnd_width = 16,
459 	.hid_width = 5,
460 	.parent_map = gcc_parent_map_0,
461 	.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
462 	.clkr.hw.init = &(const struct clk_init_data) {
463 		.name = "gcc_blsp1_uart3_apps_clk_src",
464 		.parent_data = gcc_parent_data_0,
465 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
466 		.ops = &clk_rcg2_ops,
467 	},
468 };
469 
470 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
471 	F(24000000, P_XO, 1, 0, 0),
472 	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
473 	{ }
474 };
475 
476 static struct clk_rcg2 gcc_gp1_clk_src = {
477 	.cmd_rcgr = 0x8004,
478 	.mnd_width = 8,
479 	.hid_width = 5,
480 	.parent_map = gcc_parent_map_3,
481 	.freq_tbl = ftbl_gcc_gp1_clk_src,
482 	.clkr.hw.init = &(const struct clk_init_data) {
483 		.name = "gcc_gp1_clk_src",
484 		.parent_data = gcc_parent_data_3,
485 		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
486 		.ops = &clk_rcg2_ops,
487 	},
488 };
489 
490 static struct clk_rcg2 gcc_gp2_clk_src = {
491 	.cmd_rcgr = 0x9004,
492 	.mnd_width = 8,
493 	.hid_width = 5,
494 	.parent_map = gcc_parent_map_3,
495 	.freq_tbl = ftbl_gcc_gp1_clk_src,
496 	.clkr.hw.init = &(const struct clk_init_data) {
497 		.name = "gcc_gp2_clk_src",
498 		.parent_data = gcc_parent_data_3,
499 		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
500 		.ops = &clk_rcg2_ops,
501 	},
502 };
503 
504 static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] = {
505 	F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
506 	{ }
507 };
508 
509 static struct clk_rcg2 gcc_lpass_sway_clk_src = {
510 	.cmd_rcgr = 0x27004,
511 	.mnd_width = 0,
512 	.hid_width = 5,
513 	.parent_map = gcc_parent_map_1,
514 	.freq_tbl = ftbl_gcc_lpass_sway_clk_src,
515 	.clkr.hw.init = &(const struct clk_init_data) {
516 		.name = "gcc_lpass_sway_clk_src",
517 		.parent_data = gcc_parent_data_1,
518 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
519 		.ops = &clk_rcg2_ops,
520 	},
521 };
522 
523 static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] = {
524 	F(24000000, P_XO, 1, 0, 0),
525 	{ }
526 };
527 
528 static struct clk_rcg2 gcc_nss_ts_clk_src = {
529 	.cmd_rcgr = 0x17088,
530 	.mnd_width = 0,
531 	.hid_width = 5,
532 	.parent_map = gcc_parent_map_xo,
533 	.freq_tbl = ftbl_gcc_nss_ts_clk_src,
534 	.clkr.hw.init = &(const struct clk_init_data) {
535 		.name = "gcc_nss_ts_clk_src",
536 		.parent_data = &gcc_parent_data_xo,
537 		.num_parents = 1,
538 		.ops = &clk_rcg2_ops,
539 	},
540 };
541 
542 static const struct freq_tbl ftbl_gcc_pcie3x1_0_axi_clk_src[] = {
543 	F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
544 	{ }
545 };
546 
547 static struct clk_rcg2 gcc_pcie3x1_0_axi_clk_src = {
548 	.cmd_rcgr = 0x29018,
549 	.mnd_width = 0,
550 	.hid_width = 5,
551 	.parent_map = gcc_parent_map_2,
552 	.freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
553 	.clkr.hw.init = &(const struct clk_init_data) {
554 		.name = "gcc_pcie3x1_0_axi_clk_src",
555 		.parent_data = gcc_parent_data_2,
556 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
557 		.ops = &clk_rcg2_ops,
558 	},
559 };
560 
561 static struct clk_rcg2 gcc_pcie3x1_0_rchg_clk_src = {
562 	.cmd_rcgr = 0x2907c,
563 	.hid_width = 5,
564 	.parent_map = gcc_parent_map_0,
565 	.freq_tbl = ftbl_gcc_adss_pwm_clk_src,
566 	.clkr.hw.init = &(const struct clk_init_data) {
567 		.name = "gcc_pcie3x1_0_rchg_clk_src",
568 		.parent_data = gcc_parent_data_0,
569 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
570 		.ops = &clk_rcg2_ops,
571 	},
572 };
573 
574 static struct clk_branch gcc_pcie3x1_0_rchg_clk = {
575 	.halt_reg = 0x2907c,
576 	.clkr = {
577 		.enable_reg = 0x2907c,
578 		.enable_mask = BIT(1),
579 		.hw.init = &(struct clk_init_data) {
580 			.name = "gcc_pcie3x1_0_rchg_clk",
581 			.parent_hws = (const struct clk_hw *[]) {
582 					&gcc_pcie3x1_0_rchg_clk_src.clkr.hw },
583 			.num_parents = 1,
584 			.flags = CLK_SET_RATE_PARENT,
585 			.ops = &clk_branch2_ops,
586 		},
587 	},
588 };
589 
590 static struct clk_rcg2 gcc_pcie3x1_1_axi_clk_src = {
591 	.cmd_rcgr = 0x2a004,
592 	.mnd_width = 0,
593 	.hid_width = 5,
594 	.parent_map = gcc_parent_map_2,
595 	.freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
596 	.clkr.hw.init = &(const struct clk_init_data) {
597 		.name = "gcc_pcie3x1_1_axi_clk_src",
598 		.parent_data = gcc_parent_data_2,
599 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
600 		.ops = &clk_rcg2_ops,
601 	},
602 };
603 
604 static struct clk_rcg2 gcc_pcie3x1_1_rchg_clk_src = {
605 	.cmd_rcgr = 0x2a078,
606 	.hid_width = 5,
607 	.parent_map = gcc_parent_map_0,
608 	.freq_tbl = ftbl_gcc_adss_pwm_clk_src,
609 	.clkr.hw.init = &(const struct clk_init_data) {
610 		.name = "gcc_pcie3x1_1_rchg_clk_src",
611 		.parent_data = gcc_parent_data_0,
612 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
613 		.ops = &clk_rcg2_ops,
614 	},
615 };
616 
617 static struct clk_branch gcc_pcie3x1_1_rchg_clk = {
618 	.halt_reg = 0x2a078,
619 	.clkr = {
620 		.enable_reg = 0x2a078,
621 		.enable_mask = BIT(1),
622 		.hw.init = &(struct clk_init_data) {
623 			.name = "gcc_pcie3x1_1_rchg_clk",
624 			.parent_hws = (const struct clk_hw *[]) {
625 					&gcc_pcie3x1_1_rchg_clk_src.clkr.hw },
626 			.num_parents = 1,
627 			.flags = CLK_SET_RATE_PARENT,
628 			.ops = &clk_branch2_ops,
629 		},
630 	},
631 };
632 
633 static const struct freq_tbl ftbl_gcc_pcie3x2_axi_m_clk_src[] = {
634 	F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
635 	{ }
636 };
637 
638 static struct clk_rcg2 gcc_pcie3x2_axi_m_clk_src = {
639 	.cmd_rcgr = 0x28018,
640 	.mnd_width = 0,
641 	.hid_width = 5,
642 	.parent_map = gcc_parent_map_2,
643 	.freq_tbl = ftbl_gcc_pcie3x2_axi_m_clk_src,
644 	.clkr.hw.init = &(const struct clk_init_data) {
645 		.name = "gcc_pcie3x2_axi_m_clk_src",
646 		.parent_data = gcc_parent_data_2,
647 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
648 		.ops = &clk_rcg2_ops,
649 	},
650 };
651 
652 static struct clk_rcg2 gcc_pcie3x2_axi_s_clk_src = {
653 	.cmd_rcgr = 0x28084,
654 	.mnd_width = 0,
655 	.hid_width = 5,
656 	.parent_map = gcc_parent_map_2,
657 	.freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
658 	.clkr.hw.init = &(const struct clk_init_data) {
659 		.name = "gcc_pcie3x2_axi_s_clk_src",
660 		.parent_data = gcc_parent_data_2,
661 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
662 		.ops = &clk_rcg2_ops,
663 	},
664 };
665 
666 static struct clk_rcg2 gcc_pcie3x2_rchg_clk_src = {
667 	.cmd_rcgr = 0x28078,
668 	.mnd_width = 0,
669 	.hid_width = 5,
670 	.parent_map = gcc_parent_map_0,
671 	.freq_tbl = ftbl_gcc_adss_pwm_clk_src,
672 	.clkr.hw.init = &(const struct clk_init_data) {
673 		.name = "gcc_pcie3x2_rchg_clk_src",
674 		.parent_data = gcc_parent_data_0,
675 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
676 		.ops = &clk_rcg2_ops,
677 	},
678 };
679 
680 static struct clk_branch gcc_pcie3x2_rchg_clk = {
681 	.halt_reg = 0x28078,
682 	.clkr = {
683 		.enable_reg = 0x28078,
684 		.enable_mask = BIT(1),
685 		.hw.init = &(struct clk_init_data) {
686 			.name = "gcc_pcie3x2_rchg_clk",
687 			.parent_hws = (const struct clk_hw *[]) {
688 					&gcc_pcie3x2_rchg_clk_src.clkr.hw },
689 			.num_parents = 1,
690 			.flags = CLK_SET_RATE_PARENT,
691 			.ops = &clk_branch2_ops,
692 		},
693 	},
694 };
695 
696 static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = {
697 	F(2000000, P_XO, 12, 0, 0),
698 	{ }
699 };
700 
701 static struct clk_rcg2 gcc_pcie_aux_clk_src = {
702 	.cmd_rcgr = 0x28004,
703 	.mnd_width = 16,
704 	.hid_width = 5,
705 	.parent_map = gcc_parent_map_5,
706 	.freq_tbl = ftbl_gcc_pcie_aux_clk_src,
707 	.clkr.hw.init = &(const struct clk_init_data) {
708 		.name = "gcc_pcie_aux_clk_src",
709 		.parent_data = gcc_parent_data_5,
710 		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
711 		.ops = &clk_rcg2_ops,
712 	},
713 };
714 
715 static struct clk_regmap_phy_mux gcc_pcie3x2_pipe_clk_src = {
716 	.reg = 0x28064,
717 	.clkr = {
718 		.hw.init = &(struct clk_init_data) {
719 			.name = "gcc_pcie3x2_pipe_clk_src",
720 			.parent_data = &(const struct clk_parent_data) {
721 				.index = DT_PCIE_2LANE_PHY_PIPE_CLK,
722 			},
723 			.num_parents = 1,
724 			.ops = &clk_regmap_phy_mux_ops,
725 		},
726 	},
727 };
728 
729 static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = {
730 	.reg = 0x29064,
731 	.clkr = {
732 		.hw.init = &(struct clk_init_data) {
733 			.name = "gcc_pcie3x1_0_pipe_clk_src",
734 			.parent_data = &(const struct clk_parent_data) {
735 				.index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
736 			},
737 			.num_parents = 1,
738 			.ops = &clk_regmap_phy_mux_ops,
739 		},
740 	},
741 };
742 
743 static struct clk_regmap_phy_mux gcc_pcie3x1_1_pipe_clk_src = {
744 	.reg = 0x2a064,
745 	.clkr = {
746 		.hw.init = &(struct clk_init_data) {
747 			.name = "gcc_pcie3x1_1_pipe_clk_src",
748 			.parent_data = &(const struct clk_parent_data) {
749 				.index = DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
750 			},
751 			.num_parents = 1,
752 			.ops = &clk_regmap_phy_mux_ops,
753 		},
754 	},
755 };
756 
757 static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = {
758 	F(24000000, P_XO, 1, 0, 0),
759 	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
760 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
761 	{ }
762 };
763 
764 static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = {
765 	.cmd_rcgr = 0x31004,
766 	.mnd_width = 0,
767 	.hid_width = 5,
768 	.parent_map = gcc_parent_map_0,
769 	.freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src,
770 	.clkr.hw.init = &(const struct clk_init_data) {
771 		.name = "gcc_pcnoc_bfdcd_clk_src",
772 		.parent_data = gcc_parent_data_0,
773 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
774 		.ops = &clk_rcg2_ops,
775 	},
776 };
777 
778 static struct clk_rcg2 gcc_q6_axim_clk_src = {
779 	.cmd_rcgr = 0x25004,
780 	.mnd_width = 0,
781 	.hid_width = 5,
782 	.parent_map = gcc_parent_map_6,
783 	.freq_tbl = ftbl_gcc_apss_axi_clk_src,
784 	.clkr.hw.init = &(const struct clk_init_data) {
785 		.name = "gcc_q6_axim_clk_src",
786 		.parent_data = gcc_parent_data_6,
787 		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
788 		.ops = &clk_rcg2_ops,
789 	},
790 };
791 
792 static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] = {
793 	F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
794 	{ }
795 };
796 
797 static struct clk_rcg2 gcc_qdss_at_clk_src = {
798 	.cmd_rcgr = 0x2d004,
799 	.mnd_width = 0,
800 	.hid_width = 5,
801 	.parent_map = gcc_parent_map_4,
802 	.freq_tbl = ftbl_gcc_qdss_at_clk_src,
803 	.clkr.hw.init = &(const struct clk_init_data) {
804 		.name = "gcc_qdss_at_clk_src",
805 		.parent_data = gcc_parent_data_4,
806 		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
807 		.ops = &clk_rcg2_ops,
808 	},
809 };
810 
811 static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] = {
812 	F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
813 	{ }
814 };
815 
816 static struct clk_rcg2 gcc_qdss_tsctr_clk_src = {
817 	.cmd_rcgr = 0x2d01c,
818 	.mnd_width = 0,
819 	.hid_width = 5,
820 	.parent_map = gcc_parent_map_4,
821 	.freq_tbl = ftbl_gcc_qdss_tsctr_clk_src,
822 	.clkr.hw.init = &(const struct clk_init_data) {
823 		.name = "gcc_qdss_tsctr_clk_src",
824 		.parent_data = gcc_parent_data_4,
825 		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
826 		.ops = &clk_rcg2_ops,
827 	},
828 };
829 
830 static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = {
831 	.mult = 1,
832 	.div = 2,
833 	.hw.init = &(struct clk_init_data) {
834 		.name = "gcc_qdss_tsctr_div2_clk_src",
835 		.parent_hws = (const struct clk_hw *[]) {
836 				&gcc_qdss_tsctr_clk_src.clkr.hw },
837 		.num_parents = 1,
838 		.flags = CLK_SET_RATE_PARENT,
839 		.ops = &clk_fixed_factor_ops,
840 	},
841 };
842 
843 static struct clk_fixed_factor gcc_qdss_tsctr_div3_clk_src = {
844 	.mult = 1,
845 	.div = 3,
846 	.hw.init = &(struct clk_init_data) {
847 		.name = "gcc_qdss_tsctr_div3_clk_src",
848 		.parent_hws = (const struct clk_hw *[]) {
849 				&gcc_qdss_tsctr_clk_src.clkr.hw },
850 		.num_parents = 1,
851 		.ops = &clk_fixed_factor_ops,
852 	},
853 };
854 
855 static struct clk_fixed_factor gcc_qdss_tsctr_div4_clk_src = {
856 	.mult = 1,
857 	.div = 4,
858 	.hw.init = &(struct clk_init_data) {
859 		.name = "gcc_qdss_tsctr_div4_clk_src",
860 		.parent_hws = (const struct clk_hw *[]) {
861 				&gcc_qdss_tsctr_clk_src.clkr.hw },
862 		.num_parents = 1,
863 		.ops = &clk_fixed_factor_ops,
864 	},
865 };
866 
867 static struct clk_fixed_factor gcc_qdss_tsctr_div8_clk_src = {
868 	.mult = 1,
869 	.div = 8,
870 	.hw.init = &(struct clk_init_data) {
871 		.name = "gcc_qdss_tsctr_div8_clk_src",
872 		.parent_hws = (const struct clk_hw *[]) {
873 				&gcc_qdss_tsctr_clk_src.clkr.hw },
874 		.num_parents = 1,
875 		.ops = &clk_fixed_factor_ops,
876 	},
877 };
878 
879 static struct clk_fixed_factor gcc_qdss_tsctr_div16_clk_src = {
880 	.mult = 1,
881 	.div = 16,
882 	.hw.init = &(struct clk_init_data) {
883 		.name = "gcc_qdss_tsctr_div16_clk_src",
884 		.parent_hws = (const struct clk_hw *[]) {
885 				&gcc_qdss_tsctr_clk_src.clkr.hw },
886 		.num_parents = 1,
887 		.ops = &clk_fixed_factor_ops,
888 	},
889 };
890 
891 static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] = {
892 	F(24000000, P_XO, 1, 0, 0),
893 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
894 	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
895 	F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
896 	{ }
897 };
898 
899 static struct clk_rcg2 gcc_qpic_io_macro_clk_src = {
900 	.cmd_rcgr = 0x32004,
901 	.mnd_width = 0,
902 	.hid_width = 5,
903 	.parent_map = gcc_parent_map_7,
904 	.freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,
905 	.clkr.hw.init = &(const struct clk_init_data) {
906 		.name = "gcc_qpic_io_macro_clk_src",
907 		.parent_data = gcc_parent_data_7,
908 		.num_parents = ARRAY_SIZE(gcc_parent_data_7),
909 		.ops = &clk_rcg2_ops,
910 	},
911 };
912 
913 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
914 	F(143713, P_XO, 1, 1, 167),
915 	F(400000, P_XO, 1, 1, 60),
916 	F(24000000, P_XO, 1, 0, 0),
917 	F(48000000, P_GPLL2_OUT_MAIN, 12, 1, 2),
918 	F(96000000, P_GPLL2_OUT_MAIN, 12, 0, 0),
919 	F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
920 	F(192000000, P_GPLL2_OUT_MAIN, 6, 0, 0),
921 	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
922 	{ }
923 };
924 
925 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
926 	.cmd_rcgr = 0x33004,
927 	.mnd_width = 8,
928 	.hid_width = 5,
929 	.parent_map = gcc_parent_map_8,
930 	.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
931 	.clkr.hw.init = &(const struct clk_init_data) {
932 		.name = "gcc_sdcc1_apps_clk_src",
933 		.parent_data = gcc_parent_data_8,
934 		.num_parents = ARRAY_SIZE(gcc_parent_data_8),
935 		.ops = &clk_rcg2_floor_ops,
936 	},
937 };
938 
939 static const struct freq_tbl ftbl_gcc_sleep_clk_src[] = {
940 	F(32000, P_SLEEP_CLK, 1, 0, 0),
941 	{ }
942 };
943 
944 static struct clk_rcg2 gcc_sleep_clk_src = {
945 	.cmd_rcgr = 0x3400c,
946 	.mnd_width = 0,
947 	.hid_width = 5,
948 	.parent_map = gcc_parent_map_9,
949 	.freq_tbl = ftbl_gcc_sleep_clk_src,
950 	.clkr.hw.init = &(const struct clk_init_data) {
951 		.name = "gcc_sleep_clk_src",
952 		.parent_data = gcc_parent_data_9,
953 		.num_parents = ARRAY_SIZE(gcc_parent_data_9),
954 		.ops = &clk_rcg2_ops,
955 	},
956 };
957 
958 static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] = {
959 	F(24000000, P_XO, 1, 0, 0),
960 	F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
961 	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
962 	F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
963 	{ }
964 };
965 
966 static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {
967 	.cmd_rcgr = 0x2e004,
968 	.mnd_width = 0,
969 	.hid_width = 5,
970 	.parent_map = gcc_parent_map_10,
971 	.freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src,
972 	.clkr.hw.init = &(const struct clk_init_data) {
973 		.name = "gcc_system_noc_bfdcd_clk_src",
974 		.parent_data = gcc_parent_data_10,
975 		.num_parents = ARRAY_SIZE(gcc_parent_data_10),
976 		.ops = &clk_rcg2_ops,
977 	},
978 };
979 
980 static struct clk_fixed_factor gcc_system_noc_bfdcd_div2_clk_src = {
981 	.mult = 1,
982 	.div = 2,
983 	.hw.init = &(struct clk_init_data) {
984 		.name = "gcc_system_noc_bfdcd_div2_clk_src",
985 		.parent_hws = (const struct clk_hw *[]) {
986 				&gcc_system_noc_bfdcd_clk_src.clkr.hw },
987 		.num_parents = 1,
988 		.ops = &clk_fixed_factor_ops,
989 		.flags = CLK_SET_RATE_PARENT,
990 	},
991 };
992 
993 static struct clk_rcg2 gcc_uniphy_sys_clk_src = {
994 	.cmd_rcgr = 0x16004,
995 	.mnd_width = 0,
996 	.hid_width = 5,
997 	.parent_map = gcc_parent_map_xo,
998 	.freq_tbl = ftbl_gcc_nss_ts_clk_src,
999 	.clkr.hw.init = &(const struct clk_init_data) {
1000 		.name = "gcc_uniphy_sys_clk_src",
1001 		.parent_data = &gcc_parent_data_xo,
1002 		.num_parents = 1,
1003 		.ops = &clk_rcg2_ops,
1004 	},
1005 };
1006 
1007 static struct clk_rcg2 gcc_usb0_aux_clk_src = {
1008 	.cmd_rcgr = 0x2c018,
1009 	.mnd_width = 16,
1010 	.hid_width = 5,
1011 	.parent_map = gcc_parent_map_11,
1012 	.freq_tbl = ftbl_gcc_pcie_aux_clk_src,
1013 	.clkr.hw.init = &(const struct clk_init_data) {
1014 		.name = "gcc_usb0_aux_clk_src",
1015 		.parent_data = gcc_parent_data_11,
1016 		.num_parents = ARRAY_SIZE(gcc_parent_data_11),
1017 		.ops = &clk_rcg2_ops,
1018 	},
1019 };
1020 
1021 static const struct freq_tbl ftbl_gcc_usb0_lfps_clk_src[] = {
1022 	F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1023 	{ }
1024 };
1025 
1026 static struct clk_rcg2 gcc_usb0_lfps_clk_src = {
1027 	.cmd_rcgr = 0x2c07c,
1028 	.mnd_width = 8,
1029 	.hid_width = 5,
1030 	.parent_map = gcc_parent_map_1,
1031 	.freq_tbl = ftbl_gcc_usb0_lfps_clk_src,
1032 	.clkr.hw.init = &(const struct clk_init_data) {
1033 		.name = "gcc_usb0_lfps_clk_src",
1034 		.parent_data = gcc_parent_data_1,
1035 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1036 		.ops = &clk_rcg2_ops,
1037 	},
1038 };
1039 
1040 static struct clk_rcg2 gcc_usb0_master_clk_src = {
1041 	.cmd_rcgr = 0x2c004,
1042 	.mnd_width = 8,
1043 	.hid_width = 5,
1044 	.parent_map = gcc_parent_map_0,
1045 	.freq_tbl = ftbl_gcc_gp1_clk_src,
1046 	.clkr.hw.init = &(const struct clk_init_data) {
1047 		.name = "gcc_usb0_master_clk_src",
1048 		.parent_data = gcc_parent_data_0,
1049 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1050 		.ops = &clk_rcg2_ops,
1051 	},
1052 };
1053 
1054 static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = {
1055 	F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2),
1056 	{ }
1057 };
1058 
1059 static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
1060 	.cmd_rcgr = 0x2c02c,
1061 	.mnd_width = 8,
1062 	.hid_width = 5,
1063 	.parent_map = gcc_parent_map_12,
1064 	.freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,
1065 	.clkr.hw.init = &(const struct clk_init_data) {
1066 		.name = "gcc_usb0_mock_utmi_clk_src",
1067 		.parent_data = gcc_parent_data_12,
1068 		.num_parents = ARRAY_SIZE(gcc_parent_data_12),
1069 		.ops = &clk_rcg2_ops,
1070 	},
1071 };
1072 
1073 static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {
1074 	.reg = 0x2c074,
1075 	.clkr = {
1076 		.hw.init = &(struct clk_init_data) {
1077 			.name = "gcc_usb0_pipe_clk_src",
1078 			.parent_data = &(const struct clk_parent_data) {
1079 				.index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
1080 			},
1081 			.num_parents = 1,
1082 			.ops = &clk_regmap_phy_mux_ops,
1083 		},
1084 	},
1085 };
1086 
1087 static struct clk_rcg2 gcc_wcss_ahb_clk_src = {
1088 	.cmd_rcgr = 0x25030,
1089 	.mnd_width = 0,
1090 	.hid_width = 5,
1091 	.parent_map = gcc_parent_map_1,
1092 	.freq_tbl = ftbl_gcc_lpass_sway_clk_src,
1093 	.clkr.hw.init = &(const struct clk_init_data) {
1094 		.name = "gcc_wcss_ahb_clk_src",
1095 		.parent_data = gcc_parent_data_1,
1096 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1097 		.ops = &clk_rcg2_ops,
1098 	},
1099 };
1100 
1101 static struct clk_rcg2 gcc_xo_clk_src = {
1102 	.cmd_rcgr = 0x34004,
1103 	.mnd_width = 0,
1104 	.hid_width = 5,
1105 	.parent_map = gcc_parent_map_xo,
1106 	.freq_tbl = ftbl_gcc_nss_ts_clk_src,
1107 	.clkr.hw.init = &(const struct clk_init_data) {
1108 		.name = "gcc_xo_clk_src",
1109 		.parent_data = &gcc_parent_data_xo,
1110 		.num_parents = 1,
1111 		.ops = &clk_rcg2_ops,
1112 	},
1113 };
1114 
1115 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
1116 	.mult = 1,
1117 	.div = 4,
1118 	.hw.init = &(struct clk_init_data) {
1119 		.name = "gcc_xo_div4_clk_src",
1120 		.parent_hws = (const struct clk_hw *[]) {
1121 				&gcc_xo_clk_src.clkr.hw },
1122 		.num_parents = 1,
1123 		.ops = &clk_fixed_factor_ops,
1124 		.flags = CLK_SET_RATE_PARENT,
1125 	},
1126 };
1127 
1128 static struct clk_regmap_div gcc_qdss_dap_div_clk_src = {
1129 	.reg = 0x2d028,
1130 	.shift = 0,
1131 	.width = 4,
1132 	.clkr.hw.init = &(const struct clk_init_data) {
1133 		.name = "gcc_qdss_dap_div_clk_src",
1134 		.parent_hws = (const struct clk_hw*[]) {
1135 			&gcc_qdss_tsctr_clk_src.clkr.hw,
1136 		},
1137 		.num_parents = 1,
1138 		.ops = &clk_regmap_div_ro_ops,
1139 	},
1140 };
1141 
1142 static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src = {
1143 	.reg = 0x2c040,
1144 	.shift = 0,
1145 	.width = 2,
1146 	.clkr.hw.init = &(const struct clk_init_data) {
1147 		.name = "gcc_usb0_mock_utmi_div_clk_src",
1148 		.parent_hws = (const struct clk_hw*[]) {
1149 			&gcc_usb0_mock_utmi_clk_src.clkr.hw,
1150 		},
1151 		.num_parents = 1,
1152 		.flags = CLK_SET_RATE_PARENT,
1153 		.ops = &clk_regmap_div_ro_ops,
1154 	},
1155 };
1156 
1157 static struct clk_branch gcc_adss_pwm_clk = {
1158 	.halt_reg = 0x1c00c,
1159 	.halt_check = BRANCH_HALT,
1160 	.clkr = {
1161 		.enable_reg = 0x1c00c,
1162 		.enable_mask = BIT(0),
1163 		.hw.init = &(const struct clk_init_data) {
1164 			.name = "gcc_adss_pwm_clk",
1165 			.parent_hws = (const struct clk_hw*[]) {
1166 				&gcc_adss_pwm_clk_src.clkr.hw,
1167 			},
1168 			.num_parents = 1,
1169 			.flags = CLK_SET_RATE_PARENT,
1170 			.ops = &clk_branch2_ops,
1171 		},
1172 	},
1173 };
1174 
1175 static struct clk_branch gcc_ahb_clk = {
1176 	.halt_reg = 0x34024,
1177 	.halt_check = BRANCH_HALT_VOTED,
1178 	.clkr = {
1179 		.enable_reg = 0x34024,
1180 		.enable_mask = BIT(0),
1181 		.hw.init = &(const struct clk_init_data) {
1182 			.name = "gcc_ahb_clk",
1183 			.parent_hws = (const struct clk_hw*[]) {
1184 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1185 			},
1186 			.num_parents = 1,
1187 			.flags = CLK_SET_RATE_PARENT,
1188 			.ops = &clk_branch2_ops,
1189 		},
1190 	},
1191 };
1192 
1193 static struct clk_branch gcc_blsp1_ahb_clk = {
1194 	.halt_reg = 0x1008,
1195 	.halt_check = BRANCH_HALT_VOTED,
1196 	.clkr = {
1197 		.enable_reg = 0xb004,
1198 		.enable_mask = BIT(4),
1199 		.hw.init = &(const struct clk_init_data) {
1200 			.name = "gcc_blsp1_ahb_clk",
1201 			.parent_hws = (const struct clk_hw*[]) {
1202 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1203 			},
1204 			.num_parents = 1,
1205 			.flags = CLK_SET_RATE_PARENT,
1206 			.ops = &clk_branch2_ops,
1207 		},
1208 	},
1209 };
1210 
1211 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1212 	.halt_reg = 0x2024,
1213 	.halt_check = BRANCH_HALT,
1214 	.clkr = {
1215 		.enable_reg = 0x2024,
1216 		.enable_mask = BIT(0),
1217 		.hw.init = &(const struct clk_init_data) {
1218 			.name = "gcc_blsp1_qup1_i2c_apps_clk",
1219 			.parent_hws = (const struct clk_hw*[]) {
1220 				&gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
1221 			},
1222 			.num_parents = 1,
1223 			.flags = CLK_SET_RATE_PARENT,
1224 			.ops = &clk_branch2_ops,
1225 		},
1226 	},
1227 };
1228 
1229 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1230 	.halt_reg = 0x2020,
1231 	.halt_check = BRANCH_HALT,
1232 	.clkr = {
1233 		.enable_reg = 0x2020,
1234 		.enable_mask = BIT(0),
1235 		.hw.init = &(const struct clk_init_data) {
1236 			.name = "gcc_blsp1_qup1_spi_apps_clk",
1237 			.parent_hws = (const struct clk_hw*[]) {
1238 				&gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
1239 			},
1240 			.num_parents = 1,
1241 			.flags = CLK_SET_RATE_PARENT,
1242 			.ops = &clk_branch2_ops,
1243 		},
1244 	},
1245 };
1246 
1247 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1248 	.halt_reg = 0x3024,
1249 	.halt_check = BRANCH_HALT,
1250 	.clkr = {
1251 		.enable_reg = 0x3024,
1252 		.enable_mask = BIT(0),
1253 		.hw.init = &(const struct clk_init_data) {
1254 			.name = "gcc_blsp1_qup2_i2c_apps_clk",
1255 			.parent_hws = (const struct clk_hw*[]) {
1256 				&gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
1257 			},
1258 			.num_parents = 1,
1259 			.flags = CLK_SET_RATE_PARENT,
1260 			.ops = &clk_branch2_ops,
1261 		},
1262 	},
1263 };
1264 
1265 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1266 	.halt_reg = 0x3020,
1267 	.halt_check = BRANCH_HALT,
1268 	.clkr = {
1269 		.enable_reg = 0x3020,
1270 		.enable_mask = BIT(0),
1271 		.hw.init = &(const struct clk_init_data) {
1272 			.name = "gcc_blsp1_qup2_spi_apps_clk",
1273 			.parent_hws = (const struct clk_hw*[]) {
1274 				&gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
1275 			},
1276 			.num_parents = 1,
1277 			.flags = CLK_SET_RATE_PARENT,
1278 			.ops = &clk_branch2_ops,
1279 		},
1280 	},
1281 };
1282 
1283 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1284 	.halt_reg = 0x4024,
1285 	.halt_check = BRANCH_HALT,
1286 	.clkr = {
1287 		.enable_reg = 0x4024,
1288 		.enable_mask = BIT(0),
1289 		.hw.init = &(const struct clk_init_data) {
1290 			.name = "gcc_blsp1_qup3_i2c_apps_clk",
1291 			.parent_hws = (const struct clk_hw*[]) {
1292 				&gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
1293 			},
1294 			.num_parents = 1,
1295 			.flags = CLK_SET_RATE_PARENT,
1296 			.ops = &clk_branch2_ops,
1297 		},
1298 	},
1299 };
1300 
1301 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1302 	.halt_reg = 0x4020,
1303 	.halt_check = BRANCH_HALT,
1304 	.clkr = {
1305 		.enable_reg = 0x4020,
1306 		.enable_mask = BIT(0),
1307 		.hw.init = &(const struct clk_init_data) {
1308 			.name = "gcc_blsp1_qup3_spi_apps_clk",
1309 			.parent_hws = (const struct clk_hw*[]) {
1310 				&gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
1311 			},
1312 			.num_parents = 1,
1313 			.flags = CLK_SET_RATE_PARENT,
1314 			.ops = &clk_branch2_ops,
1315 		},
1316 	},
1317 };
1318 
1319 static struct clk_branch gcc_blsp1_sleep_clk = {
1320 	.halt_reg = 0x1010,
1321 	.halt_check = BRANCH_HALT_VOTED,
1322 	.clkr = {
1323 		.enable_reg = 0xb004,
1324 		.enable_mask = BIT(5),
1325 		.hw.init = &(const struct clk_init_data) {
1326 			.name = "gcc_blsp1_sleep_clk",
1327 			.parent_hws = (const struct clk_hw*[]) {
1328 				&gcc_sleep_clk_src.clkr.hw,
1329 			},
1330 			.num_parents = 1,
1331 			.flags = CLK_SET_RATE_PARENT,
1332 			.ops = &clk_branch2_ops,
1333 		},
1334 	},
1335 };
1336 
1337 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1338 	.halt_reg = 0x2040,
1339 	.halt_check = BRANCH_HALT,
1340 	.clkr = {
1341 		.enable_reg = 0x2040,
1342 		.enable_mask = BIT(0),
1343 		.hw.init = &(const struct clk_init_data) {
1344 			.name = "gcc_blsp1_uart1_apps_clk",
1345 			.parent_hws = (const struct clk_hw*[]) {
1346 				&gcc_blsp1_uart1_apps_clk_src.clkr.hw,
1347 			},
1348 			.num_parents = 1,
1349 			.flags = CLK_SET_RATE_PARENT,
1350 			.ops = &clk_branch2_ops,
1351 		},
1352 	},
1353 };
1354 
1355 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1356 	.halt_reg = 0x3040,
1357 	.halt_check = BRANCH_HALT,
1358 	.clkr = {
1359 		.enable_reg = 0x3040,
1360 		.enable_mask = BIT(0),
1361 		.hw.init = &(const struct clk_init_data) {
1362 			.name = "gcc_blsp1_uart2_apps_clk",
1363 			.parent_hws = (const struct clk_hw*[]) {
1364 				&gcc_blsp1_uart2_apps_clk_src.clkr.hw,
1365 			},
1366 			.num_parents = 1,
1367 			.flags = CLK_SET_RATE_PARENT,
1368 			.ops = &clk_branch2_ops,
1369 		},
1370 	},
1371 };
1372 
1373 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1374 	.halt_reg = 0x4054,
1375 	.halt_check = BRANCH_HALT,
1376 	.clkr = {
1377 		.enable_reg = 0x4054,
1378 		.enable_mask = BIT(0),
1379 		.hw.init = &(const struct clk_init_data) {
1380 			.name = "gcc_blsp1_uart3_apps_clk",
1381 			.parent_hws = (const struct clk_hw*[]) {
1382 				&gcc_blsp1_uart3_apps_clk_src.clkr.hw,
1383 			},
1384 			.num_parents = 1,
1385 			.flags = CLK_SET_RATE_PARENT,
1386 			.ops = &clk_branch2_ops,
1387 		},
1388 	},
1389 };
1390 
1391 static struct clk_branch gcc_ce_ahb_clk = {
1392 	.halt_reg = 0x25074,
1393 	.halt_check = BRANCH_HALT,
1394 	.clkr = {
1395 		.enable_reg = 0x25074,
1396 		.enable_mask = BIT(0),
1397 		.hw.init = &(const struct clk_init_data) {
1398 			.name = "gcc_ce_ahb_clk",
1399 			.parent_hws = (const struct clk_hw*[]) {
1400 				&gcc_system_noc_bfdcd_div2_clk_src.hw,
1401 			},
1402 			.num_parents = 1,
1403 			.flags = CLK_SET_RATE_PARENT,
1404 			.ops = &clk_branch2_ops,
1405 		},
1406 	},
1407 };
1408 
1409 static struct clk_branch gcc_ce_axi_clk = {
1410 	.halt_reg = 0x25068,
1411 	.halt_check = BRANCH_HALT,
1412 	.clkr = {
1413 		.enable_reg = 0x25068,
1414 		.enable_mask = BIT(0),
1415 		.hw.init = &(const struct clk_init_data) {
1416 			.name = "gcc_ce_axi_clk",
1417 			.parent_hws = (const struct clk_hw*[]) {
1418 				&gcc_system_noc_bfdcd_clk_src.clkr.hw,
1419 			},
1420 			.num_parents = 1,
1421 			.flags = CLK_SET_RATE_PARENT,
1422 			.ops = &clk_branch2_ops,
1423 		},
1424 	},
1425 };
1426 
1427 static struct clk_branch gcc_ce_pcnoc_ahb_clk = {
1428 	.halt_reg = 0x25070,
1429 	.halt_check = BRANCH_HALT,
1430 	.clkr = {
1431 		.enable_reg = 0x25070,
1432 		.enable_mask = BIT(0),
1433 		.hw.init = &(const struct clk_init_data) {
1434 			.name = "gcc_ce_pcnoc_ahb_clk",
1435 			.parent_hws = (const struct clk_hw*[]) {
1436 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1437 			},
1438 			.num_parents = 1,
1439 			.flags = CLK_SET_RATE_PARENT,
1440 			.ops = &clk_branch2_ops,
1441 		},
1442 	},
1443 };
1444 
1445 static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
1446 	.halt_reg = 0x3a004,
1447 	.halt_check = BRANCH_HALT,
1448 	.clkr = {
1449 		.enable_reg = 0x3a004,
1450 		.enable_mask = BIT(0),
1451 		.hw.init = &(const struct clk_init_data) {
1452 			.name = "gcc_cmn_12gpll_ahb_clk",
1453 			.parent_hws = (const struct clk_hw*[]) {
1454 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1455 			},
1456 			.num_parents = 1,
1457 			.flags = CLK_SET_RATE_PARENT,
1458 			.ops = &clk_branch2_ops,
1459 		},
1460 	},
1461 };
1462 
1463 static struct clk_branch gcc_cmn_12gpll_apu_clk = {
1464 	.halt_reg = 0x3a00c,
1465 	.halt_check = BRANCH_HALT,
1466 	.clkr = {
1467 		.enable_reg = 0x3a00c,
1468 		.enable_mask = BIT(0),
1469 		.hw.init = &(const struct clk_init_data) {
1470 			.name = "gcc_cmn_12gpll_apu_clk",
1471 			.parent_hws = (const struct clk_hw*[]) {
1472 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1473 			},
1474 			.num_parents = 1,
1475 			.flags = CLK_SET_RATE_PARENT,
1476 			.ops = &clk_branch2_ops,
1477 		},
1478 	},
1479 };
1480 
1481 static struct clk_branch gcc_cmn_12gpll_sys_clk = {
1482 	.halt_reg = 0x3a008,
1483 	.halt_check = BRANCH_HALT,
1484 	.clkr = {
1485 		.enable_reg = 0x3a008,
1486 		.enable_mask = BIT(0),
1487 		.hw.init = &(const struct clk_init_data) {
1488 			.name = "gcc_cmn_12gpll_sys_clk",
1489 			.parent_hws = (const struct clk_hw*[]) {
1490 				&gcc_uniphy_sys_clk_src.clkr.hw,
1491 			},
1492 			.num_parents = 1,
1493 			.flags = CLK_SET_RATE_PARENT,
1494 			.ops = &clk_branch2_ops,
1495 		},
1496 	},
1497 };
1498 
1499 static struct clk_branch gcc_gp1_clk = {
1500 	.halt_reg = 0x8018,
1501 	.halt_check = BRANCH_HALT,
1502 	.clkr = {
1503 		.enable_reg = 0x8018,
1504 		.enable_mask = BIT(0),
1505 		.hw.init = &(const struct clk_init_data) {
1506 			.name = "gcc_gp1_clk",
1507 			.parent_hws = (const struct clk_hw*[]) {
1508 				&gcc_gp1_clk_src.clkr.hw,
1509 			},
1510 			.num_parents = 1,
1511 			.flags = CLK_SET_RATE_PARENT,
1512 			.ops = &clk_branch2_ops,
1513 		},
1514 	},
1515 };
1516 
1517 static struct clk_branch gcc_gp2_clk = {
1518 	.halt_reg = 0x9018,
1519 	.halt_check = BRANCH_HALT,
1520 	.clkr = {
1521 		.enable_reg = 0x9018,
1522 		.enable_mask = BIT(0),
1523 		.hw.init = &(const struct clk_init_data) {
1524 			.name = "gcc_gp2_clk",
1525 			.parent_hws = (const struct clk_hw*[]) {
1526 				&gcc_gp2_clk_src.clkr.hw,
1527 			},
1528 			.num_parents = 1,
1529 			.flags = CLK_SET_RATE_PARENT,
1530 			.ops = &clk_branch2_ops,
1531 		},
1532 	},
1533 };
1534 
1535 static struct clk_branch gcc_lpass_core_axim_clk = {
1536 	.halt_reg = 0x27018,
1537 	.halt_check = BRANCH_HALT_VOTED,
1538 	.clkr = {
1539 		.enable_reg = 0x27018,
1540 		.enable_mask = BIT(0),
1541 		.hw.init = &(const struct clk_init_data) {
1542 			.name = "gcc_lpass_core_axim_clk",
1543 			.parent_hws = (const struct clk_hw*[]) {
1544 				&gcc_lpass_sway_clk_src.clkr.hw,
1545 			},
1546 			.num_parents = 1,
1547 			.flags = CLK_SET_RATE_PARENT,
1548 			.ops = &clk_branch2_ops,
1549 		},
1550 	},
1551 };
1552 
1553 static struct clk_branch gcc_lpass_sway_clk = {
1554 	.halt_reg = 0x27014,
1555 	.halt_check = BRANCH_HALT,
1556 	.clkr = {
1557 		.enable_reg = 0x27014,
1558 		.enable_mask = BIT(0),
1559 		.hw.init = &(const struct clk_init_data) {
1560 			.name = "gcc_lpass_sway_clk",
1561 			.parent_hws = (const struct clk_hw*[]) {
1562 				&gcc_lpass_sway_clk_src.clkr.hw,
1563 			},
1564 			.num_parents = 1,
1565 			.flags = CLK_SET_RATE_PARENT,
1566 			.ops = &clk_branch2_ops,
1567 		},
1568 	},
1569 };
1570 
1571 static struct clk_branch gcc_mdio_ahb_clk = {
1572 	.halt_reg = 0x12004,
1573 	.halt_check = BRANCH_HALT,
1574 	.clkr = {
1575 		.enable_reg = 0x12004,
1576 		.enable_mask = BIT(0),
1577 		.hw.init = &(const struct clk_init_data) {
1578 			.name = "gcc_mdio_ahb_clk",
1579 			.parent_hws = (const struct clk_hw*[]) {
1580 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1581 			},
1582 			.num_parents = 1,
1583 			.flags = CLK_SET_RATE_PARENT,
1584 			.ops = &clk_branch2_ops,
1585 		},
1586 	},
1587 };
1588 
1589 static struct clk_branch gcc_mdio_slave_ahb_clk = {
1590 	.halt_reg = 0x1200c,
1591 	.halt_check = BRANCH_HALT,
1592 	.clkr = {
1593 		.enable_reg = 0x1200c,
1594 		.enable_mask = BIT(0),
1595 		.hw.init = &(const struct clk_init_data) {
1596 			.name = "gcc_mdio_slave_ahb_clk",
1597 			.parent_hws = (const struct clk_hw*[]) {
1598 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1599 			},
1600 			.num_parents = 1,
1601 			.flags = CLK_SET_RATE_PARENT,
1602 			.ops = &clk_branch2_ops,
1603 		},
1604 	},
1605 };
1606 
1607 static struct clk_branch gcc_nss_ts_clk = {
1608 	.halt_reg = 0x17018,
1609 	.halt_check = BRANCH_HALT_VOTED,
1610 	.clkr = {
1611 		.enable_reg = 0x17018,
1612 		.enable_mask = BIT(0),
1613 		.hw.init = &(const struct clk_init_data) {
1614 			.name = "gcc_nss_ts_clk",
1615 			.parent_hws = (const struct clk_hw*[]) {
1616 				&gcc_nss_ts_clk_src.clkr.hw,
1617 			},
1618 			.num_parents = 1,
1619 			.flags = CLK_SET_RATE_PARENT,
1620 			.ops = &clk_branch2_ops,
1621 		},
1622 	},
1623 };
1624 
1625 static struct clk_branch gcc_nsscc_clk = {
1626 	.halt_reg = 0x17034,
1627 	.halt_check = BRANCH_HALT,
1628 	.clkr = {
1629 		.enable_reg = 0x17034,
1630 		.enable_mask = BIT(0),
1631 		.hw.init = &(const struct clk_init_data) {
1632 			.name = "gcc_nsscc_clk",
1633 			.parent_hws = (const struct clk_hw*[]) {
1634 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1635 			},
1636 			.num_parents = 1,
1637 			.flags = CLK_SET_RATE_PARENT,
1638 			.ops = &clk_branch2_ops,
1639 		},
1640 	},
1641 };
1642 
1643 static struct clk_branch gcc_nsscfg_clk = {
1644 	.halt_reg = 0x1702c,
1645 	.halt_check = BRANCH_HALT,
1646 	.clkr = {
1647 		.enable_reg = 0x1702c,
1648 		.enable_mask = BIT(0),
1649 		.hw.init = &(const struct clk_init_data) {
1650 			.name = "gcc_nsscfg_clk",
1651 			.parent_hws = (const struct clk_hw*[]) {
1652 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1653 			},
1654 			.num_parents = 1,
1655 			.flags = CLK_SET_RATE_PARENT,
1656 			.ops = &clk_branch2_ops,
1657 		},
1658 	},
1659 };
1660 
1661 static struct clk_branch gcc_nssnoc_atb_clk = {
1662 	.halt_reg = 0x17014,
1663 	.halt_check = BRANCH_HALT,
1664 	.clkr = {
1665 		.enable_reg = 0x17014,
1666 		.enable_mask = BIT(0),
1667 		.hw.init = &(const struct clk_init_data) {
1668 			.name = "gcc_nssnoc_atb_clk",
1669 			.parent_hws = (const struct clk_hw*[]) {
1670 				&gcc_qdss_at_clk_src.clkr.hw,
1671 			},
1672 			.num_parents = 1,
1673 			.flags = CLK_SET_RATE_PARENT,
1674 			.ops = &clk_branch2_ops,
1675 		},
1676 	},
1677 };
1678 
1679 static struct clk_branch gcc_nssnoc_nsscc_clk = {
1680 	.halt_reg = 0x17030,
1681 	.halt_check = BRANCH_HALT,
1682 	.clkr = {
1683 		.enable_reg = 0x17030,
1684 		.enable_mask = BIT(0),
1685 		.hw.init = &(const struct clk_init_data) {
1686 			.name = "gcc_nssnoc_nsscc_clk",
1687 			.parent_hws = (const struct clk_hw*[]) {
1688 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1689 			},
1690 			.num_parents = 1,
1691 			.flags = CLK_SET_RATE_PARENT,
1692 			.ops = &clk_branch2_ops,
1693 		},
1694 	},
1695 };
1696 
1697 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
1698 	.halt_reg = 0x1701c,
1699 	.halt_check = BRANCH_HALT,
1700 	.clkr = {
1701 		.enable_reg = 0x1701c,
1702 		.enable_mask = BIT(0),
1703 		.hw.init = &(const struct clk_init_data) {
1704 			.name = "gcc_nssnoc_qosgen_ref_clk",
1705 			.parent_hws = (const struct clk_hw*[]) {
1706 				&gcc_xo_div4_clk_src.hw,
1707 			},
1708 			.num_parents = 1,
1709 			.flags = CLK_SET_RATE_PARENT,
1710 			.ops = &clk_branch2_ops,
1711 		},
1712 	},
1713 };
1714 
1715 static struct clk_branch gcc_nssnoc_snoc_1_clk = {
1716 	.halt_reg = 0x1707c,
1717 	.halt_check = BRANCH_HALT,
1718 	.clkr = {
1719 		.enable_reg = 0x1707c,
1720 		.enable_mask = BIT(0),
1721 		.hw.init = &(const struct clk_init_data) {
1722 			.name = "gcc_nssnoc_snoc_1_clk",
1723 			.parent_hws = (const struct clk_hw*[]) {
1724 				&gcc_system_noc_bfdcd_clk_src.clkr.hw,
1725 			},
1726 			.num_parents = 1,
1727 			.flags = CLK_SET_RATE_PARENT,
1728 			.ops = &clk_branch2_ops,
1729 		},
1730 	},
1731 };
1732 
1733 static struct clk_branch gcc_nssnoc_snoc_clk = {
1734 	.halt_reg = 0x17028,
1735 	.halt_check = BRANCH_HALT,
1736 	.clkr = {
1737 		.enable_reg = 0x17028,
1738 		.enable_mask = BIT(0),
1739 		.hw.init = &(const struct clk_init_data) {
1740 			.name = "gcc_nssnoc_snoc_clk",
1741 			.parent_hws = (const struct clk_hw*[]) {
1742 				&gcc_system_noc_bfdcd_clk_src.clkr.hw,
1743 			},
1744 			.num_parents = 1,
1745 			.flags = CLK_SET_RATE_PARENT,
1746 			.ops = &clk_branch2_ops,
1747 		},
1748 	},
1749 };
1750 
1751 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
1752 	.halt_reg = 0x17020,
1753 	.halt_check = BRANCH_HALT,
1754 	.clkr = {
1755 		.enable_reg = 0x17020,
1756 		.enable_mask = BIT(0),
1757 		.hw.init = &(const struct clk_init_data) {
1758 			.name = "gcc_nssnoc_timeout_ref_clk",
1759 			.parent_hws = (const struct clk_hw*[]) {
1760 				&gcc_xo_div4_clk_src.hw,
1761 			},
1762 			.num_parents = 1,
1763 			.flags = CLK_SET_RATE_PARENT,
1764 			.ops = &clk_branch2_ops,
1765 		},
1766 	},
1767 };
1768 
1769 static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
1770 	.halt_reg = 0x17074,
1771 	.halt_check = BRANCH_HALT,
1772 	.clkr = {
1773 		.enable_reg = 0x17074,
1774 		.enable_mask = BIT(0),
1775 		.hw.init = &(const struct clk_init_data) {
1776 			.name = "gcc_nssnoc_xo_dcd_clk",
1777 			.parent_hws = (const struct clk_hw*[]) {
1778 				&gcc_xo_clk_src.clkr.hw,
1779 			},
1780 			.num_parents = 1,
1781 			.flags = CLK_SET_RATE_PARENT,
1782 			.ops = &clk_branch2_ops,
1783 		},
1784 	},
1785 };
1786 
1787 static struct clk_branch gcc_pcie3x1_0_ahb_clk = {
1788 	.halt_reg = 0x29030,
1789 	.halt_check = BRANCH_HALT,
1790 	.clkr = {
1791 		.enable_reg = 0x29030,
1792 		.enable_mask = BIT(0),
1793 		.hw.init = &(const struct clk_init_data) {
1794 			.name = "gcc_pcie3x1_0_ahb_clk",
1795 			.parent_hws = (const struct clk_hw*[]) {
1796 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1797 			},
1798 			.num_parents = 1,
1799 			.flags = CLK_SET_RATE_PARENT,
1800 			.ops = &clk_branch2_ops,
1801 		},
1802 	},
1803 };
1804 
1805 static struct clk_branch gcc_pcie3x1_0_aux_clk = {
1806 	.halt_reg = 0x29070,
1807 	.halt_check = BRANCH_HALT,
1808 	.clkr = {
1809 		.enable_reg = 0x29070,
1810 		.enable_mask = BIT(0),
1811 		.hw.init = &(const struct clk_init_data) {
1812 			.name = "gcc_pcie3x1_0_aux_clk",
1813 			.parent_hws = (const struct clk_hw*[]) {
1814 				&gcc_pcie_aux_clk_src.clkr.hw,
1815 			},
1816 			.num_parents = 1,
1817 			.flags = CLK_SET_RATE_PARENT,
1818 			.ops = &clk_branch2_ops,
1819 		},
1820 	},
1821 };
1822 
1823 static struct clk_branch gcc_pcie3x1_0_axi_m_clk = {
1824 	.halt_reg = 0x29038,
1825 	.halt_check = BRANCH_HALT,
1826 	.clkr = {
1827 		.enable_reg = 0x29038,
1828 		.enable_mask = BIT(0),
1829 		.hw.init = &(const struct clk_init_data) {
1830 			.name = "gcc_pcie3x1_0_axi_m_clk",
1831 			.parent_hws = (const struct clk_hw*[]) {
1832 				&gcc_pcie3x1_0_axi_clk_src.clkr.hw,
1833 			},
1834 			.num_parents = 1,
1835 			.flags = CLK_SET_RATE_PARENT,
1836 			.ops = &clk_branch2_ops,
1837 		},
1838 	},
1839 };
1840 
1841 static struct clk_branch gcc_pcie3x1_0_axi_s_bridge_clk = {
1842 	.halt_reg = 0x29048,
1843 	.halt_check = BRANCH_HALT,
1844 	.clkr = {
1845 		.enable_reg = 0x29048,
1846 		.enable_mask = BIT(0),
1847 		.hw.init = &(const struct clk_init_data) {
1848 			.name = "gcc_pcie3x1_0_axi_s_bridge_clk",
1849 			.parent_hws = (const struct clk_hw*[]) {
1850 				&gcc_pcie3x1_0_axi_clk_src.clkr.hw,
1851 			},
1852 			.num_parents = 1,
1853 			.flags = CLK_SET_RATE_PARENT,
1854 			.ops = &clk_branch2_ops,
1855 		},
1856 	},
1857 };
1858 
1859 static struct clk_branch gcc_pcie3x1_0_axi_s_clk = {
1860 	.halt_reg = 0x29040,
1861 	.halt_check = BRANCH_HALT,
1862 	.clkr = {
1863 		.enable_reg = 0x29040,
1864 		.enable_mask = BIT(0),
1865 		.hw.init = &(const struct clk_init_data) {
1866 			.name = "gcc_pcie3x1_0_axi_s_clk",
1867 			.parent_hws = (const struct clk_hw*[]) {
1868 				&gcc_pcie3x1_0_axi_clk_src.clkr.hw,
1869 			},
1870 			.num_parents = 1,
1871 			.flags = CLK_SET_RATE_PARENT,
1872 			.ops = &clk_branch2_ops,
1873 		},
1874 	},
1875 };
1876 
1877 static struct clk_branch gcc_pcie3x1_0_pipe_clk = {
1878 	.halt_reg = 0x29068,
1879 	.halt_check = BRANCH_HALT_DELAY,
1880 	.clkr = {
1881 		.enable_reg = 0x29068,
1882 		.enable_mask = BIT(0),
1883 		.hw.init = &(const struct clk_init_data) {
1884 			.name = "gcc_pcie3x1_0_pipe_clk",
1885 			.parent_hws = (const struct clk_hw*[]) {
1886 				&gcc_pcie3x1_0_pipe_clk_src.clkr.hw,
1887 			},
1888 			.num_parents = 1,
1889 			.flags = CLK_SET_RATE_PARENT,
1890 			.ops = &clk_branch2_ops,
1891 		},
1892 	},
1893 };
1894 
1895 static struct clk_branch gcc_pcie3x1_1_ahb_clk = {
1896 	.halt_reg = 0x2a00c,
1897 	.halt_check = BRANCH_HALT,
1898 	.clkr = {
1899 		.enable_reg = 0x2a00c,
1900 		.enable_mask = BIT(0),
1901 		.hw.init = &(const struct clk_init_data) {
1902 			.name = "gcc_pcie3x1_1_ahb_clk",
1903 			.parent_hws = (const struct clk_hw*[]) {
1904 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1905 			},
1906 			.num_parents = 1,
1907 			.flags = CLK_SET_RATE_PARENT,
1908 			.ops = &clk_branch2_ops,
1909 		},
1910 	},
1911 };
1912 
1913 static struct clk_branch gcc_pcie3x1_1_aux_clk = {
1914 	.halt_reg = 0x2a070,
1915 	.halt_check = BRANCH_HALT,
1916 	.clkr = {
1917 		.enable_reg = 0x2a070,
1918 		.enable_mask = BIT(0),
1919 		.hw.init = &(const struct clk_init_data) {
1920 			.name = "gcc_pcie3x1_1_aux_clk",
1921 			.parent_hws = (const struct clk_hw*[]) {
1922 				&gcc_pcie_aux_clk_src.clkr.hw,
1923 			},
1924 			.num_parents = 1,
1925 			.flags = CLK_SET_RATE_PARENT,
1926 			.ops = &clk_branch2_ops,
1927 		},
1928 	},
1929 };
1930 
1931 static struct clk_branch gcc_pcie3x1_1_axi_m_clk = {
1932 	.halt_reg = 0x2a014,
1933 	.halt_check = BRANCH_HALT,
1934 	.clkr = {
1935 		.enable_reg = 0x2a014,
1936 		.enable_mask = BIT(0),
1937 		.hw.init = &(const struct clk_init_data) {
1938 			.name = "gcc_pcie3x1_1_axi_m_clk",
1939 			.parent_hws = (const struct clk_hw*[]) {
1940 				&gcc_pcie3x1_1_axi_clk_src.clkr.hw,
1941 			},
1942 			.num_parents = 1,
1943 			.flags = CLK_SET_RATE_PARENT,
1944 			.ops = &clk_branch2_ops,
1945 		},
1946 	},
1947 };
1948 
1949 static struct clk_branch gcc_pcie3x1_1_axi_s_bridge_clk = {
1950 	.halt_reg = 0x2a024,
1951 	.halt_check = BRANCH_HALT,
1952 	.clkr = {
1953 		.enable_reg = 0x2a024,
1954 		.enable_mask = BIT(0),
1955 		.hw.init = &(const struct clk_init_data) {
1956 			.name = "gcc_pcie3x1_1_axi_s_bridge_clk",
1957 			.parent_hws = (const struct clk_hw*[]) {
1958 				&gcc_pcie3x1_1_axi_clk_src.clkr.hw,
1959 			},
1960 			.num_parents = 1,
1961 			.flags = CLK_SET_RATE_PARENT,
1962 			.ops = &clk_branch2_ops,
1963 		},
1964 	},
1965 };
1966 
1967 static struct clk_branch gcc_pcie3x1_1_axi_s_clk = {
1968 	.halt_reg = 0x2a01c,
1969 	.halt_check = BRANCH_HALT,
1970 	.clkr = {
1971 		.enable_reg = 0x2a01c,
1972 		.enable_mask = BIT(0),
1973 		.hw.init = &(const struct clk_init_data) {
1974 			.name = "gcc_pcie3x1_1_axi_s_clk",
1975 			.parent_hws = (const struct clk_hw*[]) {
1976 				&gcc_pcie3x1_1_axi_clk_src.clkr.hw,
1977 			},
1978 			.num_parents = 1,
1979 			.flags = CLK_SET_RATE_PARENT,
1980 			.ops = &clk_branch2_ops,
1981 		},
1982 	},
1983 };
1984 
1985 static struct clk_branch gcc_pcie3x1_1_pipe_clk = {
1986 	.halt_reg = 0x2a068,
1987 	.halt_check = BRANCH_HALT_DELAY,
1988 	.clkr = {
1989 		.enable_reg = 0x2a068,
1990 		.enable_mask = BIT(0),
1991 		.hw.init = &(const struct clk_init_data) {
1992 			.name = "gcc_pcie3x1_1_pipe_clk",
1993 			.parent_hws = (const struct clk_hw*[]) {
1994 				&gcc_pcie3x1_1_pipe_clk_src.clkr.hw,
1995 			},
1996 			.num_parents = 1,
1997 			.flags = CLK_SET_RATE_PARENT,
1998 			.ops = &clk_branch2_ops,
1999 		},
2000 	},
2001 };
2002 
2003 static struct clk_branch gcc_pcie3x1_phy_ahb_clk = {
2004 	.halt_reg = 0x29078,
2005 	.halt_check = BRANCH_HALT,
2006 	.clkr = {
2007 		.enable_reg = 0x29078,
2008 		.enable_mask = BIT(0),
2009 		.hw.init = &(const struct clk_init_data) {
2010 			.name = "gcc_pcie3x1_phy_ahb_clk",
2011 			.parent_hws = (const struct clk_hw*[]) {
2012 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2013 			},
2014 			.num_parents = 1,
2015 			.flags = CLK_SET_RATE_PARENT,
2016 			.ops = &clk_branch2_ops,
2017 		},
2018 	},
2019 };
2020 
2021 static struct clk_branch gcc_pcie3x2_ahb_clk = {
2022 	.halt_reg = 0x28030,
2023 	.halt_check = BRANCH_HALT,
2024 	.clkr = {
2025 		.enable_reg = 0x28030,
2026 		.enable_mask = BIT(0),
2027 		.hw.init = &(const struct clk_init_data) {
2028 			.name = "gcc_pcie3x2_ahb_clk",
2029 			.parent_hws = (const struct clk_hw*[]) {
2030 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2031 			},
2032 			.num_parents = 1,
2033 			.flags = CLK_SET_RATE_PARENT,
2034 			.ops = &clk_branch2_ops,
2035 		},
2036 	},
2037 };
2038 
2039 static struct clk_branch gcc_pcie3x2_aux_clk = {
2040 	.halt_reg = 0x28070,
2041 	.halt_check = BRANCH_HALT,
2042 	.clkr = {
2043 		.enable_reg = 0x28070,
2044 		.enable_mask = BIT(0),
2045 		.hw.init = &(const struct clk_init_data) {
2046 			.name = "gcc_pcie3x2_aux_clk",
2047 			.parent_hws = (const struct clk_hw*[]) {
2048 				&gcc_pcie_aux_clk_src.clkr.hw,
2049 			},
2050 			.num_parents = 1,
2051 			.flags = CLK_SET_RATE_PARENT,
2052 			.ops = &clk_branch2_ops,
2053 		},
2054 	},
2055 };
2056 
2057 static struct clk_branch gcc_pcie3x2_axi_m_clk = {
2058 	.halt_reg = 0x28038,
2059 	.halt_check = BRANCH_HALT,
2060 	.clkr = {
2061 		.enable_reg = 0x28038,
2062 		.enable_mask = BIT(0),
2063 		.hw.init = &(const struct clk_init_data) {
2064 			.name = "gcc_pcie3x2_axi_m_clk",
2065 			.parent_hws = (const struct clk_hw*[]) {
2066 				&gcc_pcie3x2_axi_m_clk_src.clkr.hw,
2067 			},
2068 			.num_parents = 1,
2069 			.flags = CLK_SET_RATE_PARENT,
2070 			.ops = &clk_branch2_ops,
2071 		},
2072 	},
2073 };
2074 
2075 static struct clk_branch gcc_pcie3x2_axi_s_bridge_clk = {
2076 	.halt_reg = 0x28048,
2077 	.halt_check = BRANCH_HALT,
2078 	.clkr = {
2079 		.enable_reg = 0x28048,
2080 		.enable_mask = BIT(0),
2081 		.hw.init = &(const struct clk_init_data) {
2082 			.name = "gcc_pcie3x2_axi_s_bridge_clk",
2083 			.parent_hws = (const struct clk_hw*[]) {
2084 				&gcc_pcie3x2_axi_s_clk_src.clkr.hw,
2085 			},
2086 			.num_parents = 1,
2087 			.flags = CLK_SET_RATE_PARENT,
2088 			.ops = &clk_branch2_ops,
2089 		},
2090 	},
2091 };
2092 
2093 static struct clk_branch gcc_pcie3x2_axi_s_clk = {
2094 	.halt_reg = 0x28040,
2095 	.halt_check = BRANCH_HALT,
2096 	.clkr = {
2097 		.enable_reg = 0x28040,
2098 		.enable_mask = BIT(0),
2099 		.hw.init = &(const struct clk_init_data) {
2100 			.name = "gcc_pcie3x2_axi_s_clk",
2101 			.parent_hws = (const struct clk_hw*[]) {
2102 				&gcc_pcie3x2_axi_s_clk_src.clkr.hw,
2103 			},
2104 			.num_parents = 1,
2105 			.flags = CLK_SET_RATE_PARENT,
2106 			.ops = &clk_branch2_ops,
2107 		},
2108 	},
2109 };
2110 
2111 static struct clk_branch gcc_pcie3x2_phy_ahb_clk = {
2112 	.halt_reg = 0x28080,
2113 	.halt_check = BRANCH_HALT,
2114 	.clkr = {
2115 		.enable_reg = 0x28080,
2116 		.enable_mask = BIT(0),
2117 		.hw.init = &(const struct clk_init_data) {
2118 			.name = "gcc_pcie3x2_phy_ahb_clk",
2119 			.parent_hws = (const struct clk_hw*[]) {
2120 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2121 			},
2122 			.num_parents = 1,
2123 			.flags = CLK_SET_RATE_PARENT,
2124 			.ops = &clk_branch2_ops,
2125 		},
2126 	},
2127 };
2128 
2129 static struct clk_branch gcc_pcie3x2_pipe_clk = {
2130 	.halt_reg = 0x28068,
2131 	.halt_check = BRANCH_HALT_DELAY,
2132 	.clkr = {
2133 		.enable_reg = 0x28068,
2134 		.enable_mask = BIT(0),
2135 		.hw.init = &(const struct clk_init_data) {
2136 			.name = "gcc_pcie3x2_pipe_clk",
2137 			.parent_hws = (const struct clk_hw*[]) {
2138 				&gcc_pcie3x2_pipe_clk_src.clkr.hw,
2139 			},
2140 			.num_parents = 1,
2141 			.flags = CLK_SET_RATE_PARENT,
2142 			.ops = &clk_branch2_ops,
2143 		},
2144 	},
2145 };
2146 
2147 static struct clk_branch gcc_pcnoc_at_clk = {
2148 	.halt_reg = 0x31024,
2149 	.halt_check = BRANCH_HALT_VOTED,
2150 	.clkr = {
2151 		.enable_reg = 0x31024,
2152 		.enable_mask = BIT(0),
2153 		.hw.init = &(const struct clk_init_data) {
2154 			.name = "gcc_pcnoc_at_clk",
2155 			.parent_hws = (const struct clk_hw*[]) {
2156 				&gcc_qdss_at_clk_src.clkr.hw,
2157 			},
2158 			.num_parents = 1,
2159 			.flags = CLK_SET_RATE_PARENT,
2160 			.ops = &clk_branch2_ops,
2161 		},
2162 	},
2163 };
2164 
2165 static struct clk_branch gcc_pcnoc_lpass_clk = {
2166 	.halt_reg = 0x31020,
2167 	.halt_check = BRANCH_HALT,
2168 	.clkr = {
2169 		.enable_reg = 0x31020,
2170 		.enable_mask = BIT(0),
2171 		.hw.init = &(const struct clk_init_data) {
2172 			.name = "gcc_pcnoc_lpass_clk",
2173 			.parent_hws = (const struct clk_hw*[]) {
2174 				&gcc_lpass_sway_clk_src.clkr.hw,
2175 			},
2176 			.num_parents = 1,
2177 			.flags = CLK_SET_RATE_PARENT,
2178 			.ops = &clk_branch2_ops,
2179 		},
2180 	},
2181 };
2182 
2183 static struct clk_branch gcc_prng_ahb_clk = {
2184 	.halt_reg = 0x13024,
2185 	.halt_check = BRANCH_HALT_VOTED,
2186 	.clkr = {
2187 		.enable_reg = 0xb004,
2188 		.enable_mask = BIT(10),
2189 		.hw.init = &(const struct clk_init_data) {
2190 			.name = "gcc_prng_ahb_clk",
2191 			.parent_hws = (const struct clk_hw*[]) {
2192 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2193 			},
2194 			.num_parents = 1,
2195 			.flags = CLK_SET_RATE_PARENT,
2196 			.ops = &clk_branch2_ops,
2197 		},
2198 	},
2199 };
2200 
2201 static struct clk_branch gcc_q6_ahb_clk = {
2202 	.halt_reg = 0x25014,
2203 	.halt_check = BRANCH_HALT_VOTED,
2204 	.clkr = {
2205 		.enable_reg = 0x25014,
2206 		.enable_mask = BIT(0),
2207 		.hw.init = &(const struct clk_init_data) {
2208 			.name = "gcc_q6_ahb_clk",
2209 			.parent_hws = (const struct clk_hw*[]) {
2210 				&gcc_wcss_ahb_clk_src.clkr.hw,
2211 			},
2212 			.num_parents = 1,
2213 			.flags = CLK_SET_RATE_PARENT,
2214 			.ops = &clk_branch2_ops,
2215 		},
2216 	},
2217 };
2218 
2219 static struct clk_branch gcc_q6_ahb_s_clk = {
2220 	.halt_reg = 0x25018,
2221 	.halt_check = BRANCH_HALT_VOTED,
2222 	.clkr = {
2223 		.enable_reg = 0x25018,
2224 		.enable_mask = BIT(0),
2225 		.hw.init = &(const struct clk_init_data) {
2226 			.name = "gcc_q6_ahb_s_clk",
2227 			.parent_hws = (const struct clk_hw*[]) {
2228 				&gcc_wcss_ahb_clk_src.clkr.hw,
2229 			},
2230 			.num_parents = 1,
2231 			.flags = CLK_SET_RATE_PARENT,
2232 			.ops = &clk_branch2_ops,
2233 		},
2234 	},
2235 };
2236 
2237 static struct clk_branch gcc_q6_axim_clk = {
2238 	.halt_reg = 0x2500c,
2239 	.halt_check = BRANCH_HALT_VOTED,
2240 	.clkr = {
2241 		.enable_reg = 0x2500c,
2242 		.enable_mask = BIT(0),
2243 		.hw.init = &(const struct clk_init_data) {
2244 			.name = "gcc_q6_axim_clk",
2245 			.parent_hws = (const struct clk_hw*[]) {
2246 				&gcc_q6_axim_clk_src.clkr.hw,
2247 			},
2248 			.num_parents = 1,
2249 			.flags = CLK_SET_RATE_PARENT,
2250 			.ops = &clk_branch2_ops,
2251 		},
2252 	},
2253 };
2254 
2255 static struct clk_branch gcc_q6_axis_clk = {
2256 	.halt_reg = 0x25010,
2257 	.halt_check = BRANCH_HALT_VOTED,
2258 	.clkr = {
2259 		.enable_reg = 0x25010,
2260 		.enable_mask = BIT(0),
2261 		.hw.init = &(const struct clk_init_data) {
2262 			.name = "gcc_q6_axis_clk",
2263 			.parent_hws = (const struct clk_hw*[]) {
2264 				&gcc_system_noc_bfdcd_clk_src.clkr.hw,
2265 			},
2266 			.num_parents = 1,
2267 			.flags = CLK_SET_RATE_PARENT,
2268 			.ops = &clk_branch2_ops,
2269 		},
2270 	},
2271 };
2272 
2273 static struct clk_branch gcc_q6_tsctr_1to2_clk = {
2274 	.halt_reg = 0x25020,
2275 	.halt_check = BRANCH_HALT_VOTED,
2276 	.clkr = {
2277 		.enable_reg = 0x25020,
2278 		.enable_mask = BIT(0),
2279 		.hw.init = &(const struct clk_init_data) {
2280 			.name = "gcc_q6_tsctr_1to2_clk",
2281 			.parent_hws = (const struct clk_hw*[]) {
2282 				&gcc_qdss_tsctr_div2_clk_src.hw,
2283 			},
2284 			.num_parents = 1,
2285 			.flags = CLK_SET_RATE_PARENT,
2286 			.ops = &clk_branch2_ops,
2287 		},
2288 	},
2289 };
2290 
2291 static struct clk_branch gcc_q6ss_atbm_clk = {
2292 	.halt_reg = 0x2501c,
2293 	.halt_check = BRANCH_HALT_VOTED,
2294 	.clkr = {
2295 		.enable_reg = 0x2501c,
2296 		.enable_mask = BIT(0),
2297 		.hw.init = &(const struct clk_init_data) {
2298 			.name = "gcc_q6ss_atbm_clk",
2299 			.parent_hws = (const struct clk_hw*[]) {
2300 				&gcc_qdss_at_clk_src.clkr.hw,
2301 			},
2302 			.num_parents = 1,
2303 			.flags = CLK_SET_RATE_PARENT,
2304 			.ops = &clk_branch2_ops,
2305 		},
2306 	},
2307 };
2308 
2309 static struct clk_branch gcc_q6ss_pclkdbg_clk = {
2310 	.halt_reg = 0x25024,
2311 	.halt_check = BRANCH_HALT_VOTED,
2312 	.clkr = {
2313 		.enable_reg = 0x25024,
2314 		.enable_mask = BIT(0),
2315 		.hw.init = &(const struct clk_init_data) {
2316 			.name = "gcc_q6ss_pclkdbg_clk",
2317 			.parent_hws = (const struct clk_hw*[]) {
2318 				&gcc_qdss_dap_div_clk_src.clkr.hw,
2319 			},
2320 			.num_parents = 1,
2321 			.flags = CLK_SET_RATE_PARENT,
2322 			.ops = &clk_branch2_ops,
2323 		},
2324 	},
2325 };
2326 
2327 static struct clk_branch gcc_q6ss_trig_clk = {
2328 	.halt_reg = 0x250a0,
2329 	.halt_check = BRANCH_HALT_VOTED,
2330 	.clkr = {
2331 		.enable_reg = 0x250a0,
2332 		.enable_mask = BIT(0),
2333 		.hw.init = &(const struct clk_init_data) {
2334 			.name = "gcc_q6ss_trig_clk",
2335 			.parent_hws = (const struct clk_hw*[]) {
2336 				&gcc_qdss_dap_div_clk_src.clkr.hw,
2337 			},
2338 			.num_parents = 1,
2339 			.flags = CLK_SET_RATE_PARENT,
2340 			.ops = &clk_branch2_ops,
2341 		},
2342 	},
2343 };
2344 
2345 static struct clk_branch gcc_qdss_at_clk = {
2346 	.halt_reg = 0x2d038,
2347 	.halt_check = BRANCH_HALT_VOTED,
2348 	.clkr = {
2349 		.enable_reg = 0x2d038,
2350 		.enable_mask = BIT(0),
2351 		.hw.init = &(const struct clk_init_data) {
2352 			.name = "gcc_qdss_at_clk",
2353 			.parent_hws = (const struct clk_hw*[]) {
2354 				&gcc_qdss_at_clk_src.clkr.hw,
2355 			},
2356 			.num_parents = 1,
2357 			.flags = CLK_SET_RATE_PARENT,
2358 			.ops = &clk_branch2_ops,
2359 		},
2360 	},
2361 };
2362 
2363 static struct clk_branch gcc_qdss_cfg_ahb_clk = {
2364 	.halt_reg = 0x2d06c,
2365 	.halt_check = BRANCH_HALT_VOTED,
2366 	.clkr = {
2367 		.enable_reg = 0x2d06c,
2368 		.enable_mask = BIT(0),
2369 		.hw.init = &(const struct clk_init_data) {
2370 			.name = "gcc_qdss_cfg_ahb_clk",
2371 			.parent_hws = (const struct clk_hw*[]) {
2372 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2373 			},
2374 			.num_parents = 1,
2375 			.flags = CLK_SET_RATE_PARENT,
2376 			.ops = &clk_branch2_ops,
2377 		},
2378 	},
2379 };
2380 
2381 static struct clk_branch gcc_qdss_dap_ahb_clk = {
2382 	.halt_reg = 0x2d068,
2383 	.halt_check = BRANCH_HALT_VOTED,
2384 	.clkr = {
2385 		.enable_reg = 0x2d068,
2386 		.enable_mask = BIT(0),
2387 		.hw.init = &(const struct clk_init_data) {
2388 			.name = "gcc_qdss_dap_ahb_clk",
2389 			.parent_hws = (const struct clk_hw*[]) {
2390 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2391 			},
2392 			.num_parents = 1,
2393 			.flags = CLK_SET_RATE_PARENT,
2394 			.ops = &clk_branch2_ops,
2395 		},
2396 	},
2397 };
2398 
2399 static struct clk_branch gcc_qdss_dap_clk = {
2400 	.halt_reg = 0x2d05c,
2401 	.halt_check = BRANCH_HALT_VOTED,
2402 	.clkr = {
2403 		.enable_reg = 0xb004,
2404 		.enable_mask = BIT(2),
2405 		.hw.init = &(const struct clk_init_data) {
2406 			.name = "gcc_qdss_dap_clk",
2407 			.parent_hws = (const struct clk_hw*[]) {
2408 				&gcc_qdss_dap_div_clk_src.clkr.hw,
2409 			},
2410 			.num_parents = 1,
2411 			.flags = CLK_SET_RATE_PARENT,
2412 			.ops = &clk_branch2_ops,
2413 		},
2414 	},
2415 };
2416 
2417 static struct clk_branch gcc_qdss_etr_usb_clk = {
2418 	.halt_reg = 0x2d064,
2419 	.halt_check = BRANCH_HALT_VOTED,
2420 	.clkr = {
2421 		.enable_reg = 0x2d064,
2422 		.enable_mask = BIT(0),
2423 		.hw.init = &(const struct clk_init_data) {
2424 			.name = "gcc_qdss_etr_usb_clk",
2425 			.parent_hws = (const struct clk_hw*[]) {
2426 				&gcc_system_noc_bfdcd_clk_src.clkr.hw,
2427 			},
2428 			.num_parents = 1,
2429 			.flags = CLK_SET_RATE_PARENT,
2430 			.ops = &clk_branch2_ops,
2431 		},
2432 	},
2433 };
2434 
2435 static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
2436 	.mult = 1,
2437 	.div = 6,
2438 	.hw.init = &(struct clk_init_data) {
2439 		.name = "gcc_eud_at_div_clk_src",
2440 		.parent_hws = (const struct clk_hw *[]) {
2441 				&gcc_qdss_at_clk_src.clkr.hw },
2442 		.num_parents = 1,
2443 		.flags = CLK_SET_RATE_PARENT,
2444 		.ops = &clk_fixed_factor_ops,
2445 	},
2446 };
2447 
2448 static struct clk_branch gcc_qdss_eud_at_clk = {
2449 	.halt_reg = 0x2d070,
2450 	.halt_check = BRANCH_HALT_VOTED,
2451 	.clkr = {
2452 		.enable_reg = 0x2d070,
2453 		.enable_mask = BIT(0),
2454 		.hw.init = &(const struct clk_init_data) {
2455 			.name = "gcc_qdss_eud_at_clk",
2456 			.parent_hws = (const struct clk_hw*[]) {
2457 				&gcc_eud_at_div_clk_src.hw,
2458 			},
2459 			.num_parents = 1,
2460 			.flags = CLK_SET_RATE_PARENT,
2461 			.ops = &clk_branch2_ops,
2462 		},
2463 	},
2464 };
2465 
2466 static struct clk_branch gcc_qpic_ahb_clk = {
2467 	.halt_reg = 0x32010,
2468 	.halt_check = BRANCH_HALT,
2469 	.clkr = {
2470 		.enable_reg = 0x32010,
2471 		.enable_mask = BIT(0),
2472 		.hw.init = &(const struct clk_init_data) {
2473 			.name = "gcc_qpic_ahb_clk",
2474 			.parent_hws = (const struct clk_hw*[]) {
2475 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2476 			},
2477 			.num_parents = 1,
2478 			.flags = CLK_SET_RATE_PARENT,
2479 			.ops = &clk_branch2_ops,
2480 		},
2481 	},
2482 };
2483 
2484 static struct clk_branch gcc_qpic_clk = {
2485 	.halt_reg = 0x32014,
2486 	.halt_check = BRANCH_HALT,
2487 	.clkr = {
2488 		.enable_reg = 0x32014,
2489 		.enable_mask = BIT(0),
2490 		.hw.init = &(const struct clk_init_data) {
2491 			.name = "gcc_qpic_clk",
2492 			.parent_hws = (const struct clk_hw*[]) {
2493 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2494 			},
2495 			.num_parents = 1,
2496 			.flags = CLK_SET_RATE_PARENT,
2497 			.ops = &clk_branch2_ops,
2498 		},
2499 	},
2500 };
2501 
2502 static struct clk_branch gcc_qpic_io_macro_clk = {
2503 	.halt_reg = 0x3200c,
2504 	.halt_check = BRANCH_HALT,
2505 	.clkr = {
2506 		.enable_reg = 0x3200c,
2507 		.enable_mask = BIT(0),
2508 		.hw.init = &(const struct clk_init_data) {
2509 			.name = "gcc_qpic_io_macro_clk",
2510 			.parent_hws = (const struct clk_hw*[]) {
2511 				&gcc_qpic_io_macro_clk_src.clkr.hw,
2512 			},
2513 			.num_parents = 1,
2514 			.flags = CLK_SET_RATE_PARENT,
2515 			.ops = &clk_branch2_ops,
2516 		},
2517 	},
2518 };
2519 
2520 static struct clk_branch gcc_qpic_sleep_clk = {
2521 	.halt_reg = 0x3201c,
2522 	.halt_check = BRANCH_HALT,
2523 	.clkr = {
2524 		.enable_reg = 0x3201c,
2525 		.enable_mask = BIT(0),
2526 		.hw.init = &(const struct clk_init_data) {
2527 			.name = "gcc_qpic_sleep_clk",
2528 			.parent_hws = (const struct clk_hw*[]) {
2529 				&gcc_sleep_clk_src.clkr.hw,
2530 			},
2531 			.num_parents = 1,
2532 			.flags = CLK_SET_RATE_PARENT,
2533 			.ops = &clk_branch2_ops,
2534 		},
2535 	},
2536 };
2537 
2538 static struct clk_branch gcc_sdcc1_ahb_clk = {
2539 	.halt_reg = 0x33034,
2540 	.halt_check = BRANCH_HALT,
2541 	.clkr = {
2542 		.enable_reg = 0x33034,
2543 		.enable_mask = BIT(0),
2544 		.hw.init = &(const struct clk_init_data) {
2545 			.name = "gcc_sdcc1_ahb_clk",
2546 			.parent_hws = (const struct clk_hw*[]) {
2547 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2548 			},
2549 			.num_parents = 1,
2550 			.flags = CLK_SET_RATE_PARENT,
2551 			.ops = &clk_branch2_ops,
2552 		},
2553 	},
2554 };
2555 
2556 static struct clk_branch gcc_sdcc1_apps_clk = {
2557 	.halt_reg = 0x3302c,
2558 	.halt_check = BRANCH_HALT,
2559 	.clkr = {
2560 		.enable_reg = 0x3302c,
2561 		.enable_mask = BIT(0),
2562 		.hw.init = &(const struct clk_init_data) {
2563 			.name = "gcc_sdcc1_apps_clk",
2564 			.parent_hws = (const struct clk_hw*[]) {
2565 				&gcc_sdcc1_apps_clk_src.clkr.hw,
2566 			},
2567 			.num_parents = 1,
2568 			.flags = CLK_SET_RATE_PARENT,
2569 			.ops = &clk_branch2_ops,
2570 		},
2571 	},
2572 };
2573 
2574 static struct clk_branch gcc_snoc_lpass_cfg_clk = {
2575 	.halt_reg = 0x2e028,
2576 	.halt_check = BRANCH_HALT,
2577 	.clkr = {
2578 		.enable_reg = 0x2e028,
2579 		.enable_mask = BIT(0),
2580 		.hw.init = &(const struct clk_init_data) {
2581 			.name = "gcc_snoc_lpass_cfg_clk",
2582 			.parent_hws = (const struct clk_hw*[]) {
2583 				&gcc_lpass_sway_clk_src.clkr.hw,
2584 			},
2585 			.num_parents = 1,
2586 			.flags = CLK_SET_RATE_PARENT,
2587 			.ops = &clk_branch2_ops,
2588 		},
2589 	},
2590 };
2591 
2592 static struct clk_branch gcc_snoc_nssnoc_1_clk = {
2593 	.halt_reg = 0x17090,
2594 	.halt_check = BRANCH_HALT,
2595 	.clkr = {
2596 		.enable_reg = 0x17090,
2597 		.enable_mask = BIT(0),
2598 		.hw.init = &(const struct clk_init_data) {
2599 			.name = "gcc_snoc_nssnoc_1_clk",
2600 			.parent_hws = (const struct clk_hw*[]) {
2601 				&gcc_system_noc_bfdcd_clk_src.clkr.hw,
2602 			},
2603 			.num_parents = 1,
2604 			.flags = CLK_SET_RATE_PARENT,
2605 			.ops = &clk_branch2_ops,
2606 		},
2607 	},
2608 };
2609 
2610 static struct clk_branch gcc_snoc_nssnoc_clk = {
2611 	.halt_reg = 0x17084,
2612 	.halt_check = BRANCH_HALT,
2613 	.clkr = {
2614 		.enable_reg = 0x17084,
2615 		.enable_mask = BIT(0),
2616 		.hw.init = &(const struct clk_init_data) {
2617 			.name = "gcc_snoc_nssnoc_clk",
2618 			.parent_hws = (const struct clk_hw*[]) {
2619 				&gcc_system_noc_bfdcd_clk_src.clkr.hw,
2620 			},
2621 			.num_parents = 1,
2622 			.flags = CLK_SET_RATE_PARENT,
2623 			.ops = &clk_branch2_ops,
2624 		},
2625 	},
2626 };
2627 
2628 static struct clk_branch gcc_snoc_pcie3_1lane_1_m_clk = {
2629 	.halt_reg = 0x2e050,
2630 	.halt_check = BRANCH_HALT,
2631 	.clkr = {
2632 		.enable_reg = 0x2e050,
2633 		.enable_mask = BIT(0),
2634 		.hw.init = &(const struct clk_init_data) {
2635 			.name = "gcc_snoc_pcie3_1lane_1_m_clk",
2636 			.parent_hws = (const struct clk_hw*[]) {
2637 				&gcc_pcie3x1_1_axi_clk_src.clkr.hw,
2638 			},
2639 			.num_parents = 1,
2640 			.flags = CLK_SET_RATE_PARENT,
2641 			.ops = &clk_branch2_ops,
2642 		},
2643 	},
2644 };
2645 
2646 static struct clk_branch gcc_snoc_pcie3_1lane_1_s_clk = {
2647 	.halt_reg = 0x2e0ac,
2648 	.halt_check = BRANCH_HALT,
2649 	.clkr = {
2650 		.enable_reg = 0x2e0ac,
2651 		.enable_mask = BIT(0),
2652 		.hw.init = &(const struct clk_init_data) {
2653 			.name = "gcc_snoc_pcie3_1lane_1_s_clk",
2654 			.parent_hws = (const struct clk_hw*[]) {
2655 				&gcc_pcie3x1_1_axi_clk_src.clkr.hw,
2656 			},
2657 			.num_parents = 1,
2658 			.flags = CLK_SET_RATE_PARENT,
2659 			.ops = &clk_branch2_ops,
2660 		},
2661 	},
2662 };
2663 
2664 static struct clk_branch gcc_snoc_pcie3_1lane_m_clk = {
2665 	.halt_reg = 0x2e080,
2666 	.halt_check = BRANCH_HALT,
2667 	.clkr = {
2668 		.enable_reg = 0x2e080,
2669 		.enable_mask = BIT(0),
2670 		.hw.init = &(const struct clk_init_data) {
2671 			.name = "gcc_snoc_pcie3_1lane_m_clk",
2672 			.parent_hws = (const struct clk_hw*[]) {
2673 				&gcc_pcie3x1_0_axi_clk_src.clkr.hw,
2674 			},
2675 			.num_parents = 1,
2676 			.flags = CLK_SET_RATE_PARENT,
2677 			.ops = &clk_branch2_ops,
2678 		},
2679 	},
2680 };
2681 
2682 static struct clk_branch gcc_snoc_pcie3_1lane_s_clk = {
2683 	.halt_reg = 0x2e04c,
2684 	.halt_check = BRANCH_HALT,
2685 	.clkr = {
2686 		.enable_reg = 0x2e04c,
2687 		.enable_mask = BIT(0),
2688 		.hw.init = &(const struct clk_init_data) {
2689 			.name = "gcc_snoc_pcie3_1lane_s_clk",
2690 			.parent_hws = (const struct clk_hw*[]) {
2691 				&gcc_pcie3x1_0_axi_clk_src.clkr.hw,
2692 			},
2693 			.num_parents = 1,
2694 			.flags = CLK_SET_RATE_PARENT,
2695 			.ops = &clk_branch2_ops,
2696 		},
2697 	},
2698 };
2699 
2700 static struct clk_branch gcc_snoc_pcie3_2lane_m_clk = {
2701 	.halt_reg = 0x2e07c,
2702 	.halt_check = BRANCH_HALT,
2703 	.clkr = {
2704 		.enable_reg = 0x2e07c,
2705 		.enable_mask = BIT(0),
2706 		.hw.init = &(const struct clk_init_data) {
2707 			.name = "gcc_snoc_pcie3_2lane_m_clk",
2708 			.parent_hws = (const struct clk_hw*[]) {
2709 				&gcc_pcie3x2_axi_m_clk_src.clkr.hw,
2710 			},
2711 			.num_parents = 1,
2712 			.flags = CLK_SET_RATE_PARENT,
2713 			.ops = &clk_branch2_ops,
2714 		},
2715 	},
2716 };
2717 
2718 static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = {
2719 	.halt_reg = 0x2e048,
2720 	.halt_check = BRANCH_HALT,
2721 	.clkr = {
2722 		.enable_reg = 0x2e048,
2723 		.enable_mask = BIT(0),
2724 		.hw.init = &(const struct clk_init_data) {
2725 			.name = "gcc_snoc_pcie3_2lane_s_clk",
2726 			.parent_hws = (const struct clk_hw*[]) {
2727 				&gcc_pcie3x2_axi_s_clk_src.clkr.hw,
2728 			},
2729 			.num_parents = 1,
2730 			.flags = CLK_SET_RATE_PARENT,
2731 			.ops = &clk_branch2_ops,
2732 		},
2733 	},
2734 };
2735 
2736 static struct clk_branch gcc_snoc_usb_clk = {
2737 	.halt_reg = 0x2e058,
2738 	.halt_check = BRANCH_HALT_VOTED,
2739 	.clkr = {
2740 		.enable_reg = 0x2e058,
2741 		.enable_mask = BIT(0),
2742 		.hw.init = &(const struct clk_init_data) {
2743 			.name = "gcc_snoc_usb_clk",
2744 			.parent_hws = (const struct clk_hw*[]) {
2745 				&gcc_usb0_master_clk_src.clkr.hw,
2746 			},
2747 			.num_parents = 1,
2748 			.flags = CLK_SET_RATE_PARENT,
2749 			.ops = &clk_branch2_ops,
2750 		},
2751 	},
2752 };
2753 
2754 static struct clk_branch gcc_sys_noc_at_clk = {
2755 	.halt_reg = 0x2e038,
2756 	.halt_check = BRANCH_HALT_VOTED,
2757 	.clkr = {
2758 		.enable_reg = 0x2e038,
2759 		.enable_mask = BIT(0),
2760 		.hw.init = &(const struct clk_init_data) {
2761 			.name = "gcc_sys_noc_at_clk",
2762 			.parent_hws = (const struct clk_hw*[]) {
2763 				&gcc_qdss_at_clk_src.clkr.hw,
2764 			},
2765 			.num_parents = 1,
2766 			.flags = CLK_SET_RATE_PARENT,
2767 			.ops = &clk_branch2_ops,
2768 		},
2769 	},
2770 };
2771 
2772 static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
2773 	.halt_reg = 0x2e030,
2774 	.halt_check = BRANCH_HALT,
2775 	.clkr = {
2776 		.enable_reg = 0x2e030,
2777 		.enable_mask = BIT(0),
2778 		.hw.init = &(const struct clk_init_data) {
2779 			.name = "gcc_sys_noc_wcss_ahb_clk",
2780 			.parent_hws = (const struct clk_hw*[]) {
2781 				&gcc_wcss_ahb_clk_src.clkr.hw,
2782 			},
2783 			.num_parents = 1,
2784 			.flags = CLK_SET_RATE_PARENT,
2785 			.ops = &clk_branch2_ops,
2786 		},
2787 	},
2788 };
2789 
2790 static struct clk_branch gcc_uniphy0_ahb_clk = {
2791 	.halt_reg = 0x16010,
2792 	.halt_check = BRANCH_HALT,
2793 	.clkr = {
2794 		.enable_reg = 0x16010,
2795 		.enable_mask = BIT(0),
2796 		.hw.init = &(const struct clk_init_data) {
2797 			.name = "gcc_uniphy0_ahb_clk",
2798 			.parent_hws = (const struct clk_hw*[]) {
2799 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2800 			},
2801 			.num_parents = 1,
2802 			.flags = CLK_SET_RATE_PARENT,
2803 			.ops = &clk_branch2_ops,
2804 		},
2805 	},
2806 };
2807 
2808 static struct clk_branch gcc_uniphy0_sys_clk = {
2809 	.halt_reg = 0x1600c,
2810 	.halt_check = BRANCH_HALT,
2811 	.clkr = {
2812 		.enable_reg = 0x1600c,
2813 		.enable_mask = BIT(0),
2814 		.hw.init = &(const struct clk_init_data) {
2815 			.name = "gcc_uniphy0_sys_clk",
2816 			.parent_hws = (const struct clk_hw*[]) {
2817 				&gcc_uniphy_sys_clk_src.clkr.hw,
2818 			},
2819 			.num_parents = 1,
2820 			.flags = CLK_SET_RATE_PARENT,
2821 			.ops = &clk_branch2_ops,
2822 		},
2823 	},
2824 };
2825 
2826 static struct clk_branch gcc_uniphy1_ahb_clk = {
2827 	.halt_reg = 0x1601c,
2828 	.halt_check = BRANCH_HALT,
2829 	.clkr = {
2830 		.enable_reg = 0x1601c,
2831 		.enable_mask = BIT(0),
2832 		.hw.init = &(const struct clk_init_data) {
2833 			.name = "gcc_uniphy1_ahb_clk",
2834 			.parent_hws = (const struct clk_hw*[]) {
2835 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2836 			},
2837 			.num_parents = 1,
2838 			.flags = CLK_SET_RATE_PARENT,
2839 			.ops = &clk_branch2_ops,
2840 		},
2841 	},
2842 };
2843 
2844 static struct clk_branch gcc_uniphy1_sys_clk = {
2845 	.halt_reg = 0x16018,
2846 	.halt_check = BRANCH_HALT,
2847 	.clkr = {
2848 		.enable_reg = 0x16018,
2849 		.enable_mask = BIT(0),
2850 		.hw.init = &(const struct clk_init_data) {
2851 			.name = "gcc_uniphy1_sys_clk",
2852 			.parent_hws = (const struct clk_hw*[]) {
2853 				&gcc_uniphy_sys_clk_src.clkr.hw,
2854 			},
2855 			.num_parents = 1,
2856 			.flags = CLK_SET_RATE_PARENT,
2857 			.ops = &clk_branch2_ops,
2858 		},
2859 	},
2860 };
2861 
2862 static struct clk_branch gcc_usb0_aux_clk = {
2863 	.halt_reg = 0x2c050,
2864 	.halt_check = BRANCH_HALT_VOTED,
2865 	.clkr = {
2866 		.enable_reg = 0x2c050,
2867 		.enable_mask = BIT(0),
2868 		.hw.init = &(const struct clk_init_data) {
2869 			.name = "gcc_usb0_aux_clk",
2870 			.parent_hws = (const struct clk_hw*[]) {
2871 				&gcc_usb0_aux_clk_src.clkr.hw,
2872 			},
2873 			.num_parents = 1,
2874 			.flags = CLK_SET_RATE_PARENT,
2875 			.ops = &clk_branch2_ops,
2876 		},
2877 	},
2878 };
2879 
2880 static struct clk_branch gcc_usb0_eud_at_clk = {
2881 	.halt_reg = 0x30004,
2882 	.halt_check = BRANCH_HALT_VOTED,
2883 	.clkr = {
2884 		.enable_reg = 0x30004,
2885 		.enable_mask = BIT(0),
2886 		.hw.init = &(const struct clk_init_data) {
2887 			.name = "gcc_usb0_eud_at_clk",
2888 			.parent_hws = (const struct clk_hw*[]) {
2889 				&gcc_eud_at_div_clk_src.hw,
2890 			},
2891 			.num_parents = 1,
2892 			.flags = CLK_SET_RATE_PARENT,
2893 			.ops = &clk_branch2_ops,
2894 		},
2895 	},
2896 };
2897 
2898 static struct clk_branch gcc_usb0_lfps_clk = {
2899 	.halt_reg = 0x2c090,
2900 	.halt_check = BRANCH_HALT_VOTED,
2901 	.clkr = {
2902 		.enable_reg = 0x2c090,
2903 		.enable_mask = BIT(0),
2904 		.hw.init = &(const struct clk_init_data) {
2905 			.name = "gcc_usb0_lfps_clk",
2906 			.parent_hws = (const struct clk_hw*[]) {
2907 				&gcc_usb0_lfps_clk_src.clkr.hw,
2908 			},
2909 			.num_parents = 1,
2910 			.flags = CLK_SET_RATE_PARENT,
2911 			.ops = &clk_branch2_ops,
2912 		},
2913 	},
2914 };
2915 
2916 static struct clk_branch gcc_usb0_master_clk = {
2917 	.halt_reg = 0x2c048,
2918 	.halt_check = BRANCH_HALT_VOTED,
2919 	.clkr = {
2920 		.enable_reg = 0x2c048,
2921 		.enable_mask = BIT(0),
2922 		.hw.init = &(const struct clk_init_data) {
2923 			.name = "gcc_usb0_master_clk",
2924 			.parent_hws = (const struct clk_hw*[]) {
2925 				&gcc_usb0_master_clk_src.clkr.hw,
2926 			},
2927 			.num_parents = 1,
2928 			.flags = CLK_SET_RATE_PARENT,
2929 			.ops = &clk_branch2_ops,
2930 		},
2931 	},
2932 };
2933 
2934 static struct clk_branch gcc_usb0_mock_utmi_clk = {
2935 	.halt_reg = 0x2c054,
2936 	.clkr = {
2937 		.enable_reg = 0x2c054,
2938 		.enable_mask = BIT(0),
2939 		.hw.init = &(const struct clk_init_data) {
2940 			.name = "gcc_usb0_mock_utmi_clk",
2941 			.parent_hws = (const struct clk_hw*[]) {
2942 				&gcc_usb0_mock_utmi_div_clk_src.clkr.hw,
2943 			},
2944 			.num_parents = 1,
2945 			.flags = CLK_SET_RATE_PARENT,
2946 			.ops = &clk_branch2_ops,
2947 		},
2948 	},
2949 };
2950 
2951 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2952 	.halt_reg = 0x2c05c,
2953 	.halt_check = BRANCH_HALT_VOTED,
2954 	.clkr = {
2955 		.enable_reg = 0x2c05c,
2956 		.enable_mask = BIT(0),
2957 		.hw.init = &(const struct clk_init_data) {
2958 			.name = "gcc_usb0_phy_cfg_ahb_clk",
2959 			.parent_hws = (const struct clk_hw*[]) {
2960 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2961 			},
2962 			.num_parents = 1,
2963 			.flags = CLK_SET_RATE_PARENT,
2964 			.ops = &clk_branch2_ops,
2965 		},
2966 	},
2967 };
2968 
2969 static struct clk_branch gcc_usb0_pipe_clk = {
2970 	.halt_reg = 0x2c078,
2971 	.halt_check = BRANCH_HALT_DELAY,
2972 	.clkr = {
2973 		.enable_reg = 0x2c078,
2974 		.enable_mask = BIT(0),
2975 		.hw.init = &(const struct clk_init_data) {
2976 			.name = "gcc_usb0_pipe_clk",
2977 			.parent_hws = (const struct clk_hw*[]) {
2978 				&gcc_usb0_pipe_clk_src.clkr.hw,
2979 			},
2980 			.num_parents = 1,
2981 			.flags = CLK_SET_RATE_PARENT,
2982 			.ops = &clk_branch2_ops,
2983 		},
2984 	},
2985 };
2986 
2987 static struct clk_branch gcc_usb0_sleep_clk = {
2988 	.halt_reg = 0x2c058,
2989 	.halt_check = BRANCH_HALT_VOTED,
2990 	.clkr = {
2991 		.enable_reg = 0x2c058,
2992 		.enable_mask = BIT(0),
2993 		.hw.init = &(const struct clk_init_data) {
2994 			.name = "gcc_usb0_sleep_clk",
2995 			.parent_hws = (const struct clk_hw*[]) {
2996 				&gcc_sleep_clk_src.clkr.hw,
2997 			},
2998 			.num_parents = 1,
2999 			.flags = CLK_SET_RATE_PARENT,
3000 			.ops = &clk_branch2_ops,
3001 		},
3002 	},
3003 };
3004 
3005 static struct clk_branch gcc_wcss_axim_clk = {
3006 	.halt_reg = 0x2505c,
3007 	.halt_check = BRANCH_HALT,
3008 	.clkr = {
3009 		.enable_reg = 0x2505c,
3010 		.enable_mask = BIT(0),
3011 		.hw.init = &(const struct clk_init_data) {
3012 			.name = "gcc_wcss_axim_clk",
3013 			.parent_hws = (const struct clk_hw*[]) {
3014 				&gcc_system_noc_bfdcd_clk_src.clkr.hw,
3015 			},
3016 			.num_parents = 1,
3017 			.flags = CLK_SET_RATE_PARENT,
3018 			.ops = &clk_branch2_ops,
3019 		},
3020 	},
3021 };
3022 
3023 static struct clk_branch gcc_wcss_axis_clk = {
3024 	.halt_reg = 0x25060,
3025 	.halt_check = BRANCH_HALT,
3026 	.clkr = {
3027 		.enable_reg = 0x25060,
3028 		.enable_mask = BIT(0),
3029 		.hw.init = &(const struct clk_init_data) {
3030 			.name = "gcc_wcss_axis_clk",
3031 			.parent_hws = (const struct clk_hw*[]) {
3032 				&gcc_system_noc_bfdcd_clk_src.clkr.hw,
3033 			},
3034 			.num_parents = 1,
3035 			.flags = CLK_SET_RATE_PARENT,
3036 			.ops = &clk_branch2_ops,
3037 		},
3038 	},
3039 };
3040 
3041 static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {
3042 	.halt_reg = 0x25048,
3043 	.halt_check = BRANCH_HALT,
3044 	.clkr = {
3045 		.enable_reg = 0x25048,
3046 		.enable_mask = BIT(0),
3047 		.hw.init = &(const struct clk_init_data) {
3048 			.name = "gcc_wcss_dbg_ifc_apb_bdg_clk",
3049 			.parent_hws = (const struct clk_hw*[]) {
3050 				&gcc_qdss_dap_div_clk_src.clkr.hw,
3051 			},
3052 			.num_parents = 1,
3053 			.flags = CLK_SET_RATE_PARENT,
3054 			.ops = &clk_branch2_ops,
3055 		},
3056 	},
3057 };
3058 
3059 static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
3060 	.halt_reg = 0x25038,
3061 	.halt_check = BRANCH_HALT,
3062 	.clkr = {
3063 		.enable_reg = 0x25038,
3064 		.enable_mask = BIT(0),
3065 		.hw.init = &(const struct clk_init_data) {
3066 			.name = "gcc_wcss_dbg_ifc_apb_clk",
3067 			.parent_hws = (const struct clk_hw*[]) {
3068 				&gcc_qdss_dap_div_clk_src.clkr.hw,
3069 			},
3070 			.num_parents = 1,
3071 			.flags = CLK_SET_RATE_PARENT,
3072 			.ops = &clk_branch2_ops,
3073 		},
3074 	},
3075 };
3076 
3077 static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {
3078 	.halt_reg = 0x2504c,
3079 	.halt_check = BRANCH_HALT,
3080 	.clkr = {
3081 		.enable_reg = 0x2504c,
3082 		.enable_mask = BIT(0),
3083 		.hw.init = &(const struct clk_init_data) {
3084 			.name = "gcc_wcss_dbg_ifc_atb_bdg_clk",
3085 			.parent_hws = (const struct clk_hw*[]) {
3086 				&gcc_qdss_at_clk_src.clkr.hw,
3087 			},
3088 			.num_parents = 1,
3089 			.flags = CLK_SET_RATE_PARENT,
3090 			.ops = &clk_branch2_ops,
3091 		},
3092 	},
3093 };
3094 
3095 static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
3096 	.halt_reg = 0x2503c,
3097 	.halt_check = BRANCH_HALT,
3098 	.clkr = {
3099 		.enable_reg = 0x2503c,
3100 		.enable_mask = BIT(0),
3101 		.hw.init = &(const struct clk_init_data) {
3102 			.name = "gcc_wcss_dbg_ifc_atb_clk",
3103 			.parent_hws = (const struct clk_hw*[]) {
3104 				&gcc_qdss_at_clk_src.clkr.hw,
3105 			},
3106 			.num_parents = 1,
3107 			.flags = CLK_SET_RATE_PARENT,
3108 			.ops = &clk_branch2_ops,
3109 		},
3110 	},
3111 };
3112 
3113 static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {
3114 	.halt_reg = 0x25050,
3115 	.halt_check = BRANCH_HALT,
3116 	.clkr = {
3117 		.enable_reg = 0x25050,
3118 		.enable_mask = BIT(0),
3119 		.hw.init = &(const struct clk_init_data) {
3120 			.name = "gcc_wcss_dbg_ifc_nts_bdg_clk",
3121 			.parent_hws = (const struct clk_hw*[]) {
3122 				&gcc_qdss_tsctr_div2_clk_src.hw,
3123 			},
3124 			.num_parents = 1,
3125 			.flags = CLK_SET_RATE_PARENT,
3126 			.ops = &clk_branch2_ops,
3127 		},
3128 	},
3129 };
3130 
3131 static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
3132 	.halt_reg = 0x25040,
3133 	.halt_check = BRANCH_HALT,
3134 	.clkr = {
3135 		.enable_reg = 0x25040,
3136 		.enable_mask = BIT(0),
3137 		.hw.init = &(const struct clk_init_data) {
3138 			.name = "gcc_wcss_dbg_ifc_nts_clk",
3139 			.parent_hws = (const struct clk_hw*[]) {
3140 				&gcc_qdss_tsctr_div2_clk_src.hw,
3141 			},
3142 			.num_parents = 1,
3143 			.flags = CLK_SET_RATE_PARENT,
3144 			.ops = &clk_branch2_ops,
3145 		},
3146 	},
3147 };
3148 
3149 static struct clk_branch gcc_wcss_ecahb_clk = {
3150 	.halt_reg = 0x25058,
3151 	.halt_check = BRANCH_HALT,
3152 	.clkr = {
3153 		.enable_reg = 0x25058,
3154 		.enable_mask = BIT(0),
3155 		.hw.init = &(const struct clk_init_data) {
3156 			.name = "gcc_wcss_ecahb_clk",
3157 			.parent_hws = (const struct clk_hw*[]) {
3158 				&gcc_wcss_ahb_clk_src.clkr.hw,
3159 			},
3160 			.num_parents = 1,
3161 			.flags = CLK_SET_RATE_PARENT,
3162 			.ops = &clk_branch2_ops,
3163 		},
3164 	},
3165 };
3166 
3167 static struct clk_branch gcc_wcss_mst_async_bdg_clk = {
3168 	.halt_reg = 0x2e0b0,
3169 	.halt_check = BRANCH_HALT,
3170 	.clkr = {
3171 		.enable_reg = 0x2e0b0,
3172 		.enable_mask = BIT(0),
3173 		.hw.init = &(const struct clk_init_data) {
3174 			.name = "gcc_wcss_mst_async_bdg_clk",
3175 			.parent_hws = (const struct clk_hw*[]) {
3176 				&gcc_system_noc_bfdcd_clk_src.clkr.hw,
3177 			},
3178 			.num_parents = 1,
3179 			.flags = CLK_SET_RATE_PARENT,
3180 			.ops = &clk_branch2_ops,
3181 		},
3182 	},
3183 };
3184 
3185 static struct clk_branch gcc_wcss_slv_async_bdg_clk = {
3186 	.halt_reg = 0x2e0b4,
3187 	.halt_check = BRANCH_HALT,
3188 	.clkr = {
3189 		.enable_reg = 0x2e0b4,
3190 		.enable_mask = BIT(0),
3191 		.hw.init = &(const struct clk_init_data) {
3192 			.name = "gcc_wcss_slv_async_bdg_clk",
3193 			.parent_hws = (const struct clk_hw*[]) {
3194 				&gcc_system_noc_bfdcd_clk_src.clkr.hw,
3195 			},
3196 			.num_parents = 1,
3197 			.flags = CLK_SET_RATE_PARENT,
3198 			.ops = &clk_branch2_ops,
3199 		},
3200 	},
3201 };
3202 
3203 static struct clk_branch gcc_xo_clk = {
3204 	.halt_reg = 0x34018,
3205 	.halt_check = BRANCH_HALT,
3206 	.clkr = {
3207 		.enable_reg = 0x34018,
3208 		.enable_mask = BIT(0),
3209 		.hw.init = &(const struct clk_init_data) {
3210 			.name = "gcc_xo_clk",
3211 			.parent_hws = (const struct clk_hw*[]) {
3212 				&gcc_xo_clk_src.clkr.hw,
3213 			},
3214 			.num_parents = 1,
3215 			.flags = CLK_SET_RATE_PARENT,
3216 			.ops = &clk_branch2_ops,
3217 		},
3218 	},
3219 };
3220 
3221 static struct clk_branch gcc_xo_div4_clk = {
3222 	.halt_reg = 0x3401c,
3223 	.halt_check = BRANCH_HALT,
3224 	.clkr = {
3225 		.enable_reg = 0x3401c,
3226 		.enable_mask = BIT(0),
3227 		.hw.init = &(const struct clk_init_data) {
3228 			.name = "gcc_xo_div4_clk",
3229 			.parent_hws = (const struct clk_hw*[]) {
3230 				&gcc_xo_div4_clk_src.hw,
3231 			},
3232 			.num_parents = 1,
3233 			.flags = CLK_SET_RATE_PARENT,
3234 			.ops = &clk_branch2_ops,
3235 		},
3236 	},
3237 };
3238 
3239 static struct clk_branch gcc_im_sleep_clk = {
3240 	.halt_reg = 0x34020,
3241 	.halt_check = BRANCH_HALT,
3242 	.clkr = {
3243 		.enable_reg = 0x34020,
3244 		.enable_mask = BIT(0),
3245 		.hw.init = &(const struct clk_init_data) {
3246 			.name = "gcc_im_sleep_clk",
3247 			.parent_hws = (const struct clk_hw*[]) {
3248 				&gcc_sleep_clk_src.clkr.hw,
3249 			},
3250 			.num_parents = 1,
3251 			.flags = CLK_SET_RATE_PARENT,
3252 			.ops = &clk_branch2_ops,
3253 		},
3254 	},
3255 };
3256 
3257 static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
3258 	.halt_reg = 0x17080,
3259 	.halt_check = BRANCH_HALT,
3260 	.clkr = {
3261 		.enable_reg = 0x17080,
3262 		.enable_mask = BIT(0),
3263 		.hw.init = &(const struct clk_init_data) {
3264 			.name = "gcc_nssnoc_pcnoc_1_clk",
3265 			.parent_hws = (const struct clk_hw*[]) {
3266 				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
3267 			},
3268 			.num_parents = 1,
3269 			.flags = CLK_SET_RATE_PARENT,
3270 			.ops = &clk_branch2_ops,
3271 		},
3272 	},
3273 };
3274 
3275 static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = {
3276 	.reg = 0x2e010,
3277 	.shift = 0,
3278 	.width = 2,
3279 	.clkr.hw.init = &(const struct clk_init_data) {
3280 		.name = "gcc_snoc_qosgen_extref_div_clk_src",
3281 		.parent_hws = (const struct clk_hw*[]) {
3282 			&gcc_xo_clk_src.clkr.hw,
3283 		},
3284 		.num_parents = 1,
3285 		.flags = CLK_SET_RATE_PARENT,
3286 		.ops = &clk_regmap_div_ro_ops,
3287 	},
3288 };
3289 
3290 static struct clk_regmap *gcc_ipq5332_clocks[] = {
3291 	[GPLL0_MAIN] = &gpll0_main.clkr,
3292 	[GPLL0] = &gpll0.clkr,
3293 	[GPLL2_MAIN] = &gpll2_main.clkr,
3294 	[GPLL2] = &gpll2.clkr,
3295 	[GPLL4_MAIN] = &gpll4_main.clkr,
3296 	[GPLL4] = &gpll4.clkr,
3297 	[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
3298 	[GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,
3299 	[GCC_AHB_CLK] = &gcc_ahb_clk.clkr,
3300 	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3301 	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3302 	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3303 	[GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup1_spi_apps_clk_src.clkr,
3304 	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3305 	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3306 	[GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup2_spi_apps_clk_src.clkr,
3307 	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3308 	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3309 	[GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup3_spi_apps_clk_src.clkr,
3310 	[GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3311 	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3312 	[GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr,
3313 	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3314 	[GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr,
3315 	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3316 	[GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr,
3317 	[GCC_CE_AHB_CLK] = &gcc_ce_ahb_clk.clkr,
3318 	[GCC_CE_AXI_CLK] = &gcc_ce_axi_clk.clkr,
3319 	[GCC_CE_PCNOC_AHB_CLK] = &gcc_ce_pcnoc_ahb_clk.clkr,
3320 	[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
3321 	[GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
3322 	[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
3323 	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3324 	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3325 	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3326 	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3327 	[GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
3328 	[GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
3329 	[GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr,
3330 	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
3331 	[GCC_MDIO_SLAVE_AHB_CLK] = &gcc_mdio_slave_ahb_clk.clkr,
3332 	[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
3333 	[GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr,
3334 	[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
3335 	[GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
3336 	[GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
3337 	[GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
3338 	[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
3339 	[GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
3340 	[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
3341 	[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
3342 	[GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
3343 	[GCC_PCIE3X1_0_AHB_CLK] = &gcc_pcie3x1_0_ahb_clk.clkr,
3344 	[GCC_PCIE3X1_0_AUX_CLK] = &gcc_pcie3x1_0_aux_clk.clkr,
3345 	[GCC_PCIE3X1_0_AXI_CLK_SRC] = &gcc_pcie3x1_0_axi_clk_src.clkr,
3346 	[GCC_PCIE3X1_0_AXI_M_CLK] = &gcc_pcie3x1_0_axi_m_clk.clkr,
3347 	[GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK] = &gcc_pcie3x1_0_axi_s_bridge_clk.clkr,
3348 	[GCC_PCIE3X1_0_AXI_S_CLK] = &gcc_pcie3x1_0_axi_s_clk.clkr,
3349 	[GCC_PCIE3X1_0_PIPE_CLK] = &gcc_pcie3x1_0_pipe_clk.clkr,
3350 	[GCC_PCIE3X1_0_RCHG_CLK] = &gcc_pcie3x1_0_rchg_clk.clkr,
3351 	[GCC_PCIE3X1_0_RCHG_CLK_SRC] = &gcc_pcie3x1_0_rchg_clk_src.clkr,
3352 	[GCC_PCIE3X1_1_AHB_CLK] = &gcc_pcie3x1_1_ahb_clk.clkr,
3353 	[GCC_PCIE3X1_1_AUX_CLK] = &gcc_pcie3x1_1_aux_clk.clkr,
3354 	[GCC_PCIE3X1_1_AXI_CLK_SRC] = &gcc_pcie3x1_1_axi_clk_src.clkr,
3355 	[GCC_PCIE3X1_1_AXI_M_CLK] = &gcc_pcie3x1_1_axi_m_clk.clkr,
3356 	[GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK] = &gcc_pcie3x1_1_axi_s_bridge_clk.clkr,
3357 	[GCC_PCIE3X1_1_AXI_S_CLK] = &gcc_pcie3x1_1_axi_s_clk.clkr,
3358 	[GCC_PCIE3X1_1_PIPE_CLK] = &gcc_pcie3x1_1_pipe_clk.clkr,
3359 	[GCC_PCIE3X1_1_RCHG_CLK] = &gcc_pcie3x1_1_rchg_clk.clkr,
3360 	[GCC_PCIE3X1_1_RCHG_CLK_SRC] = &gcc_pcie3x1_1_rchg_clk_src.clkr,
3361 	[GCC_PCIE3X1_PHY_AHB_CLK] = &gcc_pcie3x1_phy_ahb_clk.clkr,
3362 	[GCC_PCIE3X2_AHB_CLK] = &gcc_pcie3x2_ahb_clk.clkr,
3363 	[GCC_PCIE3X2_AUX_CLK] = &gcc_pcie3x2_aux_clk.clkr,
3364 	[GCC_PCIE3X2_AXI_M_CLK] = &gcc_pcie3x2_axi_m_clk.clkr,
3365 	[GCC_PCIE3X2_AXI_M_CLK_SRC] = &gcc_pcie3x2_axi_m_clk_src.clkr,
3366 	[GCC_PCIE3X2_AXI_S_BRIDGE_CLK] = &gcc_pcie3x2_axi_s_bridge_clk.clkr,
3367 	[GCC_PCIE3X2_AXI_S_CLK] = &gcc_pcie3x2_axi_s_clk.clkr,
3368 	[GCC_PCIE3X2_AXI_S_CLK_SRC] = &gcc_pcie3x2_axi_s_clk_src.clkr,
3369 	[GCC_PCIE3X2_PHY_AHB_CLK] = &gcc_pcie3x2_phy_ahb_clk.clkr,
3370 	[GCC_PCIE3X2_PIPE_CLK] = &gcc_pcie3x2_pipe_clk.clkr,
3371 	[GCC_PCIE3X2_RCHG_CLK] = &gcc_pcie3x2_rchg_clk.clkr,
3372 	[GCC_PCIE3X2_RCHG_CLK_SRC] = &gcc_pcie3x2_rchg_clk_src.clkr,
3373 	[GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,
3374 	[GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
3375 	[GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr,
3376 	[GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr,
3377 	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3378 	[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
3379 	[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
3380 	[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
3381 	[GCC_Q6_AXIM_CLK_SRC] = &gcc_q6_axim_clk_src.clkr,
3382 	[GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr,
3383 	[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
3384 	[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
3385 	[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
3386 	[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
3387 	[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
3388 	[GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr,
3389 	[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
3390 	[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
3391 	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
3392 	[GCC_QDSS_DAP_DIV_CLK_SRC] = &gcc_qdss_dap_div_clk_src.clkr,
3393 	[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
3394 	[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
3395 	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
3396 	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
3397 	[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
3398 	[GCC_QPIC_IO_MACRO_CLK_SRC] = &gcc_qpic_io_macro_clk_src.clkr,
3399 	[GCC_QPIC_SLEEP_CLK] = &gcc_qpic_sleep_clk.clkr,
3400 	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3401 	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3402 	[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3403 	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3404 	[GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr,
3405 	[GCC_SNOC_NSSNOC_1_CLK] = &gcc_snoc_nssnoc_1_clk.clkr,
3406 	[GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr,
3407 	[GCC_SNOC_PCIE3_1LANE_1_M_CLK] = &gcc_snoc_pcie3_1lane_1_m_clk.clkr,
3408 	[GCC_SNOC_PCIE3_1LANE_1_S_CLK] = &gcc_snoc_pcie3_1lane_1_s_clk.clkr,
3409 	[GCC_SNOC_PCIE3_1LANE_M_CLK] = &gcc_snoc_pcie3_1lane_m_clk.clkr,
3410 	[GCC_SNOC_PCIE3_1LANE_S_CLK] = &gcc_snoc_pcie3_1lane_s_clk.clkr,
3411 	[GCC_SNOC_PCIE3_2LANE_M_CLK] = &gcc_snoc_pcie3_2lane_m_clk.clkr,
3412 	[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
3413 	[GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
3414 	[GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
3415 	[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
3416 	[GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr,
3417 	[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
3418 	[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
3419 	[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
3420 	[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
3421 	[GCC_UNIPHY_SYS_CLK_SRC] = &gcc_uniphy_sys_clk_src.clkr,
3422 	[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
3423 	[GCC_USB0_AUX_CLK_SRC] = &gcc_usb0_aux_clk_src.clkr,
3424 	[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
3425 	[GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr,
3426 	[GCC_USB0_LFPS_CLK_SRC] = &gcc_usb0_lfps_clk_src.clkr,
3427 	[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
3428 	[GCC_USB0_MASTER_CLK_SRC] = &gcc_usb0_master_clk_src.clkr,
3429 	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
3430 	[GCC_USB0_MOCK_UTMI_CLK_SRC] = &gcc_usb0_mock_utmi_clk_src.clkr,
3431 	[GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb0_mock_utmi_div_clk_src.clkr,
3432 	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
3433 	[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
3434 	[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
3435 	[GCC_WCSS_AHB_CLK_SRC] = &gcc_wcss_ahb_clk_src.clkr,
3436 	[GCC_WCSS_AXIM_CLK] = &gcc_wcss_axim_clk.clkr,
3437 	[GCC_WCSS_AXIS_CLK] = &gcc_wcss_axis_clk.clkr,
3438 	[GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr,
3439 	[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
3440 	[GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr,
3441 	[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
3442 	[GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr,
3443 	[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
3444 	[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
3445 	[GCC_WCSS_MST_ASYNC_BDG_CLK] = &gcc_wcss_mst_async_bdg_clk.clkr,
3446 	[GCC_WCSS_SLV_ASYNC_BDG_CLK] = &gcc_wcss_slv_async_bdg_clk.clkr,
3447 	[GCC_XO_CLK] = &gcc_xo_clk.clkr,
3448 	[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
3449 	[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
3450 	[GCC_IM_SLEEP_CLK] = &gcc_im_sleep_clk.clkr,
3451 	[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
3452 	[GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC] = &gcc_snoc_qosgen_extref_div_clk_src.clkr,
3453 	[GCC_PCIE3X2_PIPE_CLK_SRC] = &gcc_pcie3x2_pipe_clk_src.clkr,
3454 	[GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr,
3455 	[GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr,
3456 	[GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr,
3457 };
3458 
3459 static const struct qcom_reset_map gcc_ipq5332_resets[] = {
3460 	[GCC_ADSS_BCR] = { 0x1c000 },
3461 	[GCC_ADSS_PWM_CLK_ARES] = { 0x1c00c, 2 },
3462 	[GCC_AHB_CLK_ARES] = { 0x34024, 2 },
3463 	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000 },
3464 	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES] = { 0x3800c, 2 },
3465 	[GCC_APSS_AHB_CLK_ARES] = { 0x24018, 2 },
3466 	[GCC_APSS_AXI_CLK_ARES] = { 0x2401c, 2 },
3467 	[GCC_BLSP1_AHB_CLK_ARES] = { 0x1008, 2 },
3468 	[GCC_BLSP1_BCR] = { 0x1000 },
3469 	[GCC_BLSP1_QUP1_BCR] = { 0x2000 },
3470 	[GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES] = { 0x2024, 2 },
3471 	[GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES] = { 0x2020, 2 },
3472 	[GCC_BLSP1_QUP2_BCR] = { 0x3000 },
3473 	[GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES] = { 0x3024, 2 },
3474 	[GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES] = { 0x3020, 2 },
3475 	[GCC_BLSP1_QUP3_BCR] = { 0x4000 },
3476 	[GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES] = { 0x4024, 2 },
3477 	[GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES] = { 0x4020, 2 },
3478 	[GCC_BLSP1_SLEEP_CLK_ARES] = { 0x1010, 2 },
3479 	[GCC_BLSP1_UART1_APPS_CLK_ARES] = { 0x2040, 2 },
3480 	[GCC_BLSP1_UART1_BCR] = { 0x2028 },
3481 	[GCC_BLSP1_UART2_APPS_CLK_ARES] = { 0x3040, 2 },
3482 	[GCC_BLSP1_UART2_BCR] = { 0x3028 },
3483 	[GCC_BLSP1_UART3_APPS_CLK_ARES] = { 0x4054, 2 },
3484 	[GCC_BLSP1_UART3_BCR] = { 0x4028 },
3485 	[GCC_CE_BCR] = { 0x18008 },
3486 	[GCC_CMN_BLK_BCR] = { 0x3a000 },
3487 	[GCC_CMN_LDO0_BCR] = { 0x1d000 },
3488 	[GCC_CMN_LDO1_BCR] = { 0x1d008 },
3489 	[GCC_DCC_BCR] = { 0x35000 },
3490 	[GCC_GP1_CLK_ARES] = { 0x8018, 2 },
3491 	[GCC_GP2_CLK_ARES] = { 0x9018, 2 },
3492 	[GCC_LPASS_BCR] = { 0x27000 },
3493 	[GCC_LPASS_CORE_AXIM_CLK_ARES] = { 0x27018, 2 },
3494 	[GCC_LPASS_SWAY_CLK_ARES] = { 0x27014, 2 },
3495 	[GCC_MDIOM_BCR] = { 0x12000 },
3496 	[GCC_MDIOS_BCR] = { 0x12008 },
3497 	[GCC_NSS_BCR] = { 0x17000 },
3498 	[GCC_NSS_TS_CLK_ARES] = { 0x17018, 2 },
3499 	[GCC_NSSCC_CLK_ARES] = { 0x17034, 2 },
3500 	[GCC_NSSCFG_CLK_ARES] = { 0x1702c, 2 },
3501 	[GCC_NSSNOC_ATB_CLK_ARES] = { 0x17014, 2 },
3502 	[GCC_NSSNOC_NSSCC_CLK_ARES] = { 0x17030, 2 },
3503 	[GCC_NSSNOC_QOSGEN_REF_CLK_ARES] = { 0x1701c, 2 },
3504 	[GCC_NSSNOC_SNOC_1_CLK_ARES] = { 0x1707c, 2 },
3505 	[GCC_NSSNOC_SNOC_CLK_ARES] = { 0x17028, 2 },
3506 	[GCC_NSSNOC_TIMEOUT_REF_CLK_ARES] = { 0x17020, 2 },
3507 	[GCC_NSSNOC_XO_DCD_CLK_ARES] = { 0x17074, 2 },
3508 	[GCC_PCIE3X1_0_AHB_CLK_ARES] = { 0x29030, 2 },
3509 	[GCC_PCIE3X1_0_AUX_CLK_ARES] = { 0x29070, 2 },
3510 	[GCC_PCIE3X1_0_AXI_M_CLK_ARES] = { 0x29038, 2 },
3511 	[GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES] = { 0x29048, 2 },
3512 	[GCC_PCIE3X1_0_AXI_S_CLK_ARES] = { 0x29040, 2 },
3513 	[GCC_PCIE3X1_0_BCR] = { 0x29000 },
3514 	[GCC_PCIE3X1_0_LINK_DOWN_BCR] = { 0x29054 },
3515 	[GCC_PCIE3X1_0_PHY_BCR] = { 0x29060 },
3516 	[GCC_PCIE3X1_0_PHY_PHY_BCR] = { 0x2905c },
3517 	[GCC_PCIE3X1_1_AHB_CLK_ARES] = { 0x2a00c, 2 },
3518 	[GCC_PCIE3X1_1_AUX_CLK_ARES] = { 0x2a070, 2 },
3519 	[GCC_PCIE3X1_1_AXI_M_CLK_ARES] = { 0x2a014, 2 },
3520 	[GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES] = { 0x2a024, 2 },
3521 	[GCC_PCIE3X1_1_AXI_S_CLK_ARES] = { 0x2a01c, 2 },
3522 	[GCC_PCIE3X1_1_BCR] = { 0x2a000 },
3523 	[GCC_PCIE3X1_1_LINK_DOWN_BCR] = { 0x2a028 },
3524 	[GCC_PCIE3X1_1_PHY_BCR] = { 0x2a030 },
3525 	[GCC_PCIE3X1_1_PHY_PHY_BCR] = { 0x2a02c },
3526 	[GCC_PCIE3X1_PHY_AHB_CLK_ARES] = { 0x29078, 2 },
3527 	[GCC_PCIE3X2_AHB_CLK_ARES] = { 0x28030, 2 },
3528 	[GCC_PCIE3X2_AUX_CLK_ARES] = { 0x28070, 2 },
3529 	[GCC_PCIE3X2_AXI_M_CLK_ARES] = { 0x28038, 2 },
3530 	[GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES] = { 0x28048, 2 },
3531 	[GCC_PCIE3X2_AXI_S_CLK_ARES] = { 0x28040, 2 },
3532 	[GCC_PCIE3X2_BCR] = { 0x28000 },
3533 	[GCC_PCIE3X2_LINK_DOWN_BCR] = { 0x28054 },
3534 	[GCC_PCIE3X2_PHY_AHB_CLK_ARES] = { 0x28080, 2 },
3535 	[GCC_PCIE3X2_PHY_BCR] = { 0x28060 },
3536 	[GCC_PCIE3X2PHY_PHY_BCR] = { 0x2805c },
3537 	[GCC_PCNOC_BCR] = { 0x31000 },
3538 	[GCC_PCNOC_LPASS_CLK_ARES] = { 0x31020, 2 },
3539 	[GCC_PRNG_AHB_CLK_ARES] = { 0x13024, 2 },
3540 	[GCC_PRNG_BCR] = { 0x13020 },
3541 	[GCC_Q6_AHB_CLK_ARES] = { 0x25014, 2 },
3542 	[GCC_Q6_AHB_S_CLK_ARES] = { 0x25018, 2 },
3543 	[GCC_Q6_AXIM_CLK_ARES] = { 0x2500c, 2 },
3544 	[GCC_Q6_AXIS_CLK_ARES] = { 0x25010, 2 },
3545 	[GCC_Q6_TSCTR_1TO2_CLK_ARES] = { 0x25020, 2 },
3546 	[GCC_Q6SS_ATBM_CLK_ARES] = { 0x2501c, 2 },
3547 	[GCC_Q6SS_PCLKDBG_CLK_ARES] = { 0x25024, 2 },
3548 	[GCC_Q6SS_TRIG_CLK_ARES] = { 0x250a0, 2 },
3549 	[GCC_QDSS_APB2JTAG_CLK_ARES] = { 0x2d060, 2 },
3550 	[GCC_QDSS_AT_CLK_ARES] = { 0x2d038, 2 },
3551 	[GCC_QDSS_BCR] = { 0x2d000 },
3552 	[GCC_QDSS_CFG_AHB_CLK_ARES] = { 0x2d06c, 2 },
3553 	[GCC_QDSS_DAP_AHB_CLK_ARES] = { 0x2d068, 2 },
3554 	[GCC_QDSS_DAP_CLK_ARES] = { 0x2d05c, 2 },
3555 	[GCC_QDSS_ETR_USB_CLK_ARES] = { 0x2d064, 2 },
3556 	[GCC_QDSS_EUD_AT_CLK_ARES] = { 0x2d070, 2 },
3557 	[GCC_QDSS_STM_CLK_ARES] = { 0x2d040, 2 },
3558 	[GCC_QDSS_TRACECLKIN_CLK_ARES] = { 0x2d044, 2 },
3559 	[GCC_QDSS_TS_CLK_ARES] = { 0x2d078, 2 },
3560 	[GCC_QDSS_TSCTR_DIV16_CLK_ARES] = { 0x2d058, 2 },
3561 	[GCC_QDSS_TSCTR_DIV2_CLK_ARES] = { 0x2d048, 2 },
3562 	[GCC_QDSS_TSCTR_DIV3_CLK_ARES] = { 0x2d04c, 2 },
3563 	[GCC_QDSS_TSCTR_DIV4_CLK_ARES] = { 0x2d050, 2 },
3564 	[GCC_QDSS_TSCTR_DIV8_CLK_ARES] = { 0x2d054, 2 },
3565 	[GCC_QPIC_AHB_CLK_ARES] = { 0x32010, 2 },
3566 	[GCC_QPIC_CLK_ARES] = { 0x32014, 2 },
3567 	[GCC_QPIC_BCR] = { 0x32000 },
3568 	[GCC_QPIC_IO_MACRO_CLK_ARES] = { 0x3200c, 2 },
3569 	[GCC_QPIC_SLEEP_CLK_ARES] = { 0x3201c, 2 },
3570 	[GCC_QUSB2_0_PHY_BCR] = { 0x2c068 },
3571 	[GCC_SDCC1_AHB_CLK_ARES] = { 0x33034, 2 },
3572 	[GCC_SDCC1_APPS_CLK_ARES] = { 0x3302c, 2 },
3573 	[GCC_SDCC_BCR] = { 0x33000 },
3574 	[GCC_SNOC_BCR] = { 0x2e000 },
3575 	[GCC_SNOC_LPASS_CFG_CLK_ARES] = { 0x2e028, 2 },
3576 	[GCC_SNOC_NSSNOC_1_CLK_ARES] = { 0x17090, 2 },
3577 	[GCC_SNOC_NSSNOC_CLK_ARES] = { 0x17084, 2 },
3578 	[GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES] = { 0x2e034, 2 },
3579 	[GCC_SYS_NOC_WCSS_AHB_CLK_ARES] = { 0x2e030, 2 },
3580 	[GCC_UNIPHY0_AHB_CLK_ARES] = { 0x16010, 2 },
3581 	[GCC_UNIPHY0_BCR] = { 0x16000 },
3582 	[GCC_UNIPHY0_SYS_CLK_ARES] = { 0x1600c, 2 },
3583 	[GCC_UNIPHY1_AHB_CLK_ARES] = { 0x1601c, 2 },
3584 	[GCC_UNIPHY1_BCR] = { 0x16014 },
3585 	[GCC_UNIPHY1_SYS_CLK_ARES] = { 0x16018, 2 },
3586 	[GCC_USB0_AUX_CLK_ARES] = { 0x2c050, 2 },
3587 	[GCC_USB0_EUD_AT_CLK_ARES] = { 0x30004, 2 },
3588 	[GCC_USB0_LFPS_CLK_ARES] = { 0x2c090, 2 },
3589 	[GCC_USB0_MASTER_CLK_ARES] = { 0x2c048, 2 },
3590 	[GCC_USB0_MOCK_UTMI_CLK_ARES] = { 0x2c054, 2 },
3591 	[GCC_USB0_PHY_BCR] = { 0x2c06c },
3592 	[GCC_USB0_PHY_CFG_AHB_CLK_ARES] = { 0x2c05c, 2 },
3593 	[GCC_USB0_SLEEP_CLK_ARES] = { 0x2c058, 2 },
3594 	[GCC_USB3PHY_0_PHY_BCR] = { 0x2c070 },
3595 	[GCC_USB_BCR] = { 0x2c000 },
3596 	[GCC_WCSS_AXIM_CLK_ARES] = { 0x2505c, 2 },
3597 	[GCC_WCSS_AXIS_CLK_ARES] = { 0x25060, 2 },
3598 	[GCC_WCSS_BCR] = { 0x18004 },
3599 	[GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES] = { 0x25048, 2 },
3600 	[GCC_WCSS_DBG_IFC_APB_CLK_ARES] = { 0x25038, 2 },
3601 	[GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES] = { 0x2504c, 2 },
3602 	[GCC_WCSS_DBG_IFC_ATB_CLK_ARES] = { 0x2503c, 2 },
3603 	[GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES] = { 0x25050, 2 },
3604 	[GCC_WCSS_DBG_IFC_NTS_CLK_ARES] = { 0x25040, 2 },
3605 	[GCC_WCSS_ECAHB_CLK_ARES] = { 0x25058, 2 },
3606 	[GCC_WCSS_MST_ASYNC_BDG_CLK_ARES] = { 0x2e0b0, 2 },
3607 	[GCC_WCSS_Q6_BCR] = { 0x18000 },
3608 	[GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES] = { 0x2e0b4, 2 },
3609 	[GCC_XO_CLK_ARES] = { 0x34018, 2 },
3610 	[GCC_XO_DIV4_CLK_ARES] = { 0x3401c, 2 },
3611 	[GCC_Q6SS_DBG_ARES] = { 0x25094 },
3612 	[GCC_WCSS_DBG_BDG_ARES] = { 0x25098, 0 },
3613 	[GCC_WCSS_DBG_ARES] = { 0x25098, 1 },
3614 	[GCC_WCSS_AXI_S_ARES] = { 0x25098, 2 },
3615 	[GCC_WCSS_AXI_M_ARES] = { 0x25098, 3 },
3616 	[GCC_WCSSAON_ARES] = { 0x2509C },
3617 	[GCC_PCIE3X2_PIPE_ARES] = { 0x28058, 0 },
3618 	[GCC_PCIE3X2_CORE_STICKY_ARES] = { 0x28058, 1 },
3619 	[GCC_PCIE3X2_AXI_S_STICKY_ARES] = { 0x28058, 2 },
3620 	[GCC_PCIE3X2_AXI_M_STICKY_ARES] = { 0x28058, 3 },
3621 	[GCC_PCIE3X1_0_PIPE_ARES] = { 0x29058, 0 },
3622 	[GCC_PCIE3X1_0_CORE_STICKY_ARES] = { 0x29058, 1 },
3623 	[GCC_PCIE3X1_0_AXI_S_STICKY_ARES] = { 0x29058, 2 },
3624 	[GCC_PCIE3X1_0_AXI_M_STICKY_ARES] = { 0x29058, 3 },
3625 	[GCC_PCIE3X1_1_PIPE_ARES] = { 0x2a058, 0 },
3626 	[GCC_PCIE3X1_1_CORE_STICKY_ARES] = { 0x2a058, 1 },
3627 	[GCC_PCIE3X1_1_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
3628 	[GCC_PCIE3X1_1_AXI_M_STICKY_ARES] = { 0x2a058, 3 },
3629 	[GCC_IM_SLEEP_CLK_ARES] = { 0x34020, 2 },
3630 	[GCC_NSSNOC_PCNOC_1_CLK_ARES] = { 0x17080, 2 },
3631 	[GCC_UNIPHY0_XPCS_ARES] = { 0x16050 },
3632 	[GCC_UNIPHY1_XPCS_ARES] = { 0x16060 },
3633 };
3634 
3635 static const struct regmap_config gcc_ipq5332_regmap_config = {
3636 	.reg_bits = 32,
3637 	.reg_stride = 4,
3638 	.val_bits = 32,
3639 	.max_register = 0x3f024,
3640 	.fast_io = true,
3641 };
3642 
3643 static struct clk_hw *gcc_ipq5332_hws[] = {
3644 	&gpll0_div2.hw,
3645 	&gcc_xo_div4_clk_src.hw,
3646 	&gcc_system_noc_bfdcd_div2_clk_src.hw,
3647 	&gcc_qdss_tsctr_div2_clk_src.hw,
3648 	&gcc_qdss_tsctr_div3_clk_src.hw,
3649 	&gcc_qdss_tsctr_div4_clk_src.hw,
3650 	&gcc_qdss_tsctr_div8_clk_src.hw,
3651 	&gcc_qdss_tsctr_div16_clk_src.hw,
3652 	&gcc_eud_at_div_clk_src.hw,
3653 };
3654 
3655 static const struct qcom_cc_desc gcc_ipq5332_desc = {
3656 	.config = &gcc_ipq5332_regmap_config,
3657 	.clks = gcc_ipq5332_clocks,
3658 	.num_clks = ARRAY_SIZE(gcc_ipq5332_clocks),
3659 	.resets = gcc_ipq5332_resets,
3660 	.num_resets = ARRAY_SIZE(gcc_ipq5332_resets),
3661 	.clk_hws = gcc_ipq5332_hws,
3662 	.num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws),
3663 };
3664 
gcc_ipq5332_probe(struct platform_device * pdev)3665 static int gcc_ipq5332_probe(struct platform_device *pdev)
3666 {
3667 	return qcom_cc_probe(pdev, &gcc_ipq5332_desc);
3668 }
3669 
3670 static const struct of_device_id gcc_ipq5332_match_table[] = {
3671 	{ .compatible = "qcom,ipq5332-gcc" },
3672 	{ }
3673 };
3674 MODULE_DEVICE_TABLE(of, gcc_ipq5332_match_table);
3675 
3676 static struct platform_driver gcc_ipq5332_driver = {
3677 	.probe = gcc_ipq5332_probe,
3678 	.driver = {
3679 		.name = "gcc-ipq5332",
3680 		.of_match_table = gcc_ipq5332_match_table,
3681 	},
3682 };
3683 
gcc_ipq5332_init(void)3684 static int __init gcc_ipq5332_init(void)
3685 {
3686 	return platform_driver_register(&gcc_ipq5332_driver);
3687 }
3688 core_initcall(gcc_ipq5332_init);
3689 
gcc_ipq5332_exit(void)3690 static void __exit gcc_ipq5332_exit(void)
3691 {
3692 	platform_driver_unregister(&gcc_ipq5332_driver);
3693 }
3694 module_exit(gcc_ipq5332_exit);
3695 
3696 MODULE_DESCRIPTION("QTI GCC IPQ5332 Driver");
3697 MODULE_LICENSE("GPL");
3698