1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/platform_device.h>
11
12 #include "clk-gate.h"
13 #include "clk-mtk.h"
14 #include "clk-mux.h"
15 #include "clk-pll.h"
16
17 #include <dt-bindings/clock/mt7986-clk.h>
18 #include <linux/clk.h>
19
20 #define MT7986_PLL_FMAX (2500UL * MHZ)
21 #define CON0_MT7986_RST_BAR BIT(27)
22
23 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
24 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
25 _div_table, _parent_name) \
26 { \
27 .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
28 .en_mask = _en_mask, .flags = _flags, \
29 .rst_bar_mask = CON0_MT7986_RST_BAR, .fmax = MT7986_PLL_FMAX, \
30 .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
31 .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \
32 .pcw_shift = _pcw_shift, .div_table = _div_table, \
33 .parent_name = _parent_name, \
34 }
35
36 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
37 _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \
38 PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
39 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
40 "clkxtal")
41
42 static const struct mtk_pll_data plls[] = {
43 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,
44 0x0200, 4, 0, 0x0204, 0),
45 PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
46 0x0210, 4, 0, 0x0214, 0),
47 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x0, 0, 32,
48 0x0220, 4, 0, 0x0224, 0),
49 PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x0, 0, 32,
50 0x0230, 4, 0, 0x0234, 0),
51 PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x0, 0,
52 32, 0x0240, 4, 0, 0x0244, 0),
53 PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x0, 0, 32,
54 0x0250, 4, 0, 0x0254, 0),
55 PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x0, 0, 32, 0x0260,
56 4, 0, 0x0264, 0),
57 PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x0, 0, 32,
58 0x0278, 4, 0, 0x027c, 0),
59 };
60
61 static const struct of_device_id of_match_clk_mt7986_apmixed[] = {
62 { .compatible = "mediatek,mt7986-apmixedsys", },
63 { }
64 };
65 MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_apmixed);
66
clk_mt7986_apmixed_probe(struct platform_device * pdev)67 static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
68 {
69 struct clk_hw_onecell_data *clk_data;
70 struct device_node *node = pdev->dev.of_node;
71 int r;
72
73 clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
74 if (!clk_data)
75 return -ENOMEM;
76
77 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
78
79 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
80 if (r) {
81 pr_err("%s(): could not register clock provider: %d\n",
82 __func__, r);
83 goto free_apmixed_data;
84 }
85 return r;
86
87 free_apmixed_data:
88 mtk_free_clk_data(clk_data);
89 return r;
90 }
91
92 static struct platform_driver clk_mt7986_apmixed_drv = {
93 .probe = clk_mt7986_apmixed_probe,
94 .driver = {
95 .name = "clk-mt7986-apmixed",
96 .of_match_table = of_match_clk_mt7986_apmixed,
97 },
98 };
99 builtin_platform_driver(clk_mt7986_apmixed_drv);
100 MODULE_LICENSE("GPL");
101
