1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra124-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra124-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9#include <dt-bindings/soc/tegra-pmc.h> 10 11#include "tegra132-peripherals-opp.dtsi" 12 13/ { 14 compatible = "nvidia,tegra132", "nvidia,tegra124"; 15 interrupt-parent = <&lic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 pcie@1003000 { 20 compatible = "nvidia,tegra124-pcie"; 21 device_type = "pci"; 22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 25 reg-names = "pads", "afi", "cs"; 26 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 27 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 28 interrupt-names = "intr", "msi"; 29 30 #interrupt-cells = <1>; 31 interrupt-map-mask = <0 0 0 0>; 32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 33 34 bus-range = <0x00 0xff>; 35 #address-cells = <3>; 36 #size-cells = <2>; 37 38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 42 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 43 44 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 45 <&tegra_car TEGRA124_CLK_AFI>, 46 <&tegra_car TEGRA124_CLK_PLL_E>, 47 <&tegra_car TEGRA124_CLK_CML0>; 48 clock-names = "pex", "afi", "pll_e", "cml"; 49 resets = <&tegra_car 70>, 50 <&tegra_car 72>, 51 <&tegra_car 74>; 52 reset-names = "pex", "afi", "pcie_x"; 53 status = "disabled"; 54 55 pci@1,0 { 56 device_type = "pci"; 57 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 58 reg = <0x000800 0 0 0 0>; 59 bus-range = <0x00 0xff>; 60 status = "disabled"; 61 62 #address-cells = <3>; 63 #size-cells = <2>; 64 ranges; 65 66 nvidia,num-lanes = <2>; 67 }; 68 69 pci@2,0 { 70 device_type = "pci"; 71 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 72 reg = <0x001000 0 0 0 0>; 73 bus-range = <0x00 0xff>; 74 status = "disabled"; 75 76 #address-cells = <3>; 77 #size-cells = <2>; 78 ranges; 79 80 nvidia,num-lanes = <1>; 81 }; 82 }; 83 84 host1x@50000000 { 85 compatible = "nvidia,tegra132-host1x", 86 "nvidia,tegra124-host1x"; 87 reg = <0x0 0x50000000 0x0 0x00034000>; 88 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 89 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 90 interrupt-names = "syncpt", "host1x"; 91 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 92 clock-names = "host1x"; 93 resets = <&tegra_car 28>; 94 reset-names = "host1x"; 95 96 #address-cells = <2>; 97 #size-cells = <2>; 98 99 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 100 101 dc@54200000 { 102 compatible = "nvidia,tegra124-dc"; 103 reg = <0x0 0x54200000 0x0 0x00040000>; 104 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 105 clocks = <&tegra_car TEGRA124_CLK_DISP1>; 106 clock-names = "dc"; 107 resets = <&tegra_car 27>; 108 reset-names = "dc"; 109 110 iommus = <&mc TEGRA_SWGROUP_DC>; 111 112 nvidia,head = <0>; 113 }; 114 115 dc@54240000 { 116 compatible = "nvidia,tegra124-dc"; 117 reg = <0x0 0x54240000 0x0 0x00040000>; 118 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&tegra_car TEGRA124_CLK_DISP2>; 120 clock-names = "dc"; 121 resets = <&tegra_car 26>; 122 reset-names = "dc"; 123 124 iommus = <&mc TEGRA_SWGROUP_DCB>; 125 126 nvidia,head = <1>; 127 }; 128 129 hdmi@54280000 { 130 compatible = "nvidia,tegra124-hdmi"; 131 reg = <0x0 0x54280000 0x0 0x00040000>; 132 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 133 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 134 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 135 clock-names = "hdmi", "parent"; 136 resets = <&tegra_car 51>; 137 reset-names = "hdmi"; 138 status = "disabled"; 139 }; 140 141 sor@54540000 { 142 compatible = "nvidia,tegra124-sor"; 143 reg = <0x0 0x54540000 0x0 0x00040000>; 144 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 146 <&tegra_car TEGRA124_CLK_SOR0_OUT>, 147 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 148 <&tegra_car TEGRA124_CLK_PLL_DP>, 149 <&tegra_car TEGRA124_CLK_CLK_M>; 150 clock-names = "sor", "out", "parent", "dp", "safe"; 151 resets = <&tegra_car 182>; 152 reset-names = "sor"; 153 status = "disabled"; 154 }; 155 156 dpaux: dpaux@545c0000 { 157 compatible = "nvidia,tegra124-dpaux"; 158 reg = <0x0 0x545c0000 0x0 0x00040000>; 159 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 161 <&tegra_car TEGRA124_CLK_PLL_DP>; 162 clock-names = "dpaux", "parent"; 163 resets = <&tegra_car 181>; 164 reset-names = "dpaux"; 165 status = "disabled"; 166 167 i2c-bus { 168 #address-cells = <1>; 169 #size-cells = <0>; 170 }; 171 }; 172 }; 173 174 gic: interrupt-controller@50041000 { 175 compatible = "arm,cortex-a15-gic"; 176 #interrupt-cells = <3>; 177 interrupt-controller; 178 reg = <0x0 0x50041000 0x0 0x1000>, 179 <0x0 0x50042000 0x0 0x2000>, 180 <0x0 0x50044000 0x0 0x2000>, 181 <0x0 0x50046000 0x0 0x2000>; 182 interrupts = <GIC_PPI 9 183 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 184 interrupt-parent = <&gic>; 185 }; 186 187 gpu@57000000 { 188 compatible = "nvidia,gk20a"; 189 reg = <0x0 0x57000000 0x0 0x01000000>, 190 <0x0 0x58000000 0x0 0x01000000>; 191 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 193 interrupt-names = "stall", "nonstall"; 194 clocks = <&tegra_car TEGRA124_CLK_GPU>, 195 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 196 clock-names = "gpu", "pwr"; 197 resets = <&tegra_car 184>; 198 reset-names = "gpu"; 199 status = "disabled"; 200 }; 201 202 lic: interrupt-controller@60004000 { 203 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 204 reg = <0x0 0x60004000 0x0 0x100>, 205 <0x0 0x60004100 0x0 0x100>, 206 <0x0 0x60004200 0x0 0x100>, 207 <0x0 0x60004300 0x0 0x100>, 208 <0x0 0x60004400 0x0 0x100>; 209 interrupt-controller; 210 #interrupt-cells = <3>; 211 interrupt-parent = <&gic>; 212 }; 213 214 timer@60005000 { 215 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer"; 216 reg = <0x0 0x60005000 0x0 0x400>; 217 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 224 clock-names = "timer"; 225 }; 226 227 tegra_car: clock@60006000 { 228 compatible = "nvidia,tegra132-car"; 229 reg = <0x0 0x60006000 0x0 0x1000>; 230 #clock-cells = <1>; 231 #reset-cells = <1>; 232 nvidia,external-memory-controller = <&emc>; 233 }; 234 235 flow-controller@60007000 { 236 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; 237 reg = <0x0 0x60007000 0x0 0x1000>; 238 }; 239 240 actmon@6000c800 { 241 compatible = "nvidia,tegra124-actmon"; 242 reg = <0x0 0x6000c800 0x0 0x400>; 243 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 245 <&tegra_car TEGRA124_CLK_EMC>; 246 clock-names = "actmon", "emc"; 247 resets = <&tegra_car 119>; 248 reset-names = "actmon"; 249 operating-points-v2 = <&emc_bw_dfs_opp_table>; 250 interconnects = <&mc TEGRA124_MC_MPCORER &emc>; 251 interconnect-names = "cpu-read"; 252 #cooling-cells = <2>; 253 }; 254 255 gpio: gpio@6000d000 { 256 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 257 reg = <0x0 0x6000d000 0x0 0x1000>; 258 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 266 #gpio-cells = <2>; 267 gpio-controller; 268 #interrupt-cells = <2>; 269 interrupt-controller; 270 }; 271 272 apbdma: dma@60020000 { 273 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 274 reg = <0x0 0x60020000 0x0 0x1400>; 275 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 308 clock-names = "dma"; 309 resets = <&tegra_car 34>; 310 reset-names = "dma"; 311 #dma-cells = <1>; 312 }; 313 314 apbmisc@70000800 { 315 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 316 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 317 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 318 }; 319 320 pinmux: pinmux@70000868 { 321 compatible = "nvidia,tegra124-pinmux"; 322 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 323 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 324 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 325 }; 326 327 /* 328 * There are two serial driver i.e. 8250 based simple serial 329 * driver and APB DMA based serial driver for higher baudrate 330 * and performance. To enable the 8250 based driver, the compatible 331 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 332 * the APB DMA based serial driver, the compatible is 333 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 334 */ 335 uarta: serial@70006000 { 336 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 337 reg = <0x0 0x70006000 0x0 0x40>; 338 reg-shift = <2>; 339 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 341 resets = <&tegra_car 6>; 342 dmas = <&apbdma 8>, <&apbdma 8>; 343 dma-names = "rx", "tx"; 344 status = "disabled"; 345 }; 346 347 uartb: serial@70006040 { 348 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 349 reg = <0x0 0x70006040 0x0 0x40>; 350 reg-shift = <2>; 351 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 353 resets = <&tegra_car 7>; 354 dmas = <&apbdma 9>, <&apbdma 9>; 355 dma-names = "rx", "tx"; 356 status = "disabled"; 357 }; 358 359 uartc: serial@70006200 { 360 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 361 reg = <0x0 0x70006200 0x0 0x40>; 362 reg-shift = <2>; 363 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 365 resets = <&tegra_car 55>; 366 dmas = <&apbdma 10>, <&apbdma 10>; 367 dma-names = "rx", "tx"; 368 status = "disabled"; 369 }; 370 371 uartd: serial@70006300 { 372 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 373 reg = <0x0 0x70006300 0x0 0x40>; 374 reg-shift = <2>; 375 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 377 resets = <&tegra_car 65>; 378 dmas = <&apbdma 19>, <&apbdma 19>; 379 dma-names = "rx", "tx"; 380 status = "disabled"; 381 }; 382 383 pwm: pwm@7000a000 { 384 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 385 reg = <0x0 0x7000a000 0x0 0x100>; 386 #pwm-cells = <2>; 387 clocks = <&tegra_car TEGRA124_CLK_PWM>; 388 resets = <&tegra_car 17>; 389 reset-names = "pwm"; 390 status = "disabled"; 391 }; 392 393 i2c@7000c000 { 394 compatible = "nvidia,tegra124-i2c"; 395 reg = <0x0 0x7000c000 0x0 0x100>; 396 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 400 clock-names = "div-clk"; 401 resets = <&tegra_car 12>; 402 reset-names = "i2c"; 403 dmas = <&apbdma 21>, <&apbdma 21>; 404 dma-names = "rx", "tx"; 405 status = "disabled"; 406 }; 407 408 i2c@7000c400 { 409 compatible = "nvidia,tegra124-i2c"; 410 reg = <0x0 0x7000c400 0x0 0x100>; 411 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 415 clock-names = "div-clk"; 416 resets = <&tegra_car 54>; 417 reset-names = "i2c"; 418 dmas = <&apbdma 22>, <&apbdma 22>; 419 dma-names = "rx", "tx"; 420 status = "disabled"; 421 }; 422 423 i2c@7000c500 { 424 compatible = "nvidia,tegra124-i2c"; 425 reg = <0x0 0x7000c500 0x0 0x100>; 426 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 430 clock-names = "div-clk"; 431 resets = <&tegra_car 67>; 432 reset-names = "i2c"; 433 dmas = <&apbdma 23>, <&apbdma 23>; 434 dma-names = "rx", "tx"; 435 status = "disabled"; 436 }; 437 438 i2c@7000c700 { 439 compatible = "nvidia,tegra124-i2c"; 440 reg = <0x0 0x7000c700 0x0 0x100>; 441 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 445 clock-names = "div-clk"; 446 resets = <&tegra_car 103>; 447 reset-names = "i2c"; 448 dmas = <&apbdma 26>, <&apbdma 26>; 449 dma-names = "rx", "tx"; 450 status = "disabled"; 451 }; 452 453 i2c@7000d000 { 454 compatible = "nvidia,tegra124-i2c"; 455 reg = <0x0 0x7000d000 0x0 0x100>; 456 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 460 clock-names = "div-clk"; 461 resets = <&tegra_car 47>; 462 reset-names = "i2c"; 463 dmas = <&apbdma 24>, <&apbdma 24>; 464 dma-names = "rx", "tx"; 465 status = "disabled"; 466 }; 467 468 i2c@7000d100 { 469 compatible = "nvidia,tegra124-i2c"; 470 reg = <0x0 0x7000d100 0x0 0x100>; 471 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 475 clock-names = "div-clk"; 476 resets = <&tegra_car 166>; 477 reset-names = "i2c"; 478 dmas = <&apbdma 30>, <&apbdma 30>; 479 dma-names = "rx", "tx"; 480 status = "disabled"; 481 }; 482 483 spi@7000d400 { 484 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 485 reg = <0x0 0x7000d400 0x0 0x200>; 486 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 490 clock-names = "spi"; 491 resets = <&tegra_car 41>; 492 reset-names = "spi"; 493 dmas = <&apbdma 15>, <&apbdma 15>; 494 dma-names = "rx", "tx"; 495 status = "disabled"; 496 }; 497 498 spi@7000d600 { 499 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 500 reg = <0x0 0x7000d600 0x0 0x200>; 501 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 505 clock-names = "spi"; 506 resets = <&tegra_car 44>; 507 reset-names = "spi"; 508 dmas = <&apbdma 16>, <&apbdma 16>; 509 dma-names = "rx", "tx"; 510 status = "disabled"; 511 }; 512 513 spi@7000d800 { 514 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 515 reg = <0x0 0x7000d800 0x0 0x200>; 516 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 520 clock-names = "spi"; 521 resets = <&tegra_car 46>; 522 reset-names = "spi"; 523 dmas = <&apbdma 17>, <&apbdma 17>; 524 dma-names = "rx", "tx"; 525 status = "disabled"; 526 }; 527 528 spi@7000da00 { 529 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 530 reg = <0x0 0x7000da00 0x0 0x200>; 531 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 535 clock-names = "spi"; 536 resets = <&tegra_car 68>; 537 reset-names = "spi"; 538 dmas = <&apbdma 18>, <&apbdma 18>; 539 dma-names = "rx", "tx"; 540 status = "disabled"; 541 }; 542 543 spi@7000dc00 { 544 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 545 reg = <0x0 0x7000dc00 0x0 0x200>; 546 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 550 clock-names = "spi"; 551 resets = <&tegra_car 104>; 552 reset-names = "spi"; 553 dmas = <&apbdma 27>, <&apbdma 27>; 554 dma-names = "rx", "tx"; 555 status = "disabled"; 556 }; 557 558 spi@7000de00 { 559 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 560 reg = <0x0 0x7000de00 0x0 0x200>; 561 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 565 clock-names = "spi"; 566 resets = <&tegra_car 105>; 567 reset-names = "spi"; 568 dmas = <&apbdma 28>, <&apbdma 28>; 569 dma-names = "rx", "tx"; 570 status = "disabled"; 571 }; 572 573 rtc@7000e000 { 574 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 575 reg = <0x0 0x7000e000 0x0 0x100>; 576 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&tegra_car TEGRA124_CLK_RTC>; 578 clock-names = "rtc"; 579 }; 580 581 tegra_pmc: pmc@7000e400 { 582 compatible = "nvidia,tegra124-pmc"; 583 reg = <0x0 0x7000e400 0x0 0x400>; 584 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 585 clock-names = "pclk", "clk32k_in"; 586 #clock-cells = <1>; 587 }; 588 589 fuse@7000f800 { 590 compatible = "nvidia,tegra124-efuse"; 591 reg = <0x0 0x7000f800 0x0 0x400>; 592 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 593 clock-names = "fuse"; 594 resets = <&tegra_car 39>; 595 reset-names = "fuse"; 596 }; 597 598 mc: memory-controller@70019000 { 599 compatible = "nvidia,tegra132-mc"; 600 reg = <0x0 0x70019000 0x0 0x1000>; 601 clocks = <&tegra_car TEGRA124_CLK_MC>; 602 clock-names = "mc"; 603 604 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 605 606 #iommu-cells = <1>; 607 #reset-cells = <1>; 608 #interconnect-cells = <1>; 609 }; 610 611 emc: external-memory-controller@7001b000 { 612 compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; 613 reg = <0x0 0x7001b000 0x0 0x1000>; 614 clocks = <&tegra_car TEGRA124_CLK_EMC>; 615 clock-names = "emc"; 616 617 nvidia,memory-controller = <&mc>; 618 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 619 620 #interconnect-cells = <0>; 621 }; 622 623 sata@70020000 { 624 compatible = "nvidia,tegra124-ahci"; 625 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 626 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 627 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&tegra_car TEGRA124_CLK_SATA>, 629 <&tegra_car TEGRA124_CLK_SATA_OOB>; 630 clock-names = "sata", "sata-oob"; 631 resets = <&tegra_car 124>, 632 <&tegra_car 129>, 633 <&tegra_car 123>; 634 reset-names = "sata", "sata-cold", "sata-oob"; 635 status = "disabled"; 636 }; 637 638 hda@70030000 { 639 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", 640 "nvidia,tegra30-hda"; 641 reg = <0x0 0x70030000 0x0 0x10000>; 642 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&tegra_car TEGRA124_CLK_HDA>, 644 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 645 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 646 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 647 resets = <&tegra_car 125>, /* hda */ 648 <&tegra_car 128>, /* hda2hdmi */ 649 <&tegra_car 111>; /* hda2codec_2x */ 650 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 651 status = "disabled"; 652 }; 653 654 usb@70090000 { 655 compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"; 656 reg = <0x0 0x70090000 0x0 0x8000>, 657 <0x0 0x70098000 0x0 0x1000>, 658 <0x0 0x70099000 0x0 0x1000>; 659 reg-names = "hcd", "fpci", "ipfs"; 660 661 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 663 664 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, 665 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, 666 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, 667 <&tegra_car TEGRA124_CLK_XUSB_SS>, 668 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, 669 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, 670 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, 671 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, 672 <&tegra_car TEGRA124_CLK_PLL_U_480M>, 673 <&tegra_car TEGRA124_CLK_CLK_M>, 674 <&tegra_car TEGRA124_CLK_PLL_E>; 675 clock-names = "xusb_host", "xusb_host_src", 676 "xusb_falcon_src", "xusb_ss", 677 "xusb_ss_div2", "xusb_ss_src", 678 "xusb_hs_src", "xusb_fs_src", 679 "pll_u_480m", "clk_m", "pll_e"; 680 resets = <&tegra_car 89>, <&tegra_car 156>, 681 <&tegra_car 143>; 682 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 683 684 nvidia,xusb-padctl = <&padctl>; 685 686 status = "disabled"; 687 }; 688 689 padctl: padctl@7009f000 { 690 compatible = "nvidia,tegra132-xusb-padctl", 691 "nvidia,tegra124-xusb-padctl"; 692 reg = <0x0 0x7009f000 0x0 0x1000>; 693 resets = <&tegra_car 142>; 694 reset-names = "padctl"; 695 696 pads { 697 usb2 { 698 status = "disabled"; 699 700 lanes { 701 usb2-0 { 702 status = "disabled"; 703 #phy-cells = <0>; 704 }; 705 706 usb2-1 { 707 status = "disabled"; 708 #phy-cells = <0>; 709 }; 710 711 usb2-2 { 712 status = "disabled"; 713 #phy-cells = <0>; 714 }; 715 }; 716 }; 717 718 ulpi { 719 status = "disabled"; 720 721 lanes { 722 ulpi-0 { 723 status = "disabled"; 724 #phy-cells = <0>; 725 }; 726 }; 727 }; 728 729 hsic { 730 status = "disabled"; 731 732 lanes { 733 hsic-0 { 734 status = "disabled"; 735 #phy-cells = <0>; 736 }; 737 738 hsic-1 { 739 status = "disabled"; 740 #phy-cells = <0>; 741 }; 742 }; 743 }; 744 745 pcie { 746 status = "disabled"; 747 748 lanes { 749 pcie-0 { 750 status = "disabled"; 751 #phy-cells = <0>; 752 }; 753 754 pcie-1 { 755 status = "disabled"; 756 #phy-cells = <0>; 757 }; 758 759 pcie-2 { 760 status = "disabled"; 761 #phy-cells = <0>; 762 }; 763 764 pcie-3 { 765 status = "disabled"; 766 #phy-cells = <0>; 767 }; 768 769 pcie-4 { 770 status = "disabled"; 771 #phy-cells = <0>; 772 }; 773 }; 774 }; 775 776 sata { 777 status = "disabled"; 778 779 lanes { 780 sata-0 { 781 status = "disabled"; 782 #phy-cells = <0>; 783 }; 784 }; 785 }; 786 }; 787 788 ports { 789 usb2-0 { 790 status = "disabled"; 791 }; 792 793 usb2-1 { 794 status = "disabled"; 795 }; 796 797 usb2-2 { 798 status = "disabled"; 799 }; 800 801 hsic-0 { 802 status = "disabled"; 803 }; 804 805 hsic-1 { 806 status = "disabled"; 807 }; 808 809 usb3-0 { 810 status = "disabled"; 811 }; 812 813 usb3-1 { 814 status = "disabled"; 815 }; 816 }; 817 }; 818 819 mmc@700b0000 { 820 compatible = "nvidia,tegra124-sdhci"; 821 reg = <0x0 0x700b0000 0x0 0x200>; 822 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 824 clock-names = "sdhci"; 825 resets = <&tegra_car 14>; 826 reset-names = "sdhci"; 827 status = "disabled"; 828 }; 829 830 mmc@700b0200 { 831 compatible = "nvidia,tegra124-sdhci"; 832 reg = <0x0 0x700b0200 0x0 0x200>; 833 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 834 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 835 clock-names = "sdhci"; 836 resets = <&tegra_car 9>; 837 reset-names = "sdhci"; 838 status = "disabled"; 839 }; 840 841 mmc@700b0400 { 842 compatible = "nvidia,tegra124-sdhci"; 843 reg = <0x0 0x700b0400 0x0 0x200>; 844 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 846 clock-names = "sdhci"; 847 resets = <&tegra_car 69>; 848 reset-names = "sdhci"; 849 status = "disabled"; 850 }; 851 852 mmc@700b0600 { 853 compatible = "nvidia,tegra124-sdhci"; 854 reg = <0x0 0x700b0600 0x0 0x200>; 855 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 857 clock-names = "sdhci"; 858 resets = <&tegra_car 15>; 859 reset-names = "sdhci"; 860 status = "disabled"; 861 }; 862 863 soctherm: thermal-sensor@700e2000 { 864 compatible = "nvidia,tegra132-soctherm"; 865 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */ 866 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ 867 reg-names = "soctherm-reg", "ccroc-reg"; 868 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 870 interrupt-names = "thermal", "edp"; 871 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 872 <&tegra_car TEGRA124_CLK_SOC_THERM>; 873 clock-names = "tsensor", "soctherm"; 874 resets = <&tegra_car 78>; 875 reset-names = "soctherm"; 876 #thermal-sensor-cells = <1>; 877 878 throttle-cfgs { 879 throttle_heavy: heavy { 880 nvidia,priority = <100>; 881 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 882 883 #cooling-cells = <2>; 884 }; 885 }; 886 }; 887 888 ahub@70300000 { 889 compatible = "nvidia,tegra124-ahub"; 890 reg = <0x0 0x70300000 0x0 0x200>, 891 <0x0 0x70300800 0x0 0x800>, 892 <0x0 0x70300200 0x0 0x600>; 893 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 894 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 895 <&tegra_car TEGRA124_CLK_APBIF>; 896 clock-names = "d_audio", "apbif"; 897 resets = <&tegra_car 106>, /* d_audio */ 898 <&tegra_car 107>, /* apbif */ 899 <&tegra_car 30>, /* i2s0 */ 900 <&tegra_car 11>, /* i2s1 */ 901 <&tegra_car 18>, /* i2s2 */ 902 <&tegra_car 101>, /* i2s3 */ 903 <&tegra_car 102>, /* i2s4 */ 904 <&tegra_car 108>, /* dam0 */ 905 <&tegra_car 109>, /* dam1 */ 906 <&tegra_car 110>, /* dam2 */ 907 <&tegra_car 10>, /* spdif */ 908 <&tegra_car 153>, /* amx */ 909 <&tegra_car 185>, /* amx1 */ 910 <&tegra_car 154>, /* adx */ 911 <&tegra_car 180>, /* adx1 */ 912 <&tegra_car 186>, /* afc0 */ 913 <&tegra_car 187>, /* afc1 */ 914 <&tegra_car 188>, /* afc2 */ 915 <&tegra_car 189>, /* afc3 */ 916 <&tegra_car 190>, /* afc4 */ 917 <&tegra_car 191>; /* afc5 */ 918 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 919 "i2s3", "i2s4", "dam0", "dam1", "dam2", 920 "spdif", "amx", "amx1", "adx", "adx1", 921 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 922 dmas = <&apbdma 1>, <&apbdma 1>, 923 <&apbdma 2>, <&apbdma 2>, 924 <&apbdma 3>, <&apbdma 3>, 925 <&apbdma 4>, <&apbdma 4>, 926 <&apbdma 6>, <&apbdma 6>, 927 <&apbdma 7>, <&apbdma 7>, 928 <&apbdma 12>, <&apbdma 12>, 929 <&apbdma 13>, <&apbdma 13>, 930 <&apbdma 14>, <&apbdma 14>, 931 <&apbdma 29>, <&apbdma 29>; 932 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 933 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 934 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 935 "rx9", "tx9"; 936 ranges; 937 #address-cells = <2>; 938 #size-cells = <2>; 939 940 tegra_i2s0: i2s@70301000 { 941 compatible = "nvidia,tegra124-i2s"; 942 reg = <0x0 0x70301000 0x0 0x100>; 943 nvidia,ahub-cif-ids = <4 4>; 944 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 945 clock-names = "i2s"; 946 resets = <&tegra_car 30>; 947 reset-names = "i2s"; 948 status = "disabled"; 949 }; 950 951 tegra_i2s1: i2s@70301100 { 952 compatible = "nvidia,tegra124-i2s"; 953 reg = <0x0 0x70301100 0x0 0x100>; 954 nvidia,ahub-cif-ids = <5 5>; 955 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 956 clock-names = "i2s"; 957 resets = <&tegra_car 11>; 958 reset-names = "i2s"; 959 status = "disabled"; 960 }; 961 962 tegra_i2s2: i2s@70301200 { 963 compatible = "nvidia,tegra124-i2s"; 964 reg = <0x0 0x70301200 0x0 0x100>; 965 nvidia,ahub-cif-ids = <6 6>; 966 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 967 clock-names = "i2s"; 968 resets = <&tegra_car 18>; 969 reset-names = "i2s"; 970 status = "disabled"; 971 }; 972 973 tegra_i2s3: i2s@70301300 { 974 compatible = "nvidia,tegra124-i2s"; 975 reg = <0x0 0x70301300 0x0 0x100>; 976 nvidia,ahub-cif-ids = <7 7>; 977 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 978 clock-names = "i2s"; 979 resets = <&tegra_car 101>; 980 reset-names = "i2s"; 981 status = "disabled"; 982 }; 983 984 tegra_i2s4: i2s@70301400 { 985 compatible = "nvidia,tegra124-i2s"; 986 reg = <0x0 0x70301400 0x0 0x100>; 987 nvidia,ahub-cif-ids = <8 8>; 988 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 989 clock-names = "i2s"; 990 resets = <&tegra_car 102>; 991 reset-names = "i2s"; 992 status = "disabled"; 993 }; 994 }; 995 996 usb@7d000000 { 997 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 998 reg = <0x0 0x7d000000 0x0 0x4000>; 999 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1000 phy_type = "utmi"; 1001 clocks = <&tegra_car TEGRA124_CLK_USBD>; 1002 clock-names = "usb"; 1003 resets = <&tegra_car 22>; 1004 reset-names = "usb"; 1005 nvidia,phy = <&phy1>; 1006 status = "disabled"; 1007 }; 1008 1009 phy1: usb-phy@7d000000 { 1010 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1011 reg = <0x0 0x7d000000 0x0 0x4000>, 1012 <0x0 0x7d000000 0x0 0x4000>; 1013 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1014 phy_type = "utmi"; 1015 clocks = <&tegra_car TEGRA124_CLK_USBD>, 1016 <&tegra_car TEGRA124_CLK_PLL_U>, 1017 <&tegra_car TEGRA124_CLK_USBD>; 1018 clock-names = "reg", "pll_u", "utmi-pads"; 1019 resets = <&tegra_car 22>, <&tegra_car 22>; 1020 reset-names = "usb", "utmi-pads"; 1021 #phy-cells = <0>; 1022 nvidia,hssync-start-delay = <0>; 1023 nvidia,idle-wait-delay = <17>; 1024 nvidia,elastic-limit = <16>; 1025 nvidia,term-range-adj = <6>; 1026 nvidia,xcvr-setup = <9>; 1027 nvidia,xcvr-lsfslew = <0>; 1028 nvidia,xcvr-lsrslew = <3>; 1029 nvidia,hssquelch-level = <2>; 1030 nvidia,hsdiscon-level = <5>; 1031 nvidia,xcvr-hsslew = <12>; 1032 nvidia,has-utmi-pad-registers; 1033 nvidia,pmc = <&tegra_pmc 0>; 1034 status = "disabled"; 1035 }; 1036 1037 usb@7d004000 { 1038 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1039 reg = <0x0 0x7d004000 0x0 0x4000>; 1040 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1041 phy_type = "utmi"; 1042 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1043 clock-names = "usb"; 1044 resets = <&tegra_car 58>; 1045 reset-names = "usb"; 1046 nvidia,phy = <&phy2>; 1047 status = "disabled"; 1048 }; 1049 1050 phy2: usb-phy@7d004000 { 1051 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1052 reg = <0x0 0x7d004000 0x0 0x4000>, 1053 <0x0 0x7d000000 0x0 0x4000>; 1054 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1055 phy_type = "utmi"; 1056 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1057 <&tegra_car TEGRA124_CLK_PLL_U>, 1058 <&tegra_car TEGRA124_CLK_USBD>; 1059 clock-names = "reg", "pll_u", "utmi-pads"; 1060 resets = <&tegra_car 58>, <&tegra_car 22>; 1061 reset-names = "usb", "utmi-pads"; 1062 #phy-cells = <0>; 1063 nvidia,hssync-start-delay = <0>; 1064 nvidia,idle-wait-delay = <17>; 1065 nvidia,elastic-limit = <16>; 1066 nvidia,term-range-adj = <6>; 1067 nvidia,xcvr-setup = <9>; 1068 nvidia,xcvr-lsfslew = <0>; 1069 nvidia,xcvr-lsrslew = <3>; 1070 nvidia,hssquelch-level = <2>; 1071 nvidia,hsdiscon-level = <5>; 1072 nvidia,xcvr-hsslew = <12>; 1073 nvidia,pmc = <&tegra_pmc 1>; 1074 status = "disabled"; 1075 }; 1076 1077 usb@7d008000 { 1078 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1079 reg = <0x0 0x7d008000 0x0 0x4000>; 1080 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1081 phy_type = "utmi"; 1082 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1083 clock-names = "usb"; 1084 resets = <&tegra_car 59>; 1085 reset-names = "usb"; 1086 nvidia,phy = <&phy3>; 1087 status = "disabled"; 1088 }; 1089 1090 phy3: usb-phy@7d008000 { 1091 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1092 reg = <0x0 0x7d008000 0x0 0x4000>, 1093 <0x0 0x7d000000 0x0 0x4000>; 1094 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1095 phy_type = "utmi"; 1096 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1097 <&tegra_car TEGRA124_CLK_PLL_U>, 1098 <&tegra_car TEGRA124_CLK_USBD>; 1099 clock-names = "reg", "pll_u", "utmi-pads"; 1100 resets = <&tegra_car 59>, <&tegra_car 22>; 1101 reset-names = "usb", "utmi-pads"; 1102 #phy-cells = <0>; 1103 nvidia,hssync-start-delay = <0>; 1104 nvidia,idle-wait-delay = <17>; 1105 nvidia,elastic-limit = <16>; 1106 nvidia,term-range-adj = <6>; 1107 nvidia,xcvr-setup = <9>; 1108 nvidia,xcvr-lsfslew = <0>; 1109 nvidia,xcvr-lsrslew = <3>; 1110 nvidia,hssquelch-level = <2>; 1111 nvidia,hsdiscon-level = <5>; 1112 nvidia,xcvr-hsslew = <12>; 1113 nvidia,pmc = <&tegra_pmc 2>; 1114 status = "disabled"; 1115 }; 1116 1117 cpus { 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 1121 cpu@0 { 1122 device_type = "cpu"; 1123 compatible = "nvidia,tegra132-denver"; 1124 reg = <0>; 1125 }; 1126 1127 cpu@1 { 1128 device_type = "cpu"; 1129 compatible = "nvidia,tegra132-denver"; 1130 reg = <1>; 1131 }; 1132 }; 1133 1134 thermal-zones { 1135 cpu-thermal { 1136 polling-delay-passive = <1000>; 1137 polling-delay = <0>; 1138 1139 thermal-sensors = 1140 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1141 1142 trips { 1143 cpu_shutdown_trip { 1144 temperature = <105000>; 1145 hysteresis = <1000>; 1146 type = "critical"; 1147 }; 1148 1149 cpu_throttle_trip: throttle-trip { 1150 temperature = <102000>; 1151 hysteresis = <1000>; 1152 type = "hot"; 1153 }; 1154 }; 1155 1156 cooling-maps { 1157 map0 { 1158 trip = <&cpu_throttle_trip>; 1159 cooling-device = <&throttle_heavy 1 1>; 1160 }; 1161 }; 1162 }; 1163 1164 mem-thermal { 1165 polling-delay-passive = <0>; 1166 polling-delay = <0>; 1167 1168 thermal-sensors = 1169 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1170 1171 trips { 1172 mem_shutdown_trip { 1173 temperature = <101000>; 1174 hysteresis = <1000>; 1175 type = "critical"; 1176 }; 1177 mem_throttle_trip { 1178 temperature = <99000>; 1179 hysteresis = <1000>; 1180 type = "hot"; 1181 }; 1182 }; 1183 1184 cooling-maps { 1185 /* 1186 * There are currently no cooling maps, 1187 * because there are no cooling devices. 1188 */ 1189 }; 1190 }; 1191 1192 gpu-thermal { 1193 polling-delay-passive = <1000>; 1194 polling-delay = <0>; 1195 1196 thermal-sensors = 1197 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1198 1199 trips { 1200 gpu_shutdown_trip { 1201 temperature = <101000>; 1202 hysteresis = <1000>; 1203 type = "critical"; 1204 }; 1205 1206 gpu_throttle_trip: throttle-trip { 1207 temperature = <99000>; 1208 hysteresis = <1000>; 1209 type = "hot"; 1210 }; 1211 }; 1212 1213 cooling-maps { 1214 map0 { 1215 trip = <&gpu_throttle_trip>; 1216 cooling-device = <&throttle_heavy 1 1>; 1217 }; 1218 }; 1219 }; 1220 1221 pllx-thermal { 1222 polling-delay-passive = <0>; 1223 polling-delay = <0>; 1224 1225 thermal-sensors = 1226 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1227 1228 trips { 1229 pllx_shutdown_trip { 1230 temperature = <105000>; 1231 hysteresis = <1000>; 1232 type = "critical"; 1233 }; 1234 pllx_throttle_trip { 1235 temperature = <99000>; 1236 hysteresis = <1000>; 1237 type = "hot"; 1238 }; 1239 }; 1240 1241 cooling-maps { 1242 /* 1243 * There are currently no cooling maps, 1244 * because there are no cooling devices. 1245 */ 1246 }; 1247 }; 1248 }; 1249 1250 timer { 1251 compatible = "arm,armv7-timer"; 1252 interrupts = <GIC_PPI 13 1253 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1254 <GIC_PPI 14 1255 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1256 <GIC_PPI 11 1257 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1258 <GIC_PPI 10 1259 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1260 interrupt-parent = <&gic>; 1261 }; 1262}; 1263
