1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Eddie Huang <eddie.huang@mediatek.com> 5 */ 6 7#include <dt-bindings/clock/mt8173-clk.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/memory/mt8173-larb-port.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/power/mt8173-power.h> 13#include <dt-bindings/reset/mt8173-resets.h> 14#include <dt-bindings/gce/mt8173-gce.h> 15#include <dt-bindings/thermal/thermal.h> 16#include "mt8173-pinfunc.h" 17 18/ { 19 compatible = "mediatek,mt8173"; 20 interrupt-parent = <&sysirq>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 ovl0 = &ovl0; 26 ovl1 = &ovl1; 27 rdma0 = &rdma0; 28 rdma1 = &rdma1; 29 rdma2 = &rdma2; 30 wdma0 = &wdma0; 31 wdma1 = &wdma1; 32 color0 = &color0; 33 color1 = &color1; 34 split0 = &split0; 35 split1 = &split1; 36 dpi0 = &dpi0; 37 dsi0 = &dsi0; 38 dsi1 = &dsi1; 39 mdp-rdma0 = &mdp_rdma0; 40 mdp-rdma1 = &mdp_rdma1; 41 mdp-rsz0 = &mdp_rsz0; 42 mdp-rsz1 = &mdp_rsz1; 43 mdp-rsz2 = &mdp_rsz2; 44 mdp-wdma0 = &mdp_wdma0; 45 mdp-wrot0 = &mdp_wrot0; 46 mdp-wrot1 = &mdp_wrot1; 47 serial0 = &uart0; 48 serial1 = &uart1; 49 serial2 = &uart2; 50 serial3 = &uart3; 51 }; 52 53 cluster0_opp: opp-table-0 { 54 compatible = "operating-points-v2"; 55 opp-shared; 56 opp-507000000 { 57 opp-hz = /bits/ 64 <507000000>; 58 opp-microvolt = <859000>; 59 }; 60 opp-702000000 { 61 opp-hz = /bits/ 64 <702000000>; 62 opp-microvolt = <908000>; 63 }; 64 opp-1001000000 { 65 opp-hz = /bits/ 64 <1001000000>; 66 opp-microvolt = <983000>; 67 }; 68 opp-1105000000 { 69 opp-hz = /bits/ 64 <1105000000>; 70 opp-microvolt = <1009000>; 71 }; 72 opp-1209000000 { 73 opp-hz = /bits/ 64 <1209000000>; 74 opp-microvolt = <1034000>; 75 }; 76 opp-1300000000 { 77 opp-hz = /bits/ 64 <1300000000>; 78 opp-microvolt = <1057000>; 79 }; 80 opp-1508000000 { 81 opp-hz = /bits/ 64 <1508000000>; 82 opp-microvolt = <1109000>; 83 }; 84 opp-1703000000 { 85 opp-hz = /bits/ 64 <1703000000>; 86 opp-microvolt = <1125000>; 87 }; 88 }; 89 90 cluster1_opp: opp-table-1 { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 opp-507000000 { 94 opp-hz = /bits/ 64 <507000000>; 95 opp-microvolt = <828000>; 96 }; 97 opp-702000000 { 98 opp-hz = /bits/ 64 <702000000>; 99 opp-microvolt = <867000>; 100 }; 101 opp-1001000000 { 102 opp-hz = /bits/ 64 <1001000000>; 103 opp-microvolt = <927000>; 104 }; 105 opp-1209000000 { 106 opp-hz = /bits/ 64 <1209000000>; 107 opp-microvolt = <968000>; 108 }; 109 opp-1404000000 { 110 opp-hz = /bits/ 64 <1404000000>; 111 opp-microvolt = <1007000>; 112 }; 113 opp-1612000000 { 114 opp-hz = /bits/ 64 <1612000000>; 115 opp-microvolt = <1049000>; 116 }; 117 opp-1807000000 { 118 opp-hz = /bits/ 64 <1807000000>; 119 opp-microvolt = <1089000>; 120 }; 121 opp-2106000000 { 122 opp-hz = /bits/ 64 <2106000000>; 123 opp-microvolt = <1125000>; 124 }; 125 }; 126 127 cpus { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 131 cpu-map { 132 cluster0 { 133 core0 { 134 cpu = <&cpu0>; 135 }; 136 core1 { 137 cpu = <&cpu1>; 138 }; 139 }; 140 141 cluster1 { 142 core0 { 143 cpu = <&cpu2>; 144 }; 145 core1 { 146 cpu = <&cpu3>; 147 }; 148 }; 149 }; 150 151 cpu0: cpu@0 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a53"; 154 reg = <0x000>; 155 enable-method = "psci"; 156 cpu-idle-states = <&CPU_SLEEP_0>; 157 #cooling-cells = <2>; 158 dynamic-power-coefficient = <263>; 159 clocks = <&infracfg CLK_INFRA_CA53SEL>, 160 <&apmixedsys CLK_APMIXED_MAINPLL>; 161 clock-names = "cpu", "intermediate"; 162 operating-points-v2 = <&cluster0_opp>; 163 capacity-dmips-mhz = <740>; 164 }; 165 166 cpu1: cpu@1 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a53"; 169 reg = <0x001>; 170 enable-method = "psci"; 171 cpu-idle-states = <&CPU_SLEEP_0>; 172 #cooling-cells = <2>; 173 dynamic-power-coefficient = <263>; 174 clocks = <&infracfg CLK_INFRA_CA53SEL>, 175 <&apmixedsys CLK_APMIXED_MAINPLL>; 176 clock-names = "cpu", "intermediate"; 177 operating-points-v2 = <&cluster0_opp>; 178 capacity-dmips-mhz = <740>; 179 }; 180 181 cpu2: cpu@100 { 182 device_type = "cpu"; 183 compatible = "arm,cortex-a72"; 184 reg = <0x100>; 185 enable-method = "psci"; 186 cpu-idle-states = <&CPU_SLEEP_0>; 187 #cooling-cells = <2>; 188 dynamic-power-coefficient = <530>; 189 clocks = <&infracfg CLK_INFRA_CA72SEL>, 190 <&apmixedsys CLK_APMIXED_MAINPLL>; 191 clock-names = "cpu", "intermediate"; 192 operating-points-v2 = <&cluster1_opp>; 193 capacity-dmips-mhz = <1024>; 194 }; 195 196 cpu3: cpu@101 { 197 device_type = "cpu"; 198 compatible = "arm,cortex-a72"; 199 reg = <0x101>; 200 enable-method = "psci"; 201 cpu-idle-states = <&CPU_SLEEP_0>; 202 #cooling-cells = <2>; 203 dynamic-power-coefficient = <530>; 204 clocks = <&infracfg CLK_INFRA_CA72SEL>, 205 <&apmixedsys CLK_APMIXED_MAINPLL>; 206 clock-names = "cpu", "intermediate"; 207 operating-points-v2 = <&cluster1_opp>; 208 capacity-dmips-mhz = <1024>; 209 }; 210 211 idle-states { 212 entry-method = "psci"; 213 214 CPU_SLEEP_0: cpu-sleep-0 { 215 compatible = "arm,idle-state"; 216 local-timer-stop; 217 entry-latency-us = <639>; 218 exit-latency-us = <680>; 219 min-residency-us = <1088>; 220 arm,psci-suspend-param = <0x0010000>; 221 }; 222 }; 223 }; 224 225 pmu_a53 { 226 compatible = "arm,cortex-a53-pmu"; 227 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 228 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; 229 interrupt-affinity = <&cpu0>, <&cpu1>; 230 }; 231 232 pmu_a72 { 233 compatible = "arm,cortex-a72-pmu"; 234 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, 235 <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; 236 interrupt-affinity = <&cpu2>, <&cpu3>; 237 }; 238 239 psci { 240 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 241 method = "smc"; 242 cpu_suspend = <0x84000001>; 243 cpu_off = <0x84000002>; 244 cpu_on = <0x84000003>; 245 }; 246 247 clk26m: oscillator0 { 248 compatible = "fixed-clock"; 249 #clock-cells = <0>; 250 clock-frequency = <26000000>; 251 clock-output-names = "clk26m"; 252 }; 253 254 clk32k: oscillator1 { 255 compatible = "fixed-clock"; 256 #clock-cells = <0>; 257 clock-frequency = <32000>; 258 clock-output-names = "clk32k"; 259 }; 260 261 cpum_ck: oscillator2 { 262 compatible = "fixed-clock"; 263 #clock-cells = <0>; 264 clock-frequency = <0>; 265 clock-output-names = "cpum_ck"; 266 }; 267 268 thermal-zones { 269 cpu_thermal: cpu-thermal { 270 polling-delay-passive = <1000>; /* milliseconds */ 271 polling-delay = <1000>; /* milliseconds */ 272 273 thermal-sensors = <&thermal>; 274 sustainable-power = <1500>; /* milliwatts */ 275 276 trips { 277 threshold: trip-point0 { 278 temperature = <68000>; 279 hysteresis = <2000>; 280 type = "passive"; 281 }; 282 283 target: trip-point1 { 284 temperature = <85000>; 285 hysteresis = <2000>; 286 type = "passive"; 287 }; 288 289 cpu_crit: cpu_crit0 { 290 temperature = <115000>; 291 hysteresis = <2000>; 292 type = "critical"; 293 }; 294 }; 295 296 cooling-maps { 297 map0 { 298 trip = <&target>; 299 cooling-device = <&cpu0 THERMAL_NO_LIMIT 300 THERMAL_NO_LIMIT>, 301 <&cpu1 THERMAL_NO_LIMIT 302 THERMAL_NO_LIMIT>; 303 contribution = <3072>; 304 }; 305 map1 { 306 trip = <&target>; 307 cooling-device = <&cpu2 THERMAL_NO_LIMIT 308 THERMAL_NO_LIMIT>, 309 <&cpu3 THERMAL_NO_LIMIT 310 THERMAL_NO_LIMIT>; 311 contribution = <1024>; 312 }; 313 }; 314 }; 315 }; 316 317 reserved-memory { 318 #address-cells = <2>; 319 #size-cells = <2>; 320 ranges; 321 vpu_dma_reserved: vpu_dma_mem_region@b7000000 { 322 compatible = "shared-dma-pool"; 323 reg = <0 0xb7000000 0 0x500000>; 324 alignment = <0x1000>; 325 no-map; 326 }; 327 }; 328 329 timer { 330 compatible = "arm,armv8-timer"; 331 interrupt-parent = <&gic>; 332 interrupts = <GIC_PPI 13 333 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 334 <GIC_PPI 14 335 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 336 <GIC_PPI 11 337 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 338 <GIC_PPI 10 339 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 340 arm,no-tick-in-suspend; 341 }; 342 343 soc { 344 #address-cells = <2>; 345 #size-cells = <2>; 346 compatible = "simple-bus"; 347 ranges; 348 349 topckgen: clock-controller@10000000 { 350 compatible = "mediatek,mt8173-topckgen"; 351 reg = <0 0x10000000 0 0x1000>; 352 #clock-cells = <1>; 353 }; 354 355 infracfg: power-controller@10001000 { 356 compatible = "mediatek,mt8173-infracfg", "syscon"; 357 reg = <0 0x10001000 0 0x1000>; 358 #clock-cells = <1>; 359 #reset-cells = <1>; 360 }; 361 362 pericfg: power-controller@10003000 { 363 compatible = "mediatek,mt8173-pericfg", "syscon"; 364 reg = <0 0x10003000 0 0x1000>; 365 #clock-cells = <1>; 366 #reset-cells = <1>; 367 }; 368 369 syscfg_pctl_a: syscfg_pctl_a@10005000 { 370 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 371 reg = <0 0x10005000 0 0x1000>; 372 }; 373 374 pio: pinctrl@1000b000 { 375 compatible = "mediatek,mt8173-pinctrl"; 376 reg = <0 0x1000b000 0 0x1000>; 377 mediatek,pctl-regmap = <&syscfg_pctl_a>; 378 gpio-controller; 379 #gpio-cells = <2>; 380 interrupt-controller; 381 #interrupt-cells = <2>; 382 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 385 386 hdmi_pin: xxx { 387 388 /*hdmi htplg pin*/ 389 pins1 { 390 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 391 input-enable; 392 bias-pull-down; 393 }; 394 }; 395 396 i2c0_pins_a: i2c0 { 397 pins1 { 398 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 399 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 400 bias-disable; 401 }; 402 }; 403 404 i2c1_pins_a: i2c1 { 405 pins1 { 406 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 407 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 408 bias-disable; 409 }; 410 }; 411 412 i2c2_pins_a: i2c2 { 413 pins1 { 414 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 415 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 416 bias-disable; 417 }; 418 }; 419 420 i2c3_pins_a: i2c3 { 421 pins1 { 422 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 423 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 424 bias-disable; 425 }; 426 }; 427 428 i2c4_pins_a: i2c4 { 429 pins1 { 430 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 431 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 432 bias-disable; 433 }; 434 }; 435 436 i2c6_pins_a: i2c6 { 437 pins1 { 438 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 439 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 440 bias-disable; 441 }; 442 }; 443 }; 444 445 scpsys: syscon@10006000 { 446 compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd"; 447 reg = <0 0x10006000 0 0x1000>; 448 449 /* System Power Manager */ 450 spm: power-controller { 451 compatible = "mediatek,mt8173-power-controller"; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 #power-domain-cells = <1>; 455 456 /* power domains of the SoC */ 457 power-domain@MT8173_POWER_DOMAIN_VDEC { 458 reg = <MT8173_POWER_DOMAIN_VDEC>; 459 clocks = <&topckgen CLK_TOP_MM_SEL>; 460 clock-names = "mm"; 461 #power-domain-cells = <0>; 462 }; 463 power-domain@MT8173_POWER_DOMAIN_VENC { 464 reg = <MT8173_POWER_DOMAIN_VENC>; 465 clocks = <&topckgen CLK_TOP_MM_SEL>, 466 <&topckgen CLK_TOP_VENC_SEL>; 467 clock-names = "mm", "venc"; 468 #power-domain-cells = <0>; 469 }; 470 power-domain@MT8173_POWER_DOMAIN_ISP { 471 reg = <MT8173_POWER_DOMAIN_ISP>; 472 clocks = <&topckgen CLK_TOP_MM_SEL>; 473 clock-names = "mm"; 474 #power-domain-cells = <0>; 475 }; 476 power-domain@MT8173_POWER_DOMAIN_MM { 477 reg = <MT8173_POWER_DOMAIN_MM>; 478 clocks = <&topckgen CLK_TOP_MM_SEL>; 479 clock-names = "mm"; 480 #power-domain-cells = <0>; 481 mediatek,infracfg = <&infracfg>; 482 }; 483 power-domain@MT8173_POWER_DOMAIN_VENC_LT { 484 reg = <MT8173_POWER_DOMAIN_VENC_LT>; 485 clocks = <&topckgen CLK_TOP_MM_SEL>, 486 <&topckgen CLK_TOP_VENC_LT_SEL>; 487 clock-names = "mm", "venclt"; 488 #power-domain-cells = <0>; 489 }; 490 power-domain@MT8173_POWER_DOMAIN_AUDIO { 491 reg = <MT8173_POWER_DOMAIN_AUDIO>; 492 #power-domain-cells = <0>; 493 }; 494 power-domain@MT8173_POWER_DOMAIN_USB { 495 reg = <MT8173_POWER_DOMAIN_USB>; 496 #power-domain-cells = <0>; 497 }; 498 mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { 499 reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>; 500 clocks = <&clk26m>; 501 clock-names = "mfg"; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 #power-domain-cells = <1>; 505 506 power-domain@MT8173_POWER_DOMAIN_MFG_2D { 507 reg = <MT8173_POWER_DOMAIN_MFG_2D>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 #power-domain-cells = <1>; 511 512 power-domain@MT8173_POWER_DOMAIN_MFG { 513 reg = <MT8173_POWER_DOMAIN_MFG>; 514 #power-domain-cells = <0>; 515 mediatek,infracfg = <&infracfg>; 516 }; 517 }; 518 }; 519 }; 520 }; 521 522 watchdog: watchdog@10007000 { 523 compatible = "mediatek,mt8173-wdt", 524 "mediatek,mt6589-wdt"; 525 reg = <0 0x10007000 0 0x100>; 526 }; 527 528 timer: timer@10008000 { 529 compatible = "mediatek,mt8173-timer", 530 "mediatek,mt6577-timer"; 531 reg = <0 0x10008000 0 0x1000>; 532 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 533 clocks = <&infracfg CLK_INFRA_CLK_13M>, 534 <&topckgen CLK_TOP_RTC_SEL>; 535 }; 536 537 pwrap: pwrap@1000d000 { 538 compatible = "mediatek,mt8173-pwrap"; 539 reg = <0 0x1000d000 0 0x1000>; 540 reg-names = "pwrap"; 541 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 542 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 543 reset-names = "pwrap"; 544 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 545 clock-names = "spi", "wrap"; 546 }; 547 548 cec: cec@10013000 { 549 compatible = "mediatek,mt8173-cec"; 550 reg = <0 0x10013000 0 0xbc>; 551 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 552 clocks = <&infracfg CLK_INFRA_CEC>; 553 status = "disabled"; 554 }; 555 556 vpu: vpu@10020000 { 557 compatible = "mediatek,mt8173-vpu"; 558 reg = <0 0x10020000 0 0x30000>, 559 <0 0x10050000 0 0x100>; 560 reg-names = "tcm", "cfg_reg"; 561 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&topckgen CLK_TOP_SCP_SEL>; 563 clock-names = "main"; 564 memory-region = <&vpu_dma_reserved>; 565 }; 566 567 sysirq: intpol-controller@10200620 { 568 compatible = "mediatek,mt8173-sysirq", 569 "mediatek,mt6577-sysirq"; 570 interrupt-controller; 571 #interrupt-cells = <3>; 572 interrupt-parent = <&gic>; 573 reg = <0 0x10200620 0 0x20>; 574 }; 575 576 iommu: iommu@10205000 { 577 compatible = "mediatek,mt8173-m4u"; 578 reg = <0 0x10205000 0 0x1000>; 579 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 580 clocks = <&infracfg CLK_INFRA_M4U>; 581 clock-names = "bclk"; 582 mediatek,infracfg = <&infracfg>; 583 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 584 <&larb3>, <&larb4>, <&larb5>; 585 #iommu-cells = <1>; 586 }; 587 588 efuse: efuse@10206000 { 589 compatible = "mediatek,mt8173-efuse"; 590 reg = <0 0x10206000 0 0x1000>; 591 #address-cells = <1>; 592 #size-cells = <1>; 593 thermal_calibration: calib@528 { 594 reg = <0x528 0xc>; 595 }; 596 }; 597 598 apmixedsys: clock-controller@10209000 { 599 compatible = "mediatek,mt8173-apmixedsys"; 600 reg = <0 0x10209000 0 0x1000>; 601 #clock-cells = <1>; 602 }; 603 604 hdmi_phy: hdmi-phy@10209100 { 605 compatible = "mediatek,mt8173-hdmi-phy"; 606 reg = <0 0x10209100 0 0x24>; 607 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 608 clock-names = "pll_ref"; 609 clock-output-names = "hdmitx_dig_cts"; 610 mediatek,ibias = <0xa>; 611 mediatek,ibias_up = <0x1c>; 612 #clock-cells = <0>; 613 #phy-cells = <0>; 614 status = "disabled"; 615 }; 616 617 gce: mailbox@10212000 { 618 compatible = "mediatek,mt8173-gce"; 619 reg = <0 0x10212000 0 0x1000>; 620 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 621 clocks = <&infracfg CLK_INFRA_GCE>; 622 clock-names = "gce"; 623 #mbox-cells = <2>; 624 }; 625 626 mipi_tx0: dsi-phy@10215000 { 627 compatible = "mediatek,mt8173-mipi-tx"; 628 reg = <0 0x10215000 0 0x1000>; 629 clocks = <&clk26m>; 630 clock-output-names = "mipi_tx0_pll"; 631 #clock-cells = <0>; 632 #phy-cells = <0>; 633 status = "disabled"; 634 }; 635 636 mipi_tx1: dsi-phy@10216000 { 637 compatible = "mediatek,mt8173-mipi-tx"; 638 reg = <0 0x10216000 0 0x1000>; 639 clocks = <&clk26m>; 640 clock-output-names = "mipi_tx1_pll"; 641 #clock-cells = <0>; 642 #phy-cells = <0>; 643 status = "disabled"; 644 }; 645 646 gic: interrupt-controller@10221000 { 647 compatible = "arm,gic-400"; 648 #interrupt-cells = <3>; 649 interrupt-parent = <&gic>; 650 interrupt-controller; 651 reg = <0 0x10221000 0 0x1000>, 652 <0 0x10222000 0 0x2000>, 653 <0 0x10224000 0 0x2000>, 654 <0 0x10226000 0 0x2000>; 655 interrupts = <GIC_PPI 9 656 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 657 }; 658 659 auxadc: auxadc@11001000 { 660 compatible = "mediatek,mt8173-auxadc"; 661 reg = <0 0x11001000 0 0x1000>; 662 clocks = <&pericfg CLK_PERI_AUXADC>; 663 clock-names = "main"; 664 #io-channel-cells = <1>; 665 }; 666 667 uart0: serial@11002000 { 668 compatible = "mediatek,mt8173-uart", 669 "mediatek,mt6577-uart"; 670 reg = <0 0x11002000 0 0x400>; 671 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 672 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 673 clock-names = "baud", "bus"; 674 status = "disabled"; 675 }; 676 677 uart1: serial@11003000 { 678 compatible = "mediatek,mt8173-uart", 679 "mediatek,mt6577-uart"; 680 reg = <0 0x11003000 0 0x400>; 681 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 682 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 683 clock-names = "baud", "bus"; 684 status = "disabled"; 685 }; 686 687 uart2: serial@11004000 { 688 compatible = "mediatek,mt8173-uart", 689 "mediatek,mt6577-uart"; 690 reg = <0 0x11004000 0 0x400>; 691 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 692 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 693 clock-names = "baud", "bus"; 694 status = "disabled"; 695 }; 696 697 uart3: serial@11005000 { 698 compatible = "mediatek,mt8173-uart", 699 "mediatek,mt6577-uart"; 700 reg = <0 0x11005000 0 0x400>; 701 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 702 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 703 clock-names = "baud", "bus"; 704 status = "disabled"; 705 }; 706 707 i2c0: i2c@11007000 { 708 compatible = "mediatek,mt8173-i2c"; 709 reg = <0 0x11007000 0 0x70>, 710 <0 0x11000100 0 0x80>; 711 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 712 clock-div = <16>; 713 clocks = <&pericfg CLK_PERI_I2C0>, 714 <&pericfg CLK_PERI_AP_DMA>; 715 clock-names = "main", "dma"; 716 pinctrl-names = "default"; 717 pinctrl-0 = <&i2c0_pins_a>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 status = "disabled"; 721 }; 722 723 i2c1: i2c@11008000 { 724 compatible = "mediatek,mt8173-i2c"; 725 reg = <0 0x11008000 0 0x70>, 726 <0 0x11000180 0 0x80>; 727 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 728 clock-div = <16>; 729 clocks = <&pericfg CLK_PERI_I2C1>, 730 <&pericfg CLK_PERI_AP_DMA>; 731 clock-names = "main", "dma"; 732 pinctrl-names = "default"; 733 pinctrl-0 = <&i2c1_pins_a>; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 status = "disabled"; 737 }; 738 739 i2c2: i2c@11009000 { 740 compatible = "mediatek,mt8173-i2c"; 741 reg = <0 0x11009000 0 0x70>, 742 <0 0x11000200 0 0x80>; 743 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 744 clock-div = <16>; 745 clocks = <&pericfg CLK_PERI_I2C2>, 746 <&pericfg CLK_PERI_AP_DMA>; 747 clock-names = "main", "dma"; 748 pinctrl-names = "default"; 749 pinctrl-0 = <&i2c2_pins_a>; 750 #address-cells = <1>; 751 #size-cells = <0>; 752 status = "disabled"; 753 }; 754 755 spi: spi@1100a000 { 756 compatible = "mediatek,mt8173-spi"; 757 #address-cells = <1>; 758 #size-cells = <0>; 759 reg = <0 0x1100a000 0 0x1000>; 760 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 761 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 762 <&topckgen CLK_TOP_SPI_SEL>, 763 <&pericfg CLK_PERI_SPI0>; 764 clock-names = "parent-clk", "sel-clk", "spi-clk"; 765 status = "disabled"; 766 }; 767 768 thermal: thermal@1100b000 { 769 #thermal-sensor-cells = <0>; 770 compatible = "mediatek,mt8173-thermal"; 771 reg = <0 0x1100b000 0 0x1000>; 772 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 773 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 774 clock-names = "therm", "auxadc"; 775 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 776 mediatek,auxadc = <&auxadc>; 777 mediatek,apmixedsys = <&apmixedsys>; 778 nvmem-cells = <&thermal_calibration>; 779 nvmem-cell-names = "calibration-data"; 780 }; 781 782 nor_flash: spi@1100d000 { 783 compatible = "mediatek,mt8173-nor"; 784 reg = <0 0x1100d000 0 0xe0>; 785 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>; 786 assigned-clock-parents = <&clk26m>; 787 clocks = <&pericfg CLK_PERI_SPI>, 788 <&topckgen CLK_TOP_SPINFI_IFR_SEL>, 789 <&pericfg CLK_PERI_NFI>; 790 clock-names = "spi", "sf", "axi"; 791 #address-cells = <1>; 792 #size-cells = <0>; 793 status = "disabled"; 794 }; 795 796 i2c3: i2c@11010000 { 797 compatible = "mediatek,mt8173-i2c"; 798 reg = <0 0x11010000 0 0x70>, 799 <0 0x11000280 0 0x80>; 800 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 801 clock-div = <16>; 802 clocks = <&pericfg CLK_PERI_I2C3>, 803 <&pericfg CLK_PERI_AP_DMA>; 804 clock-names = "main", "dma"; 805 pinctrl-names = "default"; 806 pinctrl-0 = <&i2c3_pins_a>; 807 #address-cells = <1>; 808 #size-cells = <0>; 809 status = "disabled"; 810 }; 811 812 i2c4: i2c@11011000 { 813 compatible = "mediatek,mt8173-i2c"; 814 reg = <0 0x11011000 0 0x70>, 815 <0 0x11000300 0 0x80>; 816 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 817 clock-div = <16>; 818 clocks = <&pericfg CLK_PERI_I2C4>, 819 <&pericfg CLK_PERI_AP_DMA>; 820 clock-names = "main", "dma"; 821 pinctrl-names = "default"; 822 pinctrl-0 = <&i2c4_pins_a>; 823 #address-cells = <1>; 824 #size-cells = <0>; 825 status = "disabled"; 826 }; 827 828 hdmiddc0: i2c@11012000 { 829 compatible = "mediatek,mt8173-hdmi-ddc"; 830 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 831 reg = <0 0x11012000 0 0x1C>; 832 clocks = <&pericfg CLK_PERI_I2C5>; 833 clock-names = "ddc-i2c"; 834 }; 835 836 i2c6: i2c@11013000 { 837 compatible = "mediatek,mt8173-i2c"; 838 reg = <0 0x11013000 0 0x70>, 839 <0 0x11000080 0 0x80>; 840 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 841 clock-div = <16>; 842 clocks = <&pericfg CLK_PERI_I2C6>, 843 <&pericfg CLK_PERI_AP_DMA>; 844 clock-names = "main", "dma"; 845 pinctrl-names = "default"; 846 pinctrl-0 = <&i2c6_pins_a>; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 status = "disabled"; 850 }; 851 852 afe: audio-controller@11220000 { 853 compatible = "mediatek,mt8173-afe-pcm"; 854 reg = <0 0x11220000 0 0x1000>; 855 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 856 power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>; 857 clocks = <&infracfg CLK_INFRA_AUDIO>, 858 <&topckgen CLK_TOP_AUDIO_SEL>, 859 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 860 <&topckgen CLK_TOP_APLL1_DIV0>, 861 <&topckgen CLK_TOP_APLL2_DIV0>, 862 <&topckgen CLK_TOP_I2S0_M_SEL>, 863 <&topckgen CLK_TOP_I2S1_M_SEL>, 864 <&topckgen CLK_TOP_I2S2_M_SEL>, 865 <&topckgen CLK_TOP_I2S3_M_SEL>, 866 <&topckgen CLK_TOP_I2S3_B_SEL>; 867 clock-names = "infra_sys_audio_clk", 868 "top_pdn_audio", 869 "top_pdn_aud_intbus", 870 "bck0", 871 "bck1", 872 "i2s0_m", 873 "i2s1_m", 874 "i2s2_m", 875 "i2s3_m", 876 "i2s3_b"; 877 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 878 <&topckgen CLK_TOP_AUD_2_SEL>; 879 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 880 <&topckgen CLK_TOP_APLL2>; 881 }; 882 883 mmc0: mmc@11230000 { 884 compatible = "mediatek,mt8173-mmc"; 885 reg = <0 0x11230000 0 0x1000>; 886 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 887 clocks = <&pericfg CLK_PERI_MSDC30_0>, 888 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 889 clock-names = "source", "hclk"; 890 status = "disabled"; 891 }; 892 893 mmc1: mmc@11240000 { 894 compatible = "mediatek,mt8173-mmc"; 895 reg = <0 0x11240000 0 0x1000>; 896 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 897 clocks = <&pericfg CLK_PERI_MSDC30_1>, 898 <&topckgen CLK_TOP_AXI_SEL>; 899 clock-names = "source", "hclk"; 900 status = "disabled"; 901 }; 902 903 mmc2: mmc@11250000 { 904 compatible = "mediatek,mt8173-mmc"; 905 reg = <0 0x11250000 0 0x1000>; 906 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 907 clocks = <&pericfg CLK_PERI_MSDC30_2>, 908 <&topckgen CLK_TOP_AXI_SEL>; 909 clock-names = "source", "hclk"; 910 status = "disabled"; 911 }; 912 913 mmc3: mmc@11260000 { 914 compatible = "mediatek,mt8173-mmc"; 915 reg = <0 0x11260000 0 0x1000>; 916 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 917 clocks = <&pericfg CLK_PERI_MSDC30_3>, 918 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 919 clock-names = "source", "hclk"; 920 status = "disabled"; 921 }; 922 923 ssusb: usb@11271000 { 924 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; 925 reg = <0 0x11271000 0 0x3000>, 926 <0 0x11280700 0 0x0100>; 927 reg-names = "mac", "ippc"; 928 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 929 phys = <&u2port0 PHY_TYPE_USB2>, 930 <&u3port0 PHY_TYPE_USB3>, 931 <&u2port1 PHY_TYPE_USB2>; 932 power-domains = <&spm MT8173_POWER_DOMAIN_USB>; 933 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 934 clock-names = "sys_ck", "ref_ck"; 935 mediatek,syscon-wakeup = <&pericfg 0x400 1>; 936 #address-cells = <2>; 937 #size-cells = <2>; 938 ranges; 939 status = "disabled"; 940 941 usb_host: usb@11270000 { 942 compatible = "mediatek,mt8173-xhci", 943 "mediatek,mtk-xhci"; 944 reg = <0 0x11270000 0 0x1000>; 945 reg-names = "mac"; 946 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 947 power-domains = <&spm MT8173_POWER_DOMAIN_USB>; 948 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 949 clock-names = "sys_ck", "ref_ck"; 950 status = "disabled"; 951 }; 952 }; 953 954 u3phy: t-phy@11290000 { 955 compatible = "mediatek,mt8173-u3phy"; 956 reg = <0 0x11290000 0 0x800>; 957 #address-cells = <2>; 958 #size-cells = <2>; 959 ranges; 960 status = "okay"; 961 962 u2port0: usb-phy@11290800 { 963 reg = <0 0x11290800 0 0x100>; 964 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 965 clock-names = "ref"; 966 #phy-cells = <1>; 967 status = "okay"; 968 }; 969 970 u3port0: usb-phy@11290900 { 971 reg = <0 0x11290900 0 0x700>; 972 clocks = <&clk26m>; 973 clock-names = "ref"; 974 #phy-cells = <1>; 975 status = "okay"; 976 }; 977 978 u2port1: usb-phy@11291000 { 979 reg = <0 0x11291000 0 0x100>; 980 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 981 clock-names = "ref"; 982 #phy-cells = <1>; 983 status = "okay"; 984 }; 985 }; 986 987 mmsys: syscon@14000000 { 988 compatible = "mediatek,mt8173-mmsys", "syscon"; 989 reg = <0 0x14000000 0 0x1000>; 990 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 991 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 992 assigned-clock-rates = <400000000>; 993 #clock-cells = <1>; 994 #reset-cells = <1>; 995 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 996 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 997 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 998 }; 999 1000 mdp_rdma0: rdma@14001000 { 1001 compatible = "mediatek,mt8173-mdp-rdma", 1002 "mediatek,mt8173-mdp"; 1003 reg = <0 0x14001000 0 0x1000>; 1004 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 1005 <&mmsys CLK_MM_MUTEX_32K>; 1006 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1007 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 1008 mediatek,vpu = <&vpu>; 1009 }; 1010 1011 mdp_rdma1: rdma@14002000 { 1012 compatible = "mediatek,mt8173-mdp-rdma"; 1013 reg = <0 0x14002000 0 0x1000>; 1014 clocks = <&mmsys CLK_MM_MDP_RDMA1>, 1015 <&mmsys CLK_MM_MUTEX_32K>; 1016 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1017 iommus = <&iommu M4U_PORT_MDP_RDMA1>; 1018 }; 1019 1020 mdp_rsz0: rsz@14003000 { 1021 compatible = "mediatek,mt8173-mdp-rsz"; 1022 reg = <0 0x14003000 0 0x1000>; 1023 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 1024 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1025 }; 1026 1027 mdp_rsz1: rsz@14004000 { 1028 compatible = "mediatek,mt8173-mdp-rsz"; 1029 reg = <0 0x14004000 0 0x1000>; 1030 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 1031 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1032 }; 1033 1034 mdp_rsz2: rsz@14005000 { 1035 compatible = "mediatek,mt8173-mdp-rsz"; 1036 reg = <0 0x14005000 0 0x1000>; 1037 clocks = <&mmsys CLK_MM_MDP_RSZ2>; 1038 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1039 }; 1040 1041 mdp_wdma0: wdma@14006000 { 1042 compatible = "mediatek,mt8173-mdp-wdma"; 1043 reg = <0 0x14006000 0 0x1000>; 1044 clocks = <&mmsys CLK_MM_MDP_WDMA>; 1045 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1046 iommus = <&iommu M4U_PORT_MDP_WDMA>; 1047 }; 1048 1049 mdp_wrot0: wrot@14007000 { 1050 compatible = "mediatek,mt8173-mdp-wrot"; 1051 reg = <0 0x14007000 0 0x1000>; 1052 clocks = <&mmsys CLK_MM_MDP_WROT0>; 1053 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1054 iommus = <&iommu M4U_PORT_MDP_WROT0>; 1055 }; 1056 1057 mdp_wrot1: wrot@14008000 { 1058 compatible = "mediatek,mt8173-mdp-wrot"; 1059 reg = <0 0x14008000 0 0x1000>; 1060 clocks = <&mmsys CLK_MM_MDP_WROT1>; 1061 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1062 iommus = <&iommu M4U_PORT_MDP_WROT1>; 1063 }; 1064 1065 ovl0: ovl@1400c000 { 1066 compatible = "mediatek,mt8173-disp-ovl"; 1067 reg = <0 0x1400c000 0 0x1000>; 1068 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 1069 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1070 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1071 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1072 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1073 }; 1074 1075 ovl1: ovl@1400d000 { 1076 compatible = "mediatek,mt8173-disp-ovl"; 1077 reg = <0 0x1400d000 0 0x1000>; 1078 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 1079 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1080 clocks = <&mmsys CLK_MM_DISP_OVL1>; 1081 iommus = <&iommu M4U_PORT_DISP_OVL1>; 1082 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1083 }; 1084 1085 rdma0: rdma@1400e000 { 1086 compatible = "mediatek,mt8173-disp-rdma"; 1087 reg = <0 0x1400e000 0 0x1000>; 1088 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 1089 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1090 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1091 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1092 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1093 }; 1094 1095 rdma1: rdma@1400f000 { 1096 compatible = "mediatek,mt8173-disp-rdma"; 1097 reg = <0 0x1400f000 0 0x1000>; 1098 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 1099 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1100 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1101 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1102 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1103 }; 1104 1105 rdma2: rdma@14010000 { 1106 compatible = "mediatek,mt8173-disp-rdma"; 1107 reg = <0 0x14010000 0 0x1000>; 1108 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 1109 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1110 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 1111 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 1112 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1113 }; 1114 1115 wdma0: wdma@14011000 { 1116 compatible = "mediatek,mt8173-disp-wdma"; 1117 reg = <0 0x14011000 0 0x1000>; 1118 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 1119 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1120 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 1121 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 1122 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1123 }; 1124 1125 wdma1: wdma@14012000 { 1126 compatible = "mediatek,mt8173-disp-wdma"; 1127 reg = <0 0x14012000 0 0x1000>; 1128 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 1129 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1130 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 1131 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 1132 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1133 }; 1134 1135 color0: color@14013000 { 1136 compatible = "mediatek,mt8173-disp-color"; 1137 reg = <0 0x14013000 0 0x1000>; 1138 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 1139 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1140 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1141 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; 1142 }; 1143 1144 color1: color@14014000 { 1145 compatible = "mediatek,mt8173-disp-color"; 1146 reg = <0 0x14014000 0 0x1000>; 1147 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 1148 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1149 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 1150 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1151 }; 1152 1153 aal@14015000 { 1154 compatible = "mediatek,mt8173-disp-aal"; 1155 reg = <0 0x14015000 0 0x1000>; 1156 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 1157 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1158 clocks = <&mmsys CLK_MM_DISP_AAL>; 1159 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1160 }; 1161 1162 gamma@14016000 { 1163 compatible = "mediatek,mt8173-disp-gamma"; 1164 reg = <0 0x14016000 0 0x1000>; 1165 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 1166 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1167 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 1168 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 1169 }; 1170 1171 merge@14017000 { 1172 compatible = "mediatek,mt8173-disp-merge"; 1173 reg = <0 0x14017000 0 0x1000>; 1174 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1175 clocks = <&mmsys CLK_MM_DISP_MERGE>; 1176 }; 1177 1178 split0: split@14018000 { 1179 compatible = "mediatek,mt8173-disp-split"; 1180 reg = <0 0x14018000 0 0x1000>; 1181 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1182 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 1183 }; 1184 1185 split1: split@14019000 { 1186 compatible = "mediatek,mt8173-disp-split"; 1187 reg = <0 0x14019000 0 0x1000>; 1188 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1189 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 1190 }; 1191 1192 ufoe@1401a000 { 1193 compatible = "mediatek,mt8173-disp-ufoe"; 1194 reg = <0 0x1401a000 0 0x1000>; 1195 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 1196 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1197 clocks = <&mmsys CLK_MM_DISP_UFOE>; 1198 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; 1199 }; 1200 1201 dsi0: dsi@1401b000 { 1202 compatible = "mediatek,mt8173-dsi"; 1203 reg = <0 0x1401b000 0 0x1000>; 1204 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 1205 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1206 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 1207 <&mmsys CLK_MM_DSI0_DIGITAL>, 1208 <&mipi_tx0>; 1209 clock-names = "engine", "digital", "hs"; 1210 resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; 1211 phys = <&mipi_tx0>; 1212 phy-names = "dphy"; 1213 status = "disabled"; 1214 }; 1215 1216 dsi1: dsi@1401c000 { 1217 compatible = "mediatek,mt8173-dsi"; 1218 reg = <0 0x1401c000 0 0x1000>; 1219 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 1220 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1221 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 1222 <&mmsys CLK_MM_DSI1_DIGITAL>, 1223 <&mipi_tx1>; 1224 clock-names = "engine", "digital", "hs"; 1225 phys = <&mipi_tx1>; 1226 phy-names = "dphy"; 1227 status = "disabled"; 1228 }; 1229 1230 dpi0: dpi@1401d000 { 1231 compatible = "mediatek,mt8173-dpi"; 1232 reg = <0 0x1401d000 0 0x1000>; 1233 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 1234 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1235 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 1236 <&mmsys CLK_MM_DPI_ENGINE>, 1237 <&apmixedsys CLK_APMIXED_TVDPLL>; 1238 clock-names = "pixel", "engine", "pll"; 1239 status = "disabled"; 1240 1241 port { 1242 dpi0_out: endpoint { 1243 remote-endpoint = <&hdmi0_in>; 1244 }; 1245 }; 1246 }; 1247 1248 pwm0: pwm@1401e000 { 1249 compatible = "mediatek,mt8173-disp-pwm", 1250 "mediatek,mt6595-disp-pwm"; 1251 reg = <0 0x1401e000 0 0x1000>; 1252 #pwm-cells = <2>; 1253 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 1254 <&mmsys CLK_MM_DISP_PWM0MM>; 1255 clock-names = "main", "mm"; 1256 status = "disabled"; 1257 }; 1258 1259 pwm1: pwm@1401f000 { 1260 compatible = "mediatek,mt8173-disp-pwm", 1261 "mediatek,mt6595-disp-pwm"; 1262 reg = <0 0x1401f000 0 0x1000>; 1263 #pwm-cells = <2>; 1264 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 1265 <&mmsys CLK_MM_DISP_PWM1MM>; 1266 clock-names = "main", "mm"; 1267 status = "disabled"; 1268 }; 1269 1270 mutex: mutex@14020000 { 1271 compatible = "mediatek,mt8173-disp-mutex"; 1272 reg = <0 0x14020000 0 0x1000>; 1273 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1274 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1275 clocks = <&mmsys CLK_MM_MUTEX_32K>; 1276 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>; 1277 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, 1278 <CMDQ_EVENT_MUTEX1_STREAM_EOF>; 1279 }; 1280 1281 larb0: larb@14021000 { 1282 compatible = "mediatek,mt8173-smi-larb"; 1283 reg = <0 0x14021000 0 0x1000>; 1284 mediatek,smi = <&smi_common>; 1285 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1286 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1287 <&mmsys CLK_MM_SMI_LARB0>; 1288 clock-names = "apb", "smi"; 1289 }; 1290 1291 smi_common: smi@14022000 { 1292 compatible = "mediatek,mt8173-smi-common"; 1293 reg = <0 0x14022000 0 0x1000>; 1294 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1295 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1296 <&mmsys CLK_MM_SMI_COMMON>; 1297 clock-names = "apb", "smi"; 1298 }; 1299 1300 od@14023000 { 1301 compatible = "mediatek,mt8173-disp-od"; 1302 reg = <0 0x14023000 0 0x1000>; 1303 clocks = <&mmsys CLK_MM_DISP_OD>; 1304 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; 1305 }; 1306 1307 hdmi0: hdmi@14025000 { 1308 compatible = "mediatek,mt8173-hdmi"; 1309 reg = <0 0x14025000 0 0x400>; 1310 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1311 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1312 <&mmsys CLK_MM_HDMI_PLLCK>, 1313 <&mmsys CLK_MM_HDMI_AUDIO>, 1314 <&mmsys CLK_MM_HDMI_SPDIF>; 1315 clock-names = "pixel", "pll", "bclk", "spdif"; 1316 pinctrl-names = "default"; 1317 pinctrl-0 = <&hdmi_pin>; 1318 phys = <&hdmi_phy>; 1319 phy-names = "hdmi"; 1320 mediatek,syscon-hdmi = <&mmsys 0x900>; 1321 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1322 assigned-clock-parents = <&hdmi_phy>; 1323 status = "disabled"; 1324 1325 ports { 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 1329 port@0 { 1330 reg = <0>; 1331 1332 hdmi0_in: endpoint { 1333 remote-endpoint = <&dpi0_out>; 1334 }; 1335 }; 1336 }; 1337 }; 1338 1339 larb4: larb@14027000 { 1340 compatible = "mediatek,mt8173-smi-larb"; 1341 reg = <0 0x14027000 0 0x1000>; 1342 mediatek,smi = <&smi_common>; 1343 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1344 clocks = <&mmsys CLK_MM_SMI_LARB4>, 1345 <&mmsys CLK_MM_SMI_LARB4>; 1346 clock-names = "apb", "smi"; 1347 }; 1348 1349 imgsys: clock-controller@15000000 { 1350 compatible = "mediatek,mt8173-imgsys", "syscon"; 1351 reg = <0 0x15000000 0 0x1000>; 1352 #clock-cells = <1>; 1353 }; 1354 1355 larb2: larb@15001000 { 1356 compatible = "mediatek,mt8173-smi-larb"; 1357 reg = <0 0x15001000 0 0x1000>; 1358 mediatek,smi = <&smi_common>; 1359 power-domains = <&spm MT8173_POWER_DOMAIN_ISP>; 1360 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 1361 <&imgsys CLK_IMG_LARB2_SMI>; 1362 clock-names = "apb", "smi"; 1363 }; 1364 1365 vdecsys: clock-controller@16000000 { 1366 compatible = "mediatek,mt8173-vdecsys", "syscon"; 1367 reg = <0 0x16000000 0 0x1000>; 1368 #clock-cells = <1>; 1369 }; 1370 1371 vcodec_dec: vcodec@16000000 { 1372 compatible = "mediatek,mt8173-vcodec-dec"; 1373 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 1374 <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 1375 <0 0x16021000 0 0x800>, /* VDEC_LD */ 1376 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 1377 <0 0x16022000 0 0x1000>, /* VDEC_CM */ 1378 <0 0x16023000 0 0x1000>, /* VDEC_AD */ 1379 <0 0x16024000 0 0x1000>, /* VDEC_AV */ 1380 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 1381 <0 0x16026800 0 0x800>, /* VDEC_HWD */ 1382 <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 1383 <0 0x16027800 0 0x800>, /* VDEC_HWB */ 1384 <0 0x16028400 0 0x400>; /* VDEC_HWG */ 1385 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 1386 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 1387 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 1388 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 1389 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 1390 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 1391 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 1392 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 1393 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 1394 mediatek,vpu = <&vpu>; 1395 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; 1396 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 1397 <&topckgen CLK_TOP_UNIVPLL_D2>, 1398 <&topckgen CLK_TOP_CCI400_SEL>, 1399 <&topckgen CLK_TOP_VDEC_SEL>, 1400 <&topckgen CLK_TOP_VCODECPLL>, 1401 <&apmixedsys CLK_APMIXED_VENCPLL>, 1402 <&topckgen CLK_TOP_VENC_LT_SEL>, 1403 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1404 clock-names = "vcodecpll", 1405 "univpll_d2", 1406 "clk_cci400_sel", 1407 "vdec_sel", 1408 "vdecpll", 1409 "vencpll", 1410 "venc_lt_sel", 1411 "vdec_bus_clk_src"; 1412 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, 1413 <&topckgen CLK_TOP_CCI400_SEL>, 1414 <&topckgen CLK_TOP_VDEC_SEL>, 1415 <&apmixedsys CLK_APMIXED_VCODECPLL>, 1416 <&apmixedsys CLK_APMIXED_VENCPLL>; 1417 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, 1418 <&topckgen CLK_TOP_UNIVPLL_D2>, 1419 <&topckgen CLK_TOP_VCODECPLL>; 1420 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; 1421 }; 1422 1423 larb1: larb@16010000 { 1424 compatible = "mediatek,mt8173-smi-larb"; 1425 reg = <0 0x16010000 0 0x1000>; 1426 mediatek,smi = <&smi_common>; 1427 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; 1428 clocks = <&vdecsys CLK_VDEC_CKEN>, 1429 <&vdecsys CLK_VDEC_LARB_CKEN>; 1430 clock-names = "apb", "smi"; 1431 }; 1432 1433 vencsys: clock-controller@18000000 { 1434 compatible = "mediatek,mt8173-vencsys", "syscon"; 1435 reg = <0 0x18000000 0 0x1000>; 1436 #clock-cells = <1>; 1437 }; 1438 1439 larb3: larb@18001000 { 1440 compatible = "mediatek,mt8173-smi-larb"; 1441 reg = <0 0x18001000 0 0x1000>; 1442 mediatek,smi = <&smi_common>; 1443 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 1444 clocks = <&vencsys CLK_VENC_CKE1>, 1445 <&vencsys CLK_VENC_CKE0>; 1446 clock-names = "apb", "smi"; 1447 }; 1448 1449 vcodec_enc_avc: vcodec@18002000 { 1450 compatible = "mediatek,mt8173-vcodec-enc"; 1451 reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */ 1452 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; 1453 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1454 <&iommu M4U_PORT_VENC_REC>, 1455 <&iommu M4U_PORT_VENC_BSDMA>, 1456 <&iommu M4U_PORT_VENC_SV_COMV>, 1457 <&iommu M4U_PORT_VENC_RD_COMV>, 1458 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1459 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1460 <&iommu M4U_PORT_VENC_REF_LUMA>, 1461 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1462 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1463 <&iommu M4U_PORT_VENC_NBM_WDMA>; 1464 mediatek,vpu = <&vpu>; 1465 clocks = <&topckgen CLK_TOP_VENC_SEL>; 1466 clock-names = "venc_sel"; 1467 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1468 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; 1469 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 1470 }; 1471 1472 jpegdec: jpegdec@18004000 { 1473 compatible = "mediatek,mt8173-jpgdec"; 1474 reg = <0 0x18004000 0 0x1000>; 1475 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>; 1476 clocks = <&vencsys CLK_VENC_CKE0>, 1477 <&vencsys CLK_VENC_CKE3>; 1478 clock-names = "jpgdec-smi", 1479 "jpgdec"; 1480 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 1481 iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, 1482 <&iommu M4U_PORT_JPGDEC_BSDMA>; 1483 }; 1484 1485 vencltsys: clock-controller@19000000 { 1486 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1487 reg = <0 0x19000000 0 0x1000>; 1488 #clock-cells = <1>; 1489 }; 1490 1491 larb5: larb@19001000 { 1492 compatible = "mediatek,mt8173-smi-larb"; 1493 reg = <0 0x19001000 0 0x1000>; 1494 mediatek,smi = <&smi_common>; 1495 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; 1496 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1497 <&vencltsys CLK_VENCLT_CKE0>; 1498 clock-names = "apb", "smi"; 1499 }; 1500 1501 vcodec_enc_vp8: vcodec@19002000 { 1502 compatible = "mediatek,mt8173-vcodec-enc-vp8"; 1503 reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1504 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1505 iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, 1506 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1507 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1508 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1509 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1510 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1511 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1512 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1513 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1514 mediatek,vpu = <&vpu>; 1515 clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; 1516 clock-names = "venc_lt_sel"; 1517 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; 1518 assigned-clock-parents = 1519 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1520 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; 1521 }; 1522 }; 1523}; 1524
