1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2023 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/leds/common.h>
8#include <dt-bindings/phy/phy-imx8-pcie.h>
9
10/ {
11	led-controller {
12		compatible = "gpio-leds";
13		pinctrl-names = "default";
14		pinctrl-0 = <&pinctrl_gpio_leds>;
15
16		led-0 {
17			function = LED_FUNCTION_STATUS;
18			color = <LED_COLOR_ID_GREEN>;
19			gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
20			default-state = "on";
21			linux,default-trigger = "heartbeat";
22		};
23
24		led-1 {
25			function = LED_FUNCTION_STATUS;
26			color = <LED_COLOR_ID_RED>;
27			gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
28			default-state = "off";
29		};
30	};
31
32	pcie0_refclk: pcie0-refclk {
33		compatible = "fixed-clock";
34		#clock-cells = <0>;
35		clock-frequency = <100000000>;
36	};
37
38	pps {
39		compatible = "pps-gpio";
40		pinctrl-names = "default";
41		pinctrl-0 = <&pinctrl_pps>;
42		gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
43		status = "okay";
44	};
45
46	reg_usb2_vbus: regulator-usb2-vbus {
47		pinctrl-names = "default";
48		pinctrl-0 = <&pinctrl_reg_usb2_en>;
49		compatible = "regulator-fixed";
50		regulator-name = "usb2_vbus";
51		gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
52		enable-active-high;
53		regulator-min-microvolt = <5000000>;
54		regulator-max-microvolt = <5000000>;
55	};
56
57	reg_usdhc2_vmmc: regulator-usdhc2 {
58		pinctrl-names = "default";
59		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
60		compatible = "regulator-fixed";
61		regulator-name = "SD2_3P3V";
62		regulator-min-microvolt = <3300000>;
63		regulator-max-microvolt = <3300000>;
64		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
65		enable-active-high;
66	};
67};
68
69/* off-board header */
70&ecspi2 {
71	pinctrl-names = "default";
72	pinctrl-0 = <&pinctrl_spi2>;
73	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
74	status = "okay";
75};
76
77&gpio4 {
78	gpio-line-names =
79		"", "", "", "",
80		"", "", "", "",
81		"", "", "", "",
82		"", "gpioa", "", "",
83		"", "", "", "",
84		"", "", "", "",
85		"", "", "", "",
86		"", "", "", "";
87};
88
89&gpio4 {
90	gpio-line-names =
91		"", "gpiod", "", "",
92		"gpiob", "gpioc", "", "",
93		"", "", "", "",
94		"", "", "", "",
95		"", "", "", "",
96		"", "", "", "",
97		"", "", "pci_usb_sel", "",
98		"pci_wdis#", "", "", "";
99};
100
101&i2c2 {
102	clock-frequency = <400000>;
103	pinctrl-names = "default";
104	pinctrl-0 = <&pinctrl_i2c2>;
105	status = "okay";
106
107	eeprom@52 {
108		compatible = "atmel,24c32";
109		reg = <0x52>;
110		pagesize = <32>;
111	};
112};
113
114/* off-board header */
115&i2c3 {
116	clock-frequency = <400000>;
117	pinctrl-names = "default";
118	pinctrl-0 = <&pinctrl_i2c3>;
119	status = "okay";
120};
121
122&pcie_phy {
123	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
124	fsl,clkreq-unsupported;
125	clocks = <&pcie0_refclk>;
126	clock-names = "ref";
127	status = "okay";
128};
129
130&pcie {
131	pinctrl-names = "default";
132	pinctrl-0 = <&pinctrl_pcie0>;
133	reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
134	status = "okay";
135};
136
137/* GPS */
138&uart1 {
139	pinctrl-names = "default";
140	pinctrl-0 = <&pinctrl_uart1>;
141	status = "okay";
142};
143
144/* USB1 - Type C front panel SINK port J14 */
145&usb3_0 {
146	status = "okay";
147};
148
149&usb3_phy0 {
150	status = "okay";
151};
152
153&usb_dwc3_0 {
154	dr_mode = "peripheral";
155	status = "okay";
156};
157
158/* USB2 4-port USB3.0 HUB:
159 *  P1 - USBC connector (host only)
160 *  P2 - USB2 test connector
161 *  P3 - miniPCIe full card
162 *  P4 - miniPCIe half card
163 */
164&usb3_phy1 {
165	vbus-supply = <&reg_usb2_vbus>;
166	status = "okay";
167};
168
169&usb3_1 {
170	fsl,permanently-attached;
171	fsl,disable-port-power-control;
172	status = "okay";
173};
174
175&usb_dwc3_1 {
176	dr_mode = "host";
177	status = "okay";
178};
179
180/* microSD */
181&usdhc2 {
182	pinctrl-names = "default", "state_100mhz", "state_200mhz";
183	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
184	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
185	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
186	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
187	vmmc-supply = <&reg_usdhc2_vmmc>;
188	bus-width = <4>;
189	status = "okay";
190};
191
192&iomuxc {
193	pinctrl-names = "default";
194	pinctrl-0 = <&pinctrl_hog>;
195
196	pinctrl_hog: hoggrp {
197		fsl,pins = <
198			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13	0x40000040 /* GPIOA */
199			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01	0x40000040 /* GPIOD */
200			MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04	0x40000040 /* GPIOB */
201			MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05	0x40000040 /* GPIOC */
202			MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26	0x40000106 /* PCI_USBSEL */
203			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x40000106 /* PCI_WDIS# */
204		>;
205	};
206
207	pinctrl_gpio_leds: gpioledgrp {
208		fsl,pins = <
209			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22	0x6	/* LEDG */
210			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27	0x6	/* LEDR */
211		>;
212	};
213
214	pinctrl_i2c2: i2c2grp {
215		fsl,pins = <
216			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
217			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2
218		>;
219	};
220
221	pinctrl_i2c3: i2c3grp {
222		fsl,pins = <
223			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2
224			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2
225		>;
226	};
227
228	pinctrl_pcie0: pciegrp {
229		fsl,pins = <
230			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x106
231		>;
232	};
233
234	pinctrl_pps: ppsgrp {
235		fsl,pins = <
236			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21	0x106
237		>;
238	};
239
240	pinctrl_reg_usb2_en: regusb2grp {
241		fsl,pins = <
242			MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12	0x6 /* USBHUB_RST# (ext p/u) */
243		>;
244	};
245
246	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
247		fsl,pins = <
248			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
249		>;
250	};
251
252	pinctrl_spi2: spi2grp {
253		fsl,pins = <
254			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x140
255			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x140
256			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x140
257			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13	0x140
258		>;
259	};
260
261	pinctrl_uart1: uart1grp {
262		fsl,pins = <
263			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
264			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
265		>;
266	};
267
268	pinctrl_usdhc2: usdhc2grp {
269		fsl,pins = <
270			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
271			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
272			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
273			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
274			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
275			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
276			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc0
277		>;
278	};
279
280	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
281		fsl,pins = <
282			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
283			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
284			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
285			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
286			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
287			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
288			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc0
289		>;
290	};
291
292	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
293		fsl,pins = <
294			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
295			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
296			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
297			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
298			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
299			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
300			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc0
301		>;
302	};
303
304	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
305		fsl,pins = <
306			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c4
307		>;
308	};
309};
310