1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Device Tree Source for OMAP3 SoC
4 *
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#include <dt-bindings/bus/ti-sysc.h>
9#include <dt-bindings/media/omap3-isp.h>
10
11#include "omap3.dtsi"
12
13/ {
14	aliases {
15		serial3 = &uart4;
16	};
17
18	cpus {
19		/* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */
20		cpu: cpu@0 {
21			operating-points-v2 = <&cpu0_opp_table>;
22
23			vbb-supply = <&abb_mpu_iva>;
24			clock-latency = <300000>; /* From omap-cpufreq driver */
25			#cooling-cells = <2>;
26		};
27	};
28
29	cpu0_opp_table: opp-table {
30		compatible = "operating-points-v2-ti-cpu";
31		syscon = <&scm_conf>;
32
33		opp-50-300000000 {
34			/* OPP50 */
35			opp-hz = /bits/ 64 <300000000>;
36			/*
37			 * we currently only select the max voltage from table
38			 * Table 4-19 of the DM3730 Data sheet (SPRS685B)
39			 * Format is:	cpu0-supply:	<target min max>
40			 *		vbb-supply:	<target min max>
41			 */
42			opp-microvolt = <1012500 1012500 1012500>,
43					 <1012500 1012500 1012500>;
44			/*
45			 * first value is silicon revision bit mask
46			 * second one is "speed binned" bit mask
47			 */
48			opp-supported-hw = <0xffffffff 3>;
49			opp-suspend;
50		};
51
52		opp-100-600000000 {
53			/* OPP100 */
54			opp-hz = /bits/ 64 <600000000>;
55			opp-microvolt = <1200000 1200000 1200000>,
56					 <1200000 1200000 1200000>;
57			opp-supported-hw = <0xffffffff 3>;
58		};
59
60		opp-130-800000000 {
61			/* OPP130 */
62			opp-hz = /bits/ 64 <800000000>;
63			opp-microvolt = <1325000 1325000 1325000>,
64					 <1325000 1325000 1325000>;
65			opp-supported-hw = <0xffffffff 3>;
66		};
67
68		opp-1000000000 {
69			/* OPP1G */
70			opp-hz = /bits/ 64 <1000000000>;
71			opp-microvolt = <1375000 1375000 1375000>,
72					 <1375000 1375000 1375000>;
73			/* only on am/dm37x with speed-binned bit set */
74			opp-supported-hw = <0xffffffff 2>;
75		};
76	};
77
78	opp_supply_mpu_iva: opp-supply {
79		compatible = "ti,omap-opp-supply";
80		ti,absolute-max-voltage-uv = <1375000>;
81	};
82
83	ocp@68000000 {
84		uart4: serial@49042000 {
85			compatible = "ti,omap3-uart";
86			reg = <0x49042000 0x400>;
87			interrupts = <80>;
88			dmas = <&sdma 81 &sdma 82>;
89			dma-names = "tx", "rx";
90			ti,hwmods = "uart4";
91			clock-frequency = <48000000>;
92		};
93
94		abb_mpu_iva: regulator-abb-mpu {
95			compatible = "ti,abb-v1";
96			regulator-name = "abb_mpu_iva";
97			#address-cells = <0>;
98			#size-cells = <0>;
99			reg = <0x483072f0 0x8>, <0x48306818 0x4>;
100			reg-names = "base-address", "int-address";
101			ti,tranxdone-status-mask = <0x4000000>;
102			clocks = <&sys_ck>;
103			ti,settling-time = <30>;
104			ti,clock-cycles = <8>;
105			ti,abb_info = <
106			/*uV		ABB	efuse	rbb_m	fbb_m	vset_m*/
107			1012500		0	0	0	0	0
108			1200000		0	0	0	0	0
109			1325000		0	0	0	0	0
110			1375000		1	0	0	0	0
111			>;
112		};
113
114		omap3_pmx_core2: pinmux@480025a0 {
115			compatible = "ti,omap3-padconf", "pinctrl-single";
116			reg = <0x480025a0 0x5c>;
117			#address-cells = <1>;
118			#size-cells = <0>;
119			#pinctrl-cells = <1>;
120			#interrupt-cells = <1>;
121			interrupt-controller;
122			pinctrl-single,register-width = <16>;
123			pinctrl-single,function-mask = <0xff1f>;
124		};
125
126		isp: isp@480bc000 {
127			compatible = "ti,omap3-isp";
128			reg = <0x480bc000 0x12fc
129			       0x480bd800 0x0600>;
130			interrupts = <24>;
131			iommus = <&mmu_isp>;
132			syscon = <&scm_conf 0x2f0>;
133			ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
134			#clock-cells = <1>;
135			ports {
136				#address-cells = <1>;
137				#size-cells = <0>;
138			};
139		};
140
141		bandgap: bandgap@48002524 {
142			reg = <0x48002524 0x4>;
143			compatible = "ti,omap36xx-bandgap";
144			#thermal-sensor-cells = <0>;
145		};
146
147		target-module@480cb000 {
148			compatible = "ti,sysc-omap3630-sr", "ti,sysc";
149			ti,hwmods = "smartreflex_core";
150			reg = <0x480cb038 0x4>;
151			reg-names = "sysc";
152			ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
153			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
154					<SYSC_IDLE_NO>,
155					<SYSC_IDLE_SMART>;
156			clocks = <&sr2_fck>;
157			clock-names = "fck";
158			#address-cells = <1>;
159			#size-cells = <1>;
160			ranges = <0 0x480cb000 0x001000>;
161
162			smartreflex_core: smartreflex@0 {
163				compatible = "ti,omap3-smartreflex-core";
164				reg = <0 0x400>;
165				interrupts = <19>;
166			};
167		};
168
169		target-module@480c9000 {
170			compatible = "ti,sysc-omap3630-sr", "ti,sysc";
171			ti,hwmods = "smartreflex_mpu_iva";
172			reg = <0x480c9038 0x4>;
173			reg-names = "sysc";
174			ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
175			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
176					<SYSC_IDLE_NO>,
177					<SYSC_IDLE_SMART>;
178			clocks = <&sr1_fck>;
179			clock-names = "fck";
180			#address-cells = <1>;
181			#size-cells = <1>;
182			ranges = <0 0x480c9000 0x001000>;
183
184
185			smartreflex_mpu_iva: smartreflex@480c9000 {
186				compatible = "ti,omap3-smartreflex-mpu-iva";
187				reg = <0 0x400>;
188				interrupts = <18>;
189			};
190		};
191
192		/*
193		 * Note that the sysconfig register layout is a subset of the
194		 * "ti,sysc-omap4" type register with just sidle and midle bits
195		 * available while omap34xx has "ti,sysc-omap2" type sysconfig.
196		 */
197		sgx_module: target-module@50000000 {
198			compatible = "ti,sysc-omap4", "ti,sysc";
199			reg = <0x5000fe00 0x4>,
200			      <0x5000fe10 0x4>;
201			reg-names = "rev", "sysc";
202			ti,sysc-midle = <SYSC_IDLE_FORCE>,
203					<SYSC_IDLE_NO>,
204					<SYSC_IDLE_SMART>;
205			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
206					<SYSC_IDLE_NO>,
207					<SYSC_IDLE_SMART>;
208			clocks = <&sgx_fck>, <&sgx_ick>;
209			clock-names = "fck", "ick";
210			#address-cells = <1>;
211			#size-cells = <1>;
212			ranges = <0 0x50000000 0x2000000>;
213
214			/*
215			 * Closed source PowerVR driver, no child device
216			 * binding or driver in mainline
217			 */
218		};
219	};
220
221	thermal_zones: thermal-zones {
222		#include "omap3-cpu-thermal.dtsi"
223	};
224};
225
226&sdma {
227	compatible = "ti,omap3630-sdma", "ti,omap-sdma";
228};
229
230/* OMAP3630 needs dss_96m_fck for VENC */
231&venc {
232	clocks = <&dss_tv_fck>, <&dss_96m_fck>;
233	clock-names = "fck", "tv_dac_clk";
234};
235
236&ssi {
237	status = "okay";
238
239	clocks = <&ssi_ssr_fck>,
240		 <&ssi_sst_fck>,
241		 <&ssi_ick>;
242	clock-names = "ssi_ssr_fck",
243		      "ssi_sst_fck",
244		      "ssi_ick";
245};
246
247&usb_otg_target {
248	clocks = <&hsotgusb_ick_3430es2>;
249};
250
251/include/ "omap34xx-omap36xx-clocks.dtsi"
252/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
253/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
254/include/ "omap36xx-clocks.dtsi"
255