1[
2    {
3        "BriefDescription": "Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
4        "CounterType": "PGMABLE",
5        "EventCode": "0x80",
6        "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
7        "PerPkg": "1",
8        "PublicDescription": "UNC_ARB_TRK_OCCUPANCY.ALL",
9        "UMask": "0x01",
10        "Unit": "ARB"
11    },
12    {
13        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
14        "Counter": "1",
15        "CounterType": "FREERUN",
16        "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
17        "PerPkg": "1",
18        "PublicDescription": "UNC_MC0_RDCAS_COUNT_FREERUN",
19        "Unit": "h_imc"
20    },
21    {
22        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
23        "CounterType": "FREERUN",
24        "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
25        "PerPkg": "1",
26        "PublicDescription": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
27        "Unit": "h_imc"
28    },
29    {
30        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
31        "Counter": "2",
32        "CounterType": "FREERUN",
33        "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
34        "PerPkg": "1",
35        "PublicDescription": "UNC_MC0_WRCAS_COUNT_FREERUN",
36        "Unit": "h_imc"
37    },
38    {
39        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
40        "Counter": "4",
41        "CounterType": "FREERUN",
42        "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
43        "PerPkg": "1",
44        "PublicDescription": "UNC_MC1_RDCAS_COUNT_FREERUN",
45        "Unit": "h_imc"
46    },
47    {
48        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
49        "Counter": "3",
50        "CounterType": "FREERUN",
51        "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
52        "PerPkg": "1",
53        "PublicDescription": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
54        "Unit": "h_imc"
55    },
56    {
57        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
58        "Counter": "5",
59        "CounterType": "FREERUN",
60        "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
61        "PerPkg": "1",
62        "PublicDescription": "UNC_MC1_WRCAS_COUNT_FREERUN",
63        "Unit": "h_imc"
64    }
65]
66