1[ 2 { 3 "BriefDescription": "DRAM Page Activate commands sent due to a write request", 4 "Counter": "0,1,2,3", 5 "EventCode": "0x1", 6 "EventName": "UNC_M_ACT_COUNT.WR", 7 "PerPkg": "1", 8 "UMask": "0x2", 9 "Unit": "iMC" 10 }, 11 { 12 "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)", 13 "Counter": "0,1,2,3", 14 "EventCode": "0x4", 15 "EventName": "UNC_M_CAS_COUNT.RD_REG", 16 "PerPkg": "1", 17 "UMask": "0x1", 18 "Unit": "iMC" 19 }, 20 { 21 "BriefDescription": "DRAM Underfill Read CAS Commands issued", 22 "Counter": "0,1,2,3", 23 "EventCode": "0x4", 24 "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", 25 "PerPkg": "1", 26 "UMask": "0x2", 27 "Unit": "iMC" 28 }, 29 { 30 "BriefDescription": "All DRAM Read CAS Commands issued (including underfills)", 31 "Counter": "0,1,2,3", 32 "EventCode": "0x4", 33 "EventName": "UNC_M_CAS_COUNT.RD", 34 "PerPkg": "1", 35 "UMask": "0x3", 36 "Unit": "iMC" 37 }, 38 { 39 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd", 40 "Counter": "0,1,2,3", 41 "EventCode": "0x4", 42 "EventName": "LLC_MISSES.MEM_READ", 43 "PerPkg": "1", 44 "ScaleUnit": "64Bytes", 45 "UMask": "0x3", 46 "Unit": "iMC" 47 }, 48 { 49 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", 50 "Counter": "0,1,2,3", 51 "EventCode": "0x4", 52 "EventName": "UNC_M_CAS_COUNT.WR_WMM", 53 "PerPkg": "1", 54 "UMask": "0x4", 55 "Unit": "iMC" 56 }, 57 { 58 "BriefDescription": "All DRAM Write CAS commands issued", 59 "Counter": "0,1,2,3", 60 "EventCode": "0x4", 61 "EventName": "UNC_M_CAS_COUNT.WR", 62 "PerPkg": "1", 63 "UMask": "0xC", 64 "Unit": "iMC" 65 }, 66 { 67 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr", 68 "Counter": "0,1,2,3", 69 "EventCode": "0x4", 70 "EventName": "LLC_MISSES.MEM_WRITE", 71 "PerPkg": "1", 72 "ScaleUnit": "64Bytes", 73 "UMask": "0xC", 74 "Unit": "iMC" 75 }, 76 { 77 "BriefDescription": "All DRAM CAS Commands issued", 78 "Counter": "0,1,2,3", 79 "EventCode": "0x4", 80 "EventName": "UNC_M_CAS_COUNT.ALL", 81 "PerPkg": "1", 82 "UMask": "0xF", 83 "Unit": "iMC" 84 }, 85 { 86 "BriefDescription": "Memory controller clock ticks", 87 "Counter": "0,1,2,3", 88 "EventName": "UNC_M_CLOCKTICKS", 89 "PerPkg": "1", 90 "Unit": "iMC" 91 }, 92 { 93 "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode", 94 "Counter": "0,1,2,3", 95 "EventCode": "0x85", 96 "EventName": "UNC_M_POWER_CHANNEL_PPD", 97 "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.", 98 "MetricName": "power_channel_ppd %", 99 "PerPkg": "1", 100 "Unit": "iMC" 101 }, 102 { 103 "BriefDescription": "Cycles Memory is in self refresh power mode", 104 "Counter": "0,1,2,3", 105 "EventCode": "0x43", 106 "EventName": "UNC_M_POWER_SELF_REFRESH", 107 "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.", 108 "MetricName": "power_self_refresh %", 109 "PerPkg": "1", 110 "Unit": "iMC" 111 }, 112 { 113 "BriefDescription": "Pre-charges due to page misses", 114 "Counter": "0,1,2,3", 115 "EventCode": "0x2", 116 "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", 117 "PerPkg": "1", 118 "UMask": "0x1", 119 "Unit": "iMC" 120 }, 121 { 122 "BriefDescription": "Pre-charge for reads", 123 "Counter": "0,1,2,3", 124 "EventCode": "0x2", 125 "EventName": "UNC_M_PRE_COUNT.RD", 126 "PerPkg": "1", 127 "UMask": "0x4", 128 "Unit": "iMC" 129 }, 130 { 131 "BriefDescription": "Read Pending Queue Allocations", 132 "Counter": "0,1,2,3", 133 "EventCode": "0x10", 134 "EventName": "UNC_M_RPQ_INSERTS", 135 "PerPkg": "1", 136 "Unit": "iMC" 137 }, 138 { 139 "BriefDescription": "Read Pending Queue Occupancy", 140 "Counter": "0,1,2,3", 141 "EventCode": "0x80", 142 "EventName": "UNC_M_RPQ_OCCUPANCY", 143 "PerPkg": "1", 144 "Unit": "iMC" 145 }, 146 { 147 "BriefDescription": "Write Pending Queue Allocations", 148 "Counter": "0,1,2,3", 149 "EventCode": "0x20", 150 "EventName": "UNC_M_WPQ_INSERTS", 151 "PerPkg": "1", 152 "Unit": "iMC" 153 }, 154 { 155 "BriefDescription": "Write Pending Queue Occupancy", 156 "Counter": "0,1,2,3", 157 "EventCode": "0x81", 158 "EventName": "UNC_M_WPQ_OCCUPANCY", 159 "PerPkg": "1", 160 "Unit": "iMC" 161 }, 162 { 163 "BriefDescription": "DRAM Activate Count; Activate due to Read", 164 "Counter": "0,1,2,3", 165 "EventCode": "0x1", 166 "EventName": "UNC_M_ACT_COUNT.RD", 167 "PerPkg": "1", 168 "UMask": "0x1", 169 "Unit": "iMC" 170 }, 171 { 172 "BriefDescription": "DRAM Activate Count; Activate due to Bypass", 173 "Counter": "0,1,2,3", 174 "EventCode": "0x1", 175 "EventName": "UNC_M_ACT_COUNT.BYP", 176 "PerPkg": "1", 177 "UMask": "0x8", 178 "Unit": "iMC" 179 }, 180 { 181 "BriefDescription": "ACT command issued by 2 cycle bypass", 182 "Counter": "0,1,2,3", 183 "EventCode": "0xA1", 184 "EventName": "UNC_M_BYP_CMDS.ACT", 185 "PerPkg": "1", 186 "UMask": "0x1", 187 "Unit": "iMC" 188 }, 189 { 190 "BriefDescription": "CAS command issued by 2 cycle bypass", 191 "Counter": "0,1,2,3", 192 "EventCode": "0xA1", 193 "EventName": "UNC_M_BYP_CMDS.CAS", 194 "PerPkg": "1", 195 "UMask": "0x2", 196 "Unit": "iMC" 197 }, 198 { 199 "BriefDescription": "PRE command issued by 2 cycle bypass", 200 "Counter": "0,1,2,3", 201 "EventCode": "0xA1", 202 "EventName": "UNC_M_BYP_CMDS.PRE", 203 "PerPkg": "1", 204 "UMask": "0x4", 205 "Unit": "iMC" 206 }, 207 { 208 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode", 209 "Counter": "0,1,2,3", 210 "EventCode": "0x4", 211 "EventName": "UNC_M_CAS_COUNT.WR_RMM", 212 "PerPkg": "1", 213 "UMask": "0x8", 214 "Unit": "iMC" 215 }, 216 { 217 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM", 218 "Counter": "0,1,2,3", 219 "EventCode": "0x4", 220 "EventName": "UNC_M_CAS_COUNT.RD_WMM", 221 "PerPkg": "1", 222 "UMask": "0x10", 223 "Unit": "iMC" 224 }, 225 { 226 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM", 227 "Counter": "0,1,2,3", 228 "EventCode": "0x4", 229 "EventName": "UNC_M_CAS_COUNT.RD_RMM", 230 "PerPkg": "1", 231 "UMask": "0x20", 232 "Unit": "iMC" 233 }, 234 { 235 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode", 236 "Counter": "0,1,2,3", 237 "EventCode": "0x4", 238 "EventName": "UNC_M_CAS_COUNT.RD_ISOCH", 239 "PerPkg": "1", 240 "UMask": "0x40", 241 "Unit": "iMC" 242 }, 243 { 244 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode", 245 "Counter": "0,1,2,3", 246 "EventCode": "0x4", 247 "EventName": "UNC_M_CAS_COUNT.WR_ISOCH", 248 "PerPkg": "1", 249 "UMask": "0x80", 250 "Unit": "iMC" 251 }, 252 { 253 "BriefDescription": "DRAM Precharge All Commands", 254 "Counter": "0,1,2,3", 255 "EventCode": "0x6", 256 "EventName": "UNC_M_DRAM_PRE_ALL", 257 "PerPkg": "1", 258 "Unit": "iMC" 259 }, 260 { 261 "BriefDescription": "Number of DRAM Refreshes Issued", 262 "Counter": "0,1,2,3", 263 "EventCode": "0x5", 264 "EventName": "UNC_M_DRAM_REFRESH.PANIC", 265 "PerPkg": "1", 266 "UMask": "0x2", 267 "Unit": "iMC" 268 }, 269 { 270 "BriefDescription": "Number of DRAM Refreshes Issued", 271 "Counter": "0,1,2,3", 272 "EventCode": "0x5", 273 "EventName": "UNC_M_DRAM_REFRESH.HIGH", 274 "PerPkg": "1", 275 "UMask": "0x4", 276 "Unit": "iMC" 277 }, 278 { 279 "BriefDescription": "ECC Correctable Errors", 280 "Counter": "0,1,2,3", 281 "EventCode": "0x9", 282 "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", 283 "PerPkg": "1", 284 "Unit": "iMC" 285 }, 286 { 287 "BriefDescription": "Cycles in a Major Mode; Read Major Mode", 288 "Counter": "0,1,2,3", 289 "EventCode": "0x7", 290 "EventName": "UNC_M_MAJOR_MODES.READ", 291 "PerPkg": "1", 292 "UMask": "0x1", 293 "Unit": "iMC" 294 }, 295 { 296 "BriefDescription": "Cycles in a Major Mode; Write Major Mode", 297 "Counter": "0,1,2,3", 298 "EventCode": "0x7", 299 "EventName": "UNC_M_MAJOR_MODES.WRITE", 300 "PerPkg": "1", 301 "UMask": "0x2", 302 "Unit": "iMC" 303 }, 304 { 305 "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", 306 "Counter": "0,1,2,3", 307 "EventCode": "0x7", 308 "EventName": "UNC_M_MAJOR_MODES.PARTIAL", 309 "PerPkg": "1", 310 "UMask": "0x4", 311 "Unit": "iMC" 312 }, 313 { 314 "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", 315 "Counter": "0,1,2,3", 316 "EventCode": "0x7", 317 "EventName": "UNC_M_MAJOR_MODES.ISOCH", 318 "PerPkg": "1", 319 "UMask": "0x8", 320 "Unit": "iMC" 321 }, 322 { 323 "BriefDescription": "Channel DLLOFF Cycles", 324 "Counter": "0,1,2,3", 325 "EventCode": "0x84", 326 "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", 327 "PerPkg": "1", 328 "Unit": "iMC" 329 }, 330 { 331 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 332 "Counter": "0,1,2,3", 333 "EventCode": "0x83", 334 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", 335 "PerPkg": "1", 336 "UMask": "0x1", 337 "Unit": "iMC" 338 }, 339 { 340 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 341 "Counter": "0,1,2,3", 342 "EventCode": "0x83", 343 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", 344 "PerPkg": "1", 345 "UMask": "0x2", 346 "Unit": "iMC" 347 }, 348 { 349 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 350 "Counter": "0,1,2,3", 351 "EventCode": "0x83", 352 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", 353 "PerPkg": "1", 354 "UMask": "0x4", 355 "Unit": "iMC" 356 }, 357 { 358 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 359 "Counter": "0,1,2,3", 360 "EventCode": "0x83", 361 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", 362 "PerPkg": "1", 363 "UMask": "0x8", 364 "Unit": "iMC" 365 }, 366 { 367 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 368 "Counter": "0,1,2,3", 369 "EventCode": "0x83", 370 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", 371 "PerPkg": "1", 372 "UMask": "0x10", 373 "Unit": "iMC" 374 }, 375 { 376 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 377 "Counter": "0,1,2,3", 378 "EventCode": "0x83", 379 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", 380 "PerPkg": "1", 381 "UMask": "0x20", 382 "Unit": "iMC" 383 }, 384 { 385 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 386 "Counter": "0,1,2,3", 387 "EventCode": "0x83", 388 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", 389 "PerPkg": "1", 390 "UMask": "0x40", 391 "Unit": "iMC" 392 }, 393 { 394 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 395 "Counter": "0,1,2,3", 396 "EventCode": "0x83", 397 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", 398 "PerPkg": "1", 399 "UMask": "0x80", 400 "Unit": "iMC" 401 }, 402 { 403 "BriefDescription": "Critical Throttle Cycles", 404 "Counter": "0,1,2,3", 405 "EventCode": "0x86", 406 "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", 407 "PerPkg": "1", 408 "Unit": "iMC" 409 }, 410 { 411 "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", 412 "Counter": "0,1,2,3", 413 "EventCode": "0x42", 414 "EventName": "UNC_M_POWER_PCU_THROTTLING", 415 "PerPkg": "1", 416 "Unit": "iMC" 417 }, 418 { 419 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 420 "Counter": "0,1,2,3", 421 "EventCode": "0x41", 422 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", 423 "PerPkg": "1", 424 "UMask": "0x1", 425 "Unit": "iMC" 426 }, 427 { 428 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 429 "Counter": "0,1,2,3", 430 "EventCode": "0x41", 431 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", 432 "PerPkg": "1", 433 "UMask": "0x2", 434 "Unit": "iMC" 435 }, 436 { 437 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 438 "Counter": "0,1,2,3", 439 "EventCode": "0x41", 440 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", 441 "PerPkg": "1", 442 "UMask": "0x4", 443 "Unit": "iMC" 444 }, 445 { 446 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 447 "Counter": "0,1,2,3", 448 "EventCode": "0x41", 449 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", 450 "PerPkg": "1", 451 "UMask": "0x8", 452 "Unit": "iMC" 453 }, 454 { 455 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 456 "Counter": "0,1,2,3", 457 "EventCode": "0x41", 458 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", 459 "PerPkg": "1", 460 "UMask": "0x10", 461 "Unit": "iMC" 462 }, 463 { 464 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 465 "Counter": "0,1,2,3", 466 "EventCode": "0x41", 467 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", 468 "PerPkg": "1", 469 "UMask": "0x20", 470 "Unit": "iMC" 471 }, 472 { 473 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 474 "Counter": "0,1,2,3", 475 "EventCode": "0x41", 476 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", 477 "PerPkg": "1", 478 "UMask": "0x40", 479 "Unit": "iMC" 480 }, 481 { 482 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 483 "Counter": "0,1,2,3", 484 "EventCode": "0x41", 485 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", 486 "PerPkg": "1", 487 "UMask": "0x80", 488 "Unit": "iMC" 489 }, 490 { 491 "BriefDescription": "Read Preemption Count; Read over Read Preemption", 492 "Counter": "0,1,2,3", 493 "EventCode": "0x8", 494 "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", 495 "PerPkg": "1", 496 "UMask": "0x1", 497 "Unit": "iMC" 498 }, 499 { 500 "BriefDescription": "Read Preemption Count; Read over Write Preemption", 501 "Counter": "0,1,2,3", 502 "EventCode": "0x8", 503 "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", 504 "PerPkg": "1", 505 "UMask": "0x2", 506 "Unit": "iMC" 507 }, 508 { 509 "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration", 510 "Counter": "0,1,2,3", 511 "EventCode": "0x2", 512 "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", 513 "PerPkg": "1", 514 "UMask": "0x2", 515 "Unit": "iMC" 516 }, 517 { 518 "BriefDescription": "Pre-charge for writes", 519 "Counter": "0,1,2,3", 520 "EventCode": "0x2", 521 "EventName": "UNC_M_PRE_COUNT.WR", 522 "PerPkg": "1", 523 "UMask": "0x8", 524 "Unit": "iMC" 525 }, 526 { 527 "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass", 528 "Counter": "0,1,2,3", 529 "EventCode": "0x2", 530 "EventName": "UNC_M_PRE_COUNT.BYP", 531 "PerPkg": "1", 532 "UMask": "0x10", 533 "Unit": "iMC" 534 }, 535 { 536 "BriefDescription": "Read CAS issued with LOW priority", 537 "Counter": "0,1,2,3", 538 "EventCode": "0xA0", 539 "EventName": "UNC_M_RD_CAS_PRIO.LOW", 540 "PerPkg": "1", 541 "UMask": "0x1", 542 "Unit": "iMC" 543 }, 544 { 545 "BriefDescription": "Read CAS issued with MEDIUM priority", 546 "Counter": "0,1,2,3", 547 "EventCode": "0xA0", 548 "EventName": "UNC_M_RD_CAS_PRIO.MED", 549 "PerPkg": "1", 550 "UMask": "0x2", 551 "Unit": "iMC" 552 }, 553 { 554 "BriefDescription": "Read CAS issued with HIGH priority", 555 "Counter": "0,1,2,3", 556 "EventCode": "0xA0", 557 "EventName": "UNC_M_RD_CAS_PRIO.HIGH", 558 "PerPkg": "1", 559 "UMask": "0x4", 560 "Unit": "iMC" 561 }, 562 { 563 "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)", 564 "Counter": "0,1,2,3", 565 "EventCode": "0xA0", 566 "EventName": "UNC_M_RD_CAS_PRIO.PANIC", 567 "PerPkg": "1", 568 "UMask": "0x8", 569 "Unit": "iMC" 570 }, 571 { 572 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", 573 "Counter": "0,1,2,3", 574 "EventCode": "0xB0", 575 "EventName": "UNC_M_RD_CAS_RANK0.BANK0", 576 "PerPkg": "1", 577 "Unit": "iMC" 578 }, 579 { 580 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", 581 "Counter": "0,1,2,3", 582 "EventCode": "0xB0", 583 "EventName": "UNC_M_RD_CAS_RANK0.BANK1", 584 "PerPkg": "1", 585 "UMask": "0x1", 586 "Unit": "iMC" 587 }, 588 { 589 "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", 590 "Counter": "0,1,2,3", 591 "EventCode": "0xB0", 592 "EventName": "UNC_M_RD_CAS_RANK0.BANK2", 593 "PerPkg": "1", 594 "UMask": "0x2", 595 "Unit": "iMC" 596 }, 597 { 598 "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", 599 "Counter": "0,1,2,3", 600 "EventCode": "0xB0", 601 "EventName": "UNC_M_RD_CAS_RANK0.BANK3", 602 "PerPkg": "1", 603 "UMask": "0x3", 604 "Unit": "iMC" 605 }, 606 { 607 "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", 608 "Counter": "0,1,2,3", 609 "EventCode": "0xB0", 610 "EventName": "UNC_M_RD_CAS_RANK0.BANK4", 611 "PerPkg": "1", 612 "UMask": "0x4", 613 "Unit": "iMC" 614 }, 615 { 616 "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", 617 "Counter": "0,1,2,3", 618 "EventCode": "0xB0", 619 "EventName": "UNC_M_RD_CAS_RANK0.BANK5", 620 "PerPkg": "1", 621 "UMask": "0x5", 622 "Unit": "iMC" 623 }, 624 { 625 "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", 626 "Counter": "0,1,2,3", 627 "EventCode": "0xB0", 628 "EventName": "UNC_M_RD_CAS_RANK0.BANK6", 629 "PerPkg": "1", 630 "UMask": "0x6", 631 "Unit": "iMC" 632 }, 633 { 634 "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", 635 "Counter": "0,1,2,3", 636 "EventCode": "0xB0", 637 "EventName": "UNC_M_RD_CAS_RANK0.BANK7", 638 "PerPkg": "1", 639 "UMask": "0x7", 640 "Unit": "iMC" 641 }, 642 { 643 "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", 644 "Counter": "0,1,2,3", 645 "EventCode": "0xB0", 646 "EventName": "UNC_M_RD_CAS_RANK0.BANK8", 647 "PerPkg": "1", 648 "UMask": "0x8", 649 "Unit": "iMC" 650 }, 651 { 652 "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", 653 "Counter": "0,1,2,3", 654 "EventCode": "0xB0", 655 "EventName": "UNC_M_RD_CAS_RANK0.BANK9", 656 "PerPkg": "1", 657 "UMask": "0x9", 658 "Unit": "iMC" 659 }, 660 { 661 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", 662 "Counter": "0,1,2,3", 663 "EventCode": "0xB0", 664 "EventName": "UNC_M_RD_CAS_RANK0.BANK10", 665 "PerPkg": "1", 666 "UMask": "0xA", 667 "Unit": "iMC" 668 }, 669 { 670 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", 671 "Counter": "0,1,2,3", 672 "EventCode": "0xB0", 673 "EventName": "UNC_M_RD_CAS_RANK0.BANK11", 674 "PerPkg": "1", 675 "UMask": "0xB", 676 "Unit": "iMC" 677 }, 678 { 679 "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", 680 "Counter": "0,1,2,3", 681 "EventCode": "0xB0", 682 "EventName": "UNC_M_RD_CAS_RANK0.BANK12", 683 "PerPkg": "1", 684 "UMask": "0xC", 685 "Unit": "iMC" 686 }, 687 { 688 "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", 689 "Counter": "0,1,2,3", 690 "EventCode": "0xB0", 691 "EventName": "UNC_M_RD_CAS_RANK0.BANK13", 692 "PerPkg": "1", 693 "UMask": "0xD", 694 "Unit": "iMC" 695 }, 696 { 697 "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", 698 "Counter": "0,1,2,3", 699 "EventCode": "0xB0", 700 "EventName": "UNC_M_RD_CAS_RANK0.BANK14", 701 "PerPkg": "1", 702 "UMask": "0xE", 703 "Unit": "iMC" 704 }, 705 { 706 "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", 707 "Counter": "0,1,2,3", 708 "EventCode": "0xB0", 709 "EventName": "UNC_M_RD_CAS_RANK0.BANK15", 710 "PerPkg": "1", 711 "UMask": "0xF", 712 "Unit": "iMC" 713 }, 714 { 715 "BriefDescription": "RD_CAS Access to Rank 0; All Banks", 716 "Counter": "0,1,2,3", 717 "EventCode": "0xB0", 718 "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", 719 "PerPkg": "1", 720 "UMask": "0x10", 721 "Unit": "iMC" 722 }, 723 { 724 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", 725 "Counter": "0,1,2,3", 726 "EventCode": "0xB0", 727 "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", 728 "PerPkg": "1", 729 "UMask": "0x11", 730 "Unit": "iMC" 731 }, 732 { 733 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", 734 "Counter": "0,1,2,3", 735 "EventCode": "0xB0", 736 "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", 737 "PerPkg": "1", 738 "UMask": "0x12", 739 "Unit": "iMC" 740 }, 741 { 742 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", 743 "Counter": "0,1,2,3", 744 "EventCode": "0xB0", 745 "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", 746 "PerPkg": "1", 747 "UMask": "0x13", 748 "Unit": "iMC" 749 }, 750 { 751 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", 752 "Counter": "0,1,2,3", 753 "EventCode": "0xB0", 754 "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", 755 "PerPkg": "1", 756 "UMask": "0x14", 757 "Unit": "iMC" 758 }, 759 { 760 "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", 761 "Counter": "0,1,2,3", 762 "EventCode": "0xB1", 763 "EventName": "UNC_M_RD_CAS_RANK1.BANK0", 764 "PerPkg": "1", 765 "Unit": "iMC" 766 }, 767 { 768 "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", 769 "Counter": "0,1,2,3", 770 "EventCode": "0xB1", 771 "EventName": "UNC_M_RD_CAS_RANK1.BANK1", 772 "PerPkg": "1", 773 "UMask": "0x1", 774 "Unit": "iMC" 775 }, 776 { 777 "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", 778 "Counter": "0,1,2,3", 779 "EventCode": "0xB1", 780 "EventName": "UNC_M_RD_CAS_RANK1.BANK2", 781 "PerPkg": "1", 782 "UMask": "0x2", 783 "Unit": "iMC" 784 }, 785 { 786 "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", 787 "Counter": "0,1,2,3", 788 "EventCode": "0xB1", 789 "EventName": "UNC_M_RD_CAS_RANK1.BANK3", 790 "PerPkg": "1", 791 "UMask": "0x3", 792 "Unit": "iMC" 793 }, 794 { 795 "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", 796 "Counter": "0,1,2,3", 797 "EventCode": "0xB1", 798 "EventName": "UNC_M_RD_CAS_RANK1.BANK4", 799 "PerPkg": "1", 800 "UMask": "0x4", 801 "Unit": "iMC" 802 }, 803 { 804 "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", 805 "Counter": "0,1,2,3", 806 "EventCode": "0xB1", 807 "EventName": "UNC_M_RD_CAS_RANK1.BANK5", 808 "PerPkg": "1", 809 "UMask": "0x5", 810 "Unit": "iMC" 811 }, 812 { 813 "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", 814 "Counter": "0,1,2,3", 815 "EventCode": "0xB1", 816 "EventName": "UNC_M_RD_CAS_RANK1.BANK6", 817 "PerPkg": "1", 818 "UMask": "0x6", 819 "Unit": "iMC" 820 }, 821 { 822 "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", 823 "Counter": "0,1,2,3", 824 "EventCode": "0xB1", 825 "EventName": "UNC_M_RD_CAS_RANK1.BANK7", 826 "PerPkg": "1", 827 "UMask": "0x7", 828 "Unit": "iMC" 829 }, 830 { 831 "BriefDescription": "RD_CAS Access to Rank 1; Bank 8", 832 "Counter": "0,1,2,3", 833 "EventCode": "0xB1", 834 "EventName": "UNC_M_RD_CAS_RANK1.BANK8", 835 "PerPkg": "1", 836 "UMask": "0x8", 837 "Unit": "iMC" 838 }, 839 { 840 "BriefDescription": "RD_CAS Access to Rank 1; Bank 9", 841 "Counter": "0,1,2,3", 842 "EventCode": "0xB1", 843 "EventName": "UNC_M_RD_CAS_RANK1.BANK9", 844 "PerPkg": "1", 845 "UMask": "0x9", 846 "Unit": "iMC" 847 }, 848 { 849 "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", 850 "Counter": "0,1,2,3", 851 "EventCode": "0xB1", 852 "EventName": "UNC_M_RD_CAS_RANK1.BANK10", 853 "PerPkg": "1", 854 "UMask": "0xA", 855 "Unit": "iMC" 856 }, 857 { 858 "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", 859 "Counter": "0,1,2,3", 860 "EventCode": "0xB1", 861 "EventName": "UNC_M_RD_CAS_RANK1.BANK11", 862 "PerPkg": "1", 863 "UMask": "0xB", 864 "Unit": "iMC" 865 }, 866 { 867 "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", 868 "Counter": "0,1,2,3", 869 "EventCode": "0xB1", 870 "EventName": "UNC_M_RD_CAS_RANK1.BANK12", 871 "PerPkg": "1", 872 "UMask": "0xC", 873 "Unit": "iMC" 874 }, 875 { 876 "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", 877 "Counter": "0,1,2,3", 878 "EventCode": "0xB1", 879 "EventName": "UNC_M_RD_CAS_RANK1.BANK13", 880 "PerPkg": "1", 881 "UMask": "0xD", 882 "Unit": "iMC" 883 }, 884 { 885 "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", 886 "Counter": "0,1,2,3", 887 "EventCode": "0xB1", 888 "EventName": "UNC_M_RD_CAS_RANK1.BANK14", 889 "PerPkg": "1", 890 "UMask": "0xE", 891 "Unit": "iMC" 892 }, 893 { 894 "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", 895 "Counter": "0,1,2,3", 896 "EventCode": "0xB1", 897 "EventName": "UNC_M_RD_CAS_RANK1.BANK15", 898 "PerPkg": "1", 899 "UMask": "0xF", 900 "Unit": "iMC" 901 }, 902 { 903 "BriefDescription": "RD_CAS Access to Rank 1; All Banks", 904 "Counter": "0,1,2,3", 905 "EventCode": "0xB1", 906 "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", 907 "PerPkg": "1", 908 "UMask": "0x10", 909 "Unit": "iMC" 910 }, 911 { 912 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", 913 "Counter": "0,1,2,3", 914 "EventCode": "0xB1", 915 "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", 916 "PerPkg": "1", 917 "UMask": "0x11", 918 "Unit": "iMC" 919 }, 920 { 921 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", 922 "Counter": "0,1,2,3", 923 "EventCode": "0xB1", 924 "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", 925 "PerPkg": "1", 926 "UMask": "0x12", 927 "Unit": "iMC" 928 }, 929 { 930 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)", 931 "Counter": "0,1,2,3", 932 "EventCode": "0xB1", 933 "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", 934 "PerPkg": "1", 935 "UMask": "0x13", 936 "Unit": "iMC" 937 }, 938 { 939 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)", 940 "Counter": "0,1,2,3", 941 "EventCode": "0xB1", 942 "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", 943 "PerPkg": "1", 944 "UMask": "0x14", 945 "Unit": "iMC" 946 }, 947 { 948 "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", 949 "Counter": "0,1,2,3", 950 "EventCode": "0xB2", 951 "EventName": "UNC_M_RD_CAS_RANK2.BANK0", 952 "PerPkg": "1", 953 "Unit": "iMC" 954 }, 955 { 956 "BriefDescription": "RD_CAS Access to Rank 2; Bank 1", 957 "Counter": "0,1,2,3", 958 "EventCode": "0xB2", 959 "EventName": "UNC_M_RD_CAS_RANK2.BANK1", 960 "PerPkg": "1", 961 "UMask": "0x1", 962 "Unit": "iMC" 963 }, 964 { 965 "BriefDescription": "RD_CAS Access to Rank 2; Bank 2", 966 "Counter": "0,1,2,3", 967 "EventCode": "0xB2", 968 "EventName": "UNC_M_RD_CAS_RANK2.BANK2", 969 "PerPkg": "1", 970 "UMask": "0x2", 971 "Unit": "iMC" 972 }, 973 { 974 "BriefDescription": "RD_CAS Access to Rank 2; Bank 3", 975 "Counter": "0,1,2,3", 976 "EventCode": "0xB2", 977 "EventName": "UNC_M_RD_CAS_RANK2.BANK3", 978 "PerPkg": "1", 979 "UMask": "0x3", 980 "Unit": "iMC" 981 }, 982 { 983 "BriefDescription": "RD_CAS Access to Rank 2; Bank 4", 984 "Counter": "0,1,2,3", 985 "EventCode": "0xB2", 986 "EventName": "UNC_M_RD_CAS_RANK2.BANK4", 987 "PerPkg": "1", 988 "UMask": "0x4", 989 "Unit": "iMC" 990 }, 991 { 992 "BriefDescription": "RD_CAS Access to Rank 2; Bank 5", 993 "Counter": "0,1,2,3", 994 "EventCode": "0xB2", 995 "EventName": "UNC_M_RD_CAS_RANK2.BANK5", 996 "PerPkg": "1", 997 "UMask": "0x5", 998 "Unit": "iMC" 999 }, 1000 { 1001 "BriefDescription": "RD_CAS Access to Rank 2; Bank 6", 1002 "Counter": "0,1,2,3", 1003 "EventCode": "0xB2", 1004 "EventName": "UNC_M_RD_CAS_RANK2.BANK6", 1005 "PerPkg": "1", 1006 "UMask": "0x6", 1007 "Unit": "iMC" 1008 }, 1009 { 1010 "BriefDescription": "RD_CAS Access to Rank 2; Bank 7", 1011 "Counter": "0,1,2,3", 1012 "EventCode": "0xB2", 1013 "EventName": "UNC_M_RD_CAS_RANK2.BANK7", 1014 "PerPkg": "1", 1015 "UMask": "0x7", 1016 "Unit": "iMC" 1017 }, 1018 { 1019 "BriefDescription": "RD_CAS Access to Rank 2; Bank 8", 1020 "Counter": "0,1,2,3", 1021 "EventCode": "0xB2", 1022 "EventName": "UNC_M_RD_CAS_RANK2.BANK8", 1023 "PerPkg": "1", 1024 "UMask": "0x8", 1025 "Unit": "iMC" 1026 }, 1027 { 1028 "BriefDescription": "RD_CAS Access to Rank 2; Bank 9", 1029 "Counter": "0,1,2,3", 1030 "EventCode": "0xB2", 1031 "EventName": "UNC_M_RD_CAS_RANK2.BANK9", 1032 "PerPkg": "1", 1033 "UMask": "0x9", 1034 "Unit": "iMC" 1035 }, 1036 { 1037 "BriefDescription": "RD_CAS Access to Rank 2; Bank 10", 1038 "Counter": "0,1,2,3", 1039 "EventCode": "0xB2", 1040 "EventName": "UNC_M_RD_CAS_RANK2.BANK10", 1041 "PerPkg": "1", 1042 "UMask": "0xA", 1043 "Unit": "iMC" 1044 }, 1045 { 1046 "BriefDescription": "RD_CAS Access to Rank 2; Bank 11", 1047 "Counter": "0,1,2,3", 1048 "EventCode": "0xB2", 1049 "EventName": "UNC_M_RD_CAS_RANK2.BANK11", 1050 "PerPkg": "1", 1051 "UMask": "0xB", 1052 "Unit": "iMC" 1053 }, 1054 { 1055 "BriefDescription": "RD_CAS Access to Rank 2; Bank 12", 1056 "Counter": "0,1,2,3", 1057 "EventCode": "0xB2", 1058 "EventName": "UNC_M_RD_CAS_RANK2.BANK12", 1059 "PerPkg": "1", 1060 "UMask": "0xC", 1061 "Unit": "iMC" 1062 }, 1063 { 1064 "BriefDescription": "RD_CAS Access to Rank 2; Bank 13", 1065 "Counter": "0,1,2,3", 1066 "EventCode": "0xB2", 1067 "EventName": "UNC_M_RD_CAS_RANK2.BANK13", 1068 "PerPkg": "1", 1069 "UMask": "0xD", 1070 "Unit": "iMC" 1071 }, 1072 { 1073 "BriefDescription": "RD_CAS Access to Rank 2; Bank 14", 1074 "Counter": "0,1,2,3", 1075 "EventCode": "0xB2", 1076 "EventName": "UNC_M_RD_CAS_RANK2.BANK14", 1077 "PerPkg": "1", 1078 "UMask": "0xE", 1079 "Unit": "iMC" 1080 }, 1081 { 1082 "BriefDescription": "RD_CAS Access to Rank 2; Bank 15", 1083 "Counter": "0,1,2,3", 1084 "EventCode": "0xB2", 1085 "EventName": "UNC_M_RD_CAS_RANK2.BANK15", 1086 "PerPkg": "1", 1087 "UMask": "0xF", 1088 "Unit": "iMC" 1089 }, 1090 { 1091 "BriefDescription": "RD_CAS Access to Rank 2; All Banks", 1092 "Counter": "0,1,2,3", 1093 "EventCode": "0xB2", 1094 "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS", 1095 "PerPkg": "1", 1096 "UMask": "0x10", 1097 "Unit": "iMC" 1098 }, 1099 { 1100 "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 0 (Banks 0-3)", 1101 "Counter": "0,1,2,3", 1102 "EventCode": "0xB2", 1103 "EventName": "UNC_M_RD_CAS_RANK2.BANKG0", 1104 "PerPkg": "1", 1105 "UMask": "0x11", 1106 "Unit": "iMC" 1107 }, 1108 { 1109 "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 1 (Banks 4-7)", 1110 "Counter": "0,1,2,3", 1111 "EventCode": "0xB2", 1112 "EventName": "UNC_M_RD_CAS_RANK2.BANKG1", 1113 "PerPkg": "1", 1114 "UMask": "0x12", 1115 "Unit": "iMC" 1116 }, 1117 { 1118 "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 2 (Banks 8-11)", 1119 "Counter": "0,1,2,3", 1120 "EventCode": "0xB2", 1121 "EventName": "UNC_M_RD_CAS_RANK2.BANKG2", 1122 "PerPkg": "1", 1123 "UMask": "0x13", 1124 "Unit": "iMC" 1125 }, 1126 { 1127 "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 3 (Banks 12-15)", 1128 "Counter": "0,1,2,3", 1129 "EventCode": "0xB2", 1130 "EventName": "UNC_M_RD_CAS_RANK2.BANKG3", 1131 "PerPkg": "1", 1132 "UMask": "0x14", 1133 "Unit": "iMC" 1134 }, 1135 { 1136 "BriefDescription": "RD_CAS Access to Rank 3; Bank 0", 1137 "Counter": "0,1,2,3", 1138 "EventCode": "0xB3", 1139 "EventName": "UNC_M_RD_CAS_RANK3.BANK0", 1140 "PerPkg": "1", 1141 "Unit": "iMC" 1142 }, 1143 { 1144 "BriefDescription": "RD_CAS Access to Rank 3; Bank 1", 1145 "Counter": "0,1,2,3", 1146 "EventCode": "0xB3", 1147 "EventName": "UNC_M_RD_CAS_RANK3.BANK1", 1148 "PerPkg": "1", 1149 "UMask": "0x1", 1150 "Unit": "iMC" 1151 }, 1152 { 1153 "BriefDescription": "RD_CAS Access to Rank 3; Bank 2", 1154 "Counter": "0,1,2,3", 1155 "EventCode": "0xB3", 1156 "EventName": "UNC_M_RD_CAS_RANK3.BANK2", 1157 "PerPkg": "1", 1158 "UMask": "0x2", 1159 "Unit": "iMC" 1160 }, 1161 { 1162 "BriefDescription": "RD_CAS Access to Rank 3; Bank 3", 1163 "Counter": "0,1,2,3", 1164 "EventCode": "0xB3", 1165 "EventName": "UNC_M_RD_CAS_RANK3.BANK3", 1166 "PerPkg": "1", 1167 "UMask": "0x3", 1168 "Unit": "iMC" 1169 }, 1170 { 1171 "BriefDescription": "RD_CAS Access to Rank 3; Bank 4", 1172 "Counter": "0,1,2,3", 1173 "EventCode": "0xB3", 1174 "EventName": "UNC_M_RD_CAS_RANK3.BANK4", 1175 "PerPkg": "1", 1176 "UMask": "0x4", 1177 "Unit": "iMC" 1178 }, 1179 { 1180 "BriefDescription": "RD_CAS Access to Rank 3; Bank 5", 1181 "Counter": "0,1,2,3", 1182 "EventCode": "0xB3", 1183 "EventName": "UNC_M_RD_CAS_RANK3.BANK5", 1184 "PerPkg": "1", 1185 "UMask": "0x5", 1186 "Unit": "iMC" 1187 }, 1188 { 1189 "BriefDescription": "RD_CAS Access to Rank 3; Bank 6", 1190 "Counter": "0,1,2,3", 1191 "EventCode": "0xB3", 1192 "EventName": "UNC_M_RD_CAS_RANK3.BANK6", 1193 "PerPkg": "1", 1194 "UMask": "0x6", 1195 "Unit": "iMC" 1196 }, 1197 { 1198 "BriefDescription": "RD_CAS Access to Rank 3; Bank 7", 1199 "Counter": "0,1,2,3", 1200 "EventCode": "0xB3", 1201 "EventName": "UNC_M_RD_CAS_RANK3.BANK7", 1202 "PerPkg": "1", 1203 "UMask": "0x7", 1204 "Unit": "iMC" 1205 }, 1206 { 1207 "BriefDescription": "RD_CAS Access to Rank 3; Bank 8", 1208 "Counter": "0,1,2,3", 1209 "EventCode": "0xB3", 1210 "EventName": "UNC_M_RD_CAS_RANK3.BANK8", 1211 "PerPkg": "1", 1212 "UMask": "0x8", 1213 "Unit": "iMC" 1214 }, 1215 { 1216 "BriefDescription": "RD_CAS Access to Rank 3; Bank 9", 1217 "Counter": "0,1,2,3", 1218 "EventCode": "0xB3", 1219 "EventName": "UNC_M_RD_CAS_RANK3.BANK9", 1220 "PerPkg": "1", 1221 "UMask": "0x9", 1222 "Unit": "iMC" 1223 }, 1224 { 1225 "BriefDescription": "RD_CAS Access to Rank 3; Bank 10", 1226 "Counter": "0,1,2,3", 1227 "EventCode": "0xB3", 1228 "EventName": "UNC_M_RD_CAS_RANK3.BANK10", 1229 "PerPkg": "1", 1230 "UMask": "0xA", 1231 "Unit": "iMC" 1232 }, 1233 { 1234 "BriefDescription": "RD_CAS Access to Rank 3; Bank 11", 1235 "Counter": "0,1,2,3", 1236 "EventCode": "0xB3", 1237 "EventName": "UNC_M_RD_CAS_RANK3.BANK11", 1238 "PerPkg": "1", 1239 "UMask": "0xB", 1240 "Unit": "iMC" 1241 }, 1242 { 1243 "BriefDescription": "RD_CAS Access to Rank 3; Bank 12", 1244 "Counter": "0,1,2,3", 1245 "EventCode": "0xB3", 1246 "EventName": "UNC_M_RD_CAS_RANK3.BANK12", 1247 "PerPkg": "1", 1248 "UMask": "0xC", 1249 "Unit": "iMC" 1250 }, 1251 { 1252 "BriefDescription": "RD_CAS Access to Rank 3; Bank 13", 1253 "Counter": "0,1,2,3", 1254 "EventCode": "0xB3", 1255 "EventName": "UNC_M_RD_CAS_RANK3.BANK13", 1256 "PerPkg": "1", 1257 "UMask": "0xD", 1258 "Unit": "iMC" 1259 }, 1260 { 1261 "BriefDescription": "RD_CAS Access to Rank 3; Bank 14", 1262 "Counter": "0,1,2,3", 1263 "EventCode": "0xB3", 1264 "EventName": "UNC_M_RD_CAS_RANK3.BANK14", 1265 "PerPkg": "1", 1266 "UMask": "0xE", 1267 "Unit": "iMC" 1268 }, 1269 { 1270 "BriefDescription": "RD_CAS Access to Rank 3; Bank 15", 1271 "Counter": "0,1,2,3", 1272 "EventCode": "0xB3", 1273 "EventName": "UNC_M_RD_CAS_RANK3.BANK15", 1274 "PerPkg": "1", 1275 "UMask": "0xF", 1276 "Unit": "iMC" 1277 }, 1278 { 1279 "BriefDescription": "RD_CAS Access to Rank 3; All Banks", 1280 "Counter": "0,1,2,3", 1281 "EventCode": "0xB3", 1282 "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS", 1283 "PerPkg": "1", 1284 "UMask": "0x10", 1285 "Unit": "iMC" 1286 }, 1287 { 1288 "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 0 (Banks 0-3)", 1289 "Counter": "0,1,2,3", 1290 "EventCode": "0xB3", 1291 "EventName": "UNC_M_RD_CAS_RANK3.BANKG0", 1292 "PerPkg": "1", 1293 "UMask": "0x11", 1294 "Unit": "iMC" 1295 }, 1296 { 1297 "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)", 1298 "Counter": "0,1,2,3", 1299 "EventCode": "0xB3", 1300 "EventName": "UNC_M_RD_CAS_RANK3.BANKG1", 1301 "PerPkg": "1", 1302 "UMask": "0x12", 1303 "Unit": "iMC" 1304 }, 1305 { 1306 "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)", 1307 "Counter": "0,1,2,3", 1308 "EventCode": "0xB3", 1309 "EventName": "UNC_M_RD_CAS_RANK3.BANKG2", 1310 "PerPkg": "1", 1311 "UMask": "0x13", 1312 "Unit": "iMC" 1313 }, 1314 { 1315 "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 3 (Banks 12-15)", 1316 "Counter": "0,1,2,3", 1317 "EventCode": "0xB3", 1318 "EventName": "UNC_M_RD_CAS_RANK3.BANKG3", 1319 "PerPkg": "1", 1320 "UMask": "0x14", 1321 "Unit": "iMC" 1322 }, 1323 { 1324 "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", 1325 "Counter": "0,1,2,3", 1326 "EventCode": "0xB4", 1327 "EventName": "UNC_M_RD_CAS_RANK4.BANK0", 1328 "PerPkg": "1", 1329 "Unit": "iMC" 1330 }, 1331 { 1332 "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", 1333 "Counter": "0,1,2,3", 1334 "EventCode": "0xB4", 1335 "EventName": "UNC_M_RD_CAS_RANK4.BANK1", 1336 "PerPkg": "1", 1337 "UMask": "0x1", 1338 "Unit": "iMC" 1339 }, 1340 { 1341 "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", 1342 "Counter": "0,1,2,3", 1343 "EventCode": "0xB4", 1344 "EventName": "UNC_M_RD_CAS_RANK4.BANK2", 1345 "PerPkg": "1", 1346 "UMask": "0x2", 1347 "Unit": "iMC" 1348 }, 1349 { 1350 "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", 1351 "Counter": "0,1,2,3", 1352 "EventCode": "0xB4", 1353 "EventName": "UNC_M_RD_CAS_RANK4.BANK3", 1354 "PerPkg": "1", 1355 "UMask": "0x3", 1356 "Unit": "iMC" 1357 }, 1358 { 1359 "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", 1360 "Counter": "0,1,2,3", 1361 "EventCode": "0xB4", 1362 "EventName": "UNC_M_RD_CAS_RANK4.BANK4", 1363 "PerPkg": "1", 1364 "UMask": "0x4", 1365 "Unit": "iMC" 1366 }, 1367 { 1368 "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", 1369 "Counter": "0,1,2,3", 1370 "EventCode": "0xB4", 1371 "EventName": "UNC_M_RD_CAS_RANK4.BANK5", 1372 "PerPkg": "1", 1373 "UMask": "0x5", 1374 "Unit": "iMC" 1375 }, 1376 { 1377 "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", 1378 "Counter": "0,1,2,3", 1379 "EventCode": "0xB4", 1380 "EventName": "UNC_M_RD_CAS_RANK4.BANK6", 1381 "PerPkg": "1", 1382 "UMask": "0x6", 1383 "Unit": "iMC" 1384 }, 1385 { 1386 "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", 1387 "Counter": "0,1,2,3", 1388 "EventCode": "0xB4", 1389 "EventName": "UNC_M_RD_CAS_RANK4.BANK7", 1390 "PerPkg": "1", 1391 "UMask": "0x7", 1392 "Unit": "iMC" 1393 }, 1394 { 1395 "BriefDescription": "RD_CAS Access to Rank 4; Bank 8", 1396 "Counter": "0,1,2,3", 1397 "EventCode": "0xB4", 1398 "EventName": "UNC_M_RD_CAS_RANK4.BANK8", 1399 "PerPkg": "1", 1400 "UMask": "0x8", 1401 "Unit": "iMC" 1402 }, 1403 { 1404 "BriefDescription": "RD_CAS Access to Rank 4; Bank 9", 1405 "Counter": "0,1,2,3", 1406 "EventCode": "0xB4", 1407 "EventName": "UNC_M_RD_CAS_RANK4.BANK9", 1408 "PerPkg": "1", 1409 "UMask": "0x9", 1410 "Unit": "iMC" 1411 }, 1412 { 1413 "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", 1414 "Counter": "0,1,2,3", 1415 "EventCode": "0xB4", 1416 "EventName": "UNC_M_RD_CAS_RANK4.BANK10", 1417 "PerPkg": "1", 1418 "UMask": "0xA", 1419 "Unit": "iMC" 1420 }, 1421 { 1422 "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", 1423 "Counter": "0,1,2,3", 1424 "EventCode": "0xB4", 1425 "EventName": "UNC_M_RD_CAS_RANK4.BANK11", 1426 "PerPkg": "1", 1427 "UMask": "0xB", 1428 "Unit": "iMC" 1429 }, 1430 { 1431 "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", 1432 "Counter": "0,1,2,3", 1433 "EventCode": "0xB4", 1434 "EventName": "UNC_M_RD_CAS_RANK4.BANK12", 1435 "PerPkg": "1", 1436 "UMask": "0xC", 1437 "Unit": "iMC" 1438 }, 1439 { 1440 "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", 1441 "Counter": "0,1,2,3", 1442 "EventCode": "0xB4", 1443 "EventName": "UNC_M_RD_CAS_RANK4.BANK13", 1444 "PerPkg": "1", 1445 "UMask": "0xD", 1446 "Unit": "iMC" 1447 }, 1448 { 1449 "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", 1450 "Counter": "0,1,2,3", 1451 "EventCode": "0xB4", 1452 "EventName": "UNC_M_RD_CAS_RANK4.BANK14", 1453 "PerPkg": "1", 1454 "UMask": "0xE", 1455 "Unit": "iMC" 1456 }, 1457 { 1458 "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", 1459 "Counter": "0,1,2,3", 1460 "EventCode": "0xB4", 1461 "EventName": "UNC_M_RD_CAS_RANK4.BANK15", 1462 "PerPkg": "1", 1463 "UMask": "0xF", 1464 "Unit": "iMC" 1465 }, 1466 { 1467 "BriefDescription": "RD_CAS Access to Rank 4; All Banks", 1468 "Counter": "0,1,2,3", 1469 "EventCode": "0xB4", 1470 "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", 1471 "PerPkg": "1", 1472 "UMask": "0x10", 1473 "Unit": "iMC" 1474 }, 1475 { 1476 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)", 1477 "Counter": "0,1,2,3", 1478 "EventCode": "0xB4", 1479 "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", 1480 "PerPkg": "1", 1481 "UMask": "0x11", 1482 "Unit": "iMC" 1483 }, 1484 { 1485 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)", 1486 "Counter": "0,1,2,3", 1487 "EventCode": "0xB4", 1488 "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", 1489 "PerPkg": "1", 1490 "UMask": "0x12", 1491 "Unit": "iMC" 1492 }, 1493 { 1494 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)", 1495 "Counter": "0,1,2,3", 1496 "EventCode": "0xB4", 1497 "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", 1498 "PerPkg": "1", 1499 "UMask": "0x13", 1500 "Unit": "iMC" 1501 }, 1502 { 1503 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)", 1504 "Counter": "0,1,2,3", 1505 "EventCode": "0xB4", 1506 "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", 1507 "PerPkg": "1", 1508 "UMask": "0x14", 1509 "Unit": "iMC" 1510 }, 1511 { 1512 "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", 1513 "Counter": "0,1,2,3", 1514 "EventCode": "0xB5", 1515 "EventName": "UNC_M_RD_CAS_RANK5.BANK0", 1516 "PerPkg": "1", 1517 "Unit": "iMC" 1518 }, 1519 { 1520 "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", 1521 "Counter": "0,1,2,3", 1522 "EventCode": "0xB5", 1523 "EventName": "UNC_M_RD_CAS_RANK5.BANK1", 1524 "PerPkg": "1", 1525 "UMask": "0x1", 1526 "Unit": "iMC" 1527 }, 1528 { 1529 "BriefDescription": "RD_CAS Access to Rank 5; Bank 2", 1530 "Counter": "0,1,2,3", 1531 "EventCode": "0xB5", 1532 "EventName": "UNC_M_RD_CAS_RANK5.BANK2", 1533 "PerPkg": "1", 1534 "UMask": "0x2", 1535 "Unit": "iMC" 1536 }, 1537 { 1538 "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", 1539 "Counter": "0,1,2,3", 1540 "EventCode": "0xB5", 1541 "EventName": "UNC_M_RD_CAS_RANK5.BANK3", 1542 "PerPkg": "1", 1543 "UMask": "0x3", 1544 "Unit": "iMC" 1545 }, 1546 { 1547 "BriefDescription": "RD_CAS Access to Rank 5; Bank 4", 1548 "Counter": "0,1,2,3", 1549 "EventCode": "0xB5", 1550 "EventName": "UNC_M_RD_CAS_RANK5.BANK4", 1551 "PerPkg": "1", 1552 "UMask": "0x4", 1553 "Unit": "iMC" 1554 }, 1555 { 1556 "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", 1557 "Counter": "0,1,2,3", 1558 "EventCode": "0xB5", 1559 "EventName": "UNC_M_RD_CAS_RANK5.BANK5", 1560 "PerPkg": "1", 1561 "UMask": "0x5", 1562 "Unit": "iMC" 1563 }, 1564 { 1565 "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", 1566 "Counter": "0,1,2,3", 1567 "EventCode": "0xB5", 1568 "EventName": "UNC_M_RD_CAS_RANK5.BANK6", 1569 "PerPkg": "1", 1570 "UMask": "0x6", 1571 "Unit": "iMC" 1572 }, 1573 { 1574 "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", 1575 "Counter": "0,1,2,3", 1576 "EventCode": "0xB5", 1577 "EventName": "UNC_M_RD_CAS_RANK5.BANK7", 1578 "PerPkg": "1", 1579 "UMask": "0x7", 1580 "Unit": "iMC" 1581 }, 1582 { 1583 "BriefDescription": "RD_CAS Access to Rank 5; Bank 8", 1584 "Counter": "0,1,2,3", 1585 "EventCode": "0xB5", 1586 "EventName": "UNC_M_RD_CAS_RANK5.BANK8", 1587 "PerPkg": "1", 1588 "UMask": "0x8", 1589 "Unit": "iMC" 1590 }, 1591 { 1592 "BriefDescription": "RD_CAS Access to Rank 5; Bank 9", 1593 "Counter": "0,1,2,3", 1594 "EventCode": "0xB5", 1595 "EventName": "UNC_M_RD_CAS_RANK5.BANK9", 1596 "PerPkg": "1", 1597 "UMask": "0x9", 1598 "Unit": "iMC" 1599 }, 1600 { 1601 "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", 1602 "Counter": "0,1,2,3", 1603 "EventCode": "0xB5", 1604 "EventName": "UNC_M_RD_CAS_RANK5.BANK10", 1605 "PerPkg": "1", 1606 "UMask": "0xA", 1607 "Unit": "iMC" 1608 }, 1609 { 1610 "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", 1611 "Counter": "0,1,2,3", 1612 "EventCode": "0xB5", 1613 "EventName": "UNC_M_RD_CAS_RANK5.BANK11", 1614 "PerPkg": "1", 1615 "UMask": "0xB", 1616 "Unit": "iMC" 1617 }, 1618 { 1619 "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", 1620 "Counter": "0,1,2,3", 1621 "EventCode": "0xB5", 1622 "EventName": "UNC_M_RD_CAS_RANK5.BANK12", 1623 "PerPkg": "1", 1624 "UMask": "0xC", 1625 "Unit": "iMC" 1626 }, 1627 { 1628 "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", 1629 "Counter": "0,1,2,3", 1630 "EventCode": "0xB5", 1631 "EventName": "UNC_M_RD_CAS_RANK5.BANK13", 1632 "PerPkg": "1", 1633 "UMask": "0xD", 1634 "Unit": "iMC" 1635 }, 1636 { 1637 "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", 1638 "Counter": "0,1,2,3", 1639 "EventCode": "0xB5", 1640 "EventName": "UNC_M_RD_CAS_RANK5.BANK14", 1641 "PerPkg": "1", 1642 "UMask": "0xE", 1643 "Unit": "iMC" 1644 }, 1645 { 1646 "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", 1647 "Counter": "0,1,2,3", 1648 "EventCode": "0xB5", 1649 "EventName": "UNC_M_RD_CAS_RANK5.BANK15", 1650 "PerPkg": "1", 1651 "UMask": "0xF", 1652 "Unit": "iMC" 1653 }, 1654 { 1655 "BriefDescription": "RD_CAS Access to Rank 5; All Banks", 1656 "Counter": "0,1,2,3", 1657 "EventCode": "0xB5", 1658 "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", 1659 "PerPkg": "1", 1660 "UMask": "0x10", 1661 "Unit": "iMC" 1662 }, 1663 { 1664 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)", 1665 "Counter": "0,1,2,3", 1666 "EventCode": "0xB5", 1667 "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", 1668 "PerPkg": "1", 1669 "UMask": "0x11", 1670 "Unit": "iMC" 1671 }, 1672 { 1673 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)", 1674 "Counter": "0,1,2,3", 1675 "EventCode": "0xB5", 1676 "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", 1677 "PerPkg": "1", 1678 "UMask": "0x12", 1679 "Unit": "iMC" 1680 }, 1681 { 1682 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)", 1683 "Counter": "0,1,2,3", 1684 "EventCode": "0xB5", 1685 "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", 1686 "PerPkg": "1", 1687 "UMask": "0x13", 1688 "Unit": "iMC" 1689 }, 1690 { 1691 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)", 1692 "Counter": "0,1,2,3", 1693 "EventCode": "0xB5", 1694 "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", 1695 "PerPkg": "1", 1696 "UMask": "0x14", 1697 "Unit": "iMC" 1698 }, 1699 { 1700 "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", 1701 "Counter": "0,1,2,3", 1702 "EventCode": "0xB6", 1703 "EventName": "UNC_M_RD_CAS_RANK6.BANK0", 1704 "PerPkg": "1", 1705 "Unit": "iMC" 1706 }, 1707 { 1708 "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", 1709 "Counter": "0,1,2,3", 1710 "EventCode": "0xB6", 1711 "EventName": "UNC_M_RD_CAS_RANK6.BANK1", 1712 "PerPkg": "1", 1713 "UMask": "0x1", 1714 "Unit": "iMC" 1715 }, 1716 { 1717 "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", 1718 "Counter": "0,1,2,3", 1719 "EventCode": "0xB6", 1720 "EventName": "UNC_M_RD_CAS_RANK6.BANK2", 1721 "PerPkg": "1", 1722 "UMask": "0x2", 1723 "Unit": "iMC" 1724 }, 1725 { 1726 "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", 1727 "Counter": "0,1,2,3", 1728 "EventCode": "0xB6", 1729 "EventName": "UNC_M_RD_CAS_RANK6.BANK3", 1730 "PerPkg": "1", 1731 "UMask": "0x3", 1732 "Unit": "iMC" 1733 }, 1734 { 1735 "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", 1736 "Counter": "0,1,2,3", 1737 "EventCode": "0xB6", 1738 "EventName": "UNC_M_RD_CAS_RANK6.BANK4", 1739 "PerPkg": "1", 1740 "UMask": "0x4", 1741 "Unit": "iMC" 1742 }, 1743 { 1744 "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", 1745 "Counter": "0,1,2,3", 1746 "EventCode": "0xB6", 1747 "EventName": "UNC_M_RD_CAS_RANK6.BANK5", 1748 "PerPkg": "1", 1749 "UMask": "0x5", 1750 "Unit": "iMC" 1751 }, 1752 { 1753 "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", 1754 "Counter": "0,1,2,3", 1755 "EventCode": "0xB6", 1756 "EventName": "UNC_M_RD_CAS_RANK6.BANK6", 1757 "PerPkg": "1", 1758 "UMask": "0x6", 1759 "Unit": "iMC" 1760 }, 1761 { 1762 "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", 1763 "Counter": "0,1,2,3", 1764 "EventCode": "0xB6", 1765 "EventName": "UNC_M_RD_CAS_RANK6.BANK7", 1766 "PerPkg": "1", 1767 "UMask": "0x7", 1768 "Unit": "iMC" 1769 }, 1770 { 1771 "BriefDescription": "RD_CAS Access to Rank 6; Bank 8", 1772 "Counter": "0,1,2,3", 1773 "EventCode": "0xB6", 1774 "EventName": "UNC_M_RD_CAS_RANK6.BANK8", 1775 "PerPkg": "1", 1776 "UMask": "0x8", 1777 "Unit": "iMC" 1778 }, 1779 { 1780 "BriefDescription": "RD_CAS Access to Rank 6; Bank 9", 1781 "Counter": "0,1,2,3", 1782 "EventCode": "0xB6", 1783 "EventName": "UNC_M_RD_CAS_RANK6.BANK9", 1784 "PerPkg": "1", 1785 "UMask": "0x9", 1786 "Unit": "iMC" 1787 }, 1788 { 1789 "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", 1790 "Counter": "0,1,2,3", 1791 "EventCode": "0xB6", 1792 "EventName": "UNC_M_RD_CAS_RANK6.BANK10", 1793 "PerPkg": "1", 1794 "UMask": "0xA", 1795 "Unit": "iMC" 1796 }, 1797 { 1798 "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", 1799 "Counter": "0,1,2,3", 1800 "EventCode": "0xB6", 1801 "EventName": "UNC_M_RD_CAS_RANK6.BANK11", 1802 "PerPkg": "1", 1803 "UMask": "0xB", 1804 "Unit": "iMC" 1805 }, 1806 { 1807 "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", 1808 "Counter": "0,1,2,3", 1809 "EventCode": "0xB6", 1810 "EventName": "UNC_M_RD_CAS_RANK6.BANK12", 1811 "PerPkg": "1", 1812 "UMask": "0xC", 1813 "Unit": "iMC" 1814 }, 1815 { 1816 "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", 1817 "Counter": "0,1,2,3", 1818 "EventCode": "0xB6", 1819 "EventName": "UNC_M_RD_CAS_RANK6.BANK13", 1820 "PerPkg": "1", 1821 "UMask": "0xD", 1822 "Unit": "iMC" 1823 }, 1824 { 1825 "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", 1826 "Counter": "0,1,2,3", 1827 "EventCode": "0xB6", 1828 "EventName": "UNC_M_RD_CAS_RANK6.BANK14", 1829 "PerPkg": "1", 1830 "UMask": "0xE", 1831 "Unit": "iMC" 1832 }, 1833 { 1834 "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", 1835 "Counter": "0,1,2,3", 1836 "EventCode": "0xB6", 1837 "EventName": "UNC_M_RD_CAS_RANK6.BANK15", 1838 "PerPkg": "1", 1839 "UMask": "0xF", 1840 "Unit": "iMC" 1841 }, 1842 { 1843 "BriefDescription": "RD_CAS Access to Rank 6; All Banks", 1844 "Counter": "0,1,2,3", 1845 "EventCode": "0xB6", 1846 "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", 1847 "PerPkg": "1", 1848 "UMask": "0x10", 1849 "Unit": "iMC" 1850 }, 1851 { 1852 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)", 1853 "Counter": "0,1,2,3", 1854 "EventCode": "0xB6", 1855 "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", 1856 "PerPkg": "1", 1857 "UMask": "0x11", 1858 "Unit": "iMC" 1859 }, 1860 { 1861 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)", 1862 "Counter": "0,1,2,3", 1863 "EventCode": "0xB6", 1864 "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", 1865 "PerPkg": "1", 1866 "UMask": "0x12", 1867 "Unit": "iMC" 1868 }, 1869 { 1870 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)", 1871 "Counter": "0,1,2,3", 1872 "EventCode": "0xB6", 1873 "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", 1874 "PerPkg": "1", 1875 "UMask": "0x13", 1876 "Unit": "iMC" 1877 }, 1878 { 1879 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)", 1880 "Counter": "0,1,2,3", 1881 "EventCode": "0xB6", 1882 "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", 1883 "PerPkg": "1", 1884 "UMask": "0x14", 1885 "Unit": "iMC" 1886 }, 1887 { 1888 "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", 1889 "Counter": "0,1,2,3", 1890 "EventCode": "0xB7", 1891 "EventName": "UNC_M_RD_CAS_RANK7.BANK0", 1892 "PerPkg": "1", 1893 "Unit": "iMC" 1894 }, 1895 { 1896 "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", 1897 "Counter": "0,1,2,3", 1898 "EventCode": "0xB7", 1899 "EventName": "UNC_M_RD_CAS_RANK7.BANK1", 1900 "PerPkg": "1", 1901 "UMask": "0x1", 1902 "Unit": "iMC" 1903 }, 1904 { 1905 "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", 1906 "Counter": "0,1,2,3", 1907 "EventCode": "0xB7", 1908 "EventName": "UNC_M_RD_CAS_RANK7.BANK2", 1909 "PerPkg": "1", 1910 "UMask": "0x2", 1911 "Unit": "iMC" 1912 }, 1913 { 1914 "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", 1915 "Counter": "0,1,2,3", 1916 "EventCode": "0xB7", 1917 "EventName": "UNC_M_RD_CAS_RANK7.BANK3", 1918 "PerPkg": "1", 1919 "UMask": "0x3", 1920 "Unit": "iMC" 1921 }, 1922 { 1923 "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", 1924 "Counter": "0,1,2,3", 1925 "EventCode": "0xB7", 1926 "EventName": "UNC_M_RD_CAS_RANK7.BANK4", 1927 "PerPkg": "1", 1928 "UMask": "0x4", 1929 "Unit": "iMC" 1930 }, 1931 { 1932 "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", 1933 "Counter": "0,1,2,3", 1934 "EventCode": "0xB7", 1935 "EventName": "UNC_M_RD_CAS_RANK7.BANK5", 1936 "PerPkg": "1", 1937 "UMask": "0x5", 1938 "Unit": "iMC" 1939 }, 1940 { 1941 "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", 1942 "Counter": "0,1,2,3", 1943 "EventCode": "0xB7", 1944 "EventName": "UNC_M_RD_CAS_RANK7.BANK6", 1945 "PerPkg": "1", 1946 "UMask": "0x6", 1947 "Unit": "iMC" 1948 }, 1949 { 1950 "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", 1951 "Counter": "0,1,2,3", 1952 "EventCode": "0xB7", 1953 "EventName": "UNC_M_RD_CAS_RANK7.BANK7", 1954 "PerPkg": "1", 1955 "UMask": "0x7", 1956 "Unit": "iMC" 1957 }, 1958 { 1959 "BriefDescription": "RD_CAS Access to Rank 7; Bank 8", 1960 "Counter": "0,1,2,3", 1961 "EventCode": "0xB7", 1962 "EventName": "UNC_M_RD_CAS_RANK7.BANK8", 1963 "PerPkg": "1", 1964 "UMask": "0x8", 1965 "Unit": "iMC" 1966 }, 1967 { 1968 "BriefDescription": "RD_CAS Access to Rank 7; Bank 9", 1969 "Counter": "0,1,2,3", 1970 "EventCode": "0xB7", 1971 "EventName": "UNC_M_RD_CAS_RANK7.BANK9", 1972 "PerPkg": "1", 1973 "UMask": "0x9", 1974 "Unit": "iMC" 1975 }, 1976 { 1977 "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", 1978 "Counter": "0,1,2,3", 1979 "EventCode": "0xB7", 1980 "EventName": "UNC_M_RD_CAS_RANK7.BANK10", 1981 "PerPkg": "1", 1982 "UMask": "0xA", 1983 "Unit": "iMC" 1984 }, 1985 { 1986 "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", 1987 "Counter": "0,1,2,3", 1988 "EventCode": "0xB7", 1989 "EventName": "UNC_M_RD_CAS_RANK7.BANK11", 1990 "PerPkg": "1", 1991 "UMask": "0xB", 1992 "Unit": "iMC" 1993 }, 1994 { 1995 "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", 1996 "Counter": "0,1,2,3", 1997 "EventCode": "0xB7", 1998 "EventName": "UNC_M_RD_CAS_RANK7.BANK12", 1999 "PerPkg": "1", 2000 "UMask": "0xC", 2001 "Unit": "iMC" 2002 }, 2003 { 2004 "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", 2005 "Counter": "0,1,2,3", 2006 "EventCode": "0xB7", 2007 "EventName": "UNC_M_RD_CAS_RANK7.BANK13", 2008 "PerPkg": "1", 2009 "UMask": "0xD", 2010 "Unit": "iMC" 2011 }, 2012 { 2013 "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", 2014 "Counter": "0,1,2,3", 2015 "EventCode": "0xB7", 2016 "EventName": "UNC_M_RD_CAS_RANK7.BANK14", 2017 "PerPkg": "1", 2018 "UMask": "0xE", 2019 "Unit": "iMC" 2020 }, 2021 { 2022 "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", 2023 "Counter": "0,1,2,3", 2024 "EventCode": "0xB7", 2025 "EventName": "UNC_M_RD_CAS_RANK7.BANK15", 2026 "PerPkg": "1", 2027 "UMask": "0xF", 2028 "Unit": "iMC" 2029 }, 2030 { 2031 "BriefDescription": "RD_CAS Access to Rank 7; All Banks", 2032 "Counter": "0,1,2,3", 2033 "EventCode": "0xB7", 2034 "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", 2035 "PerPkg": "1", 2036 "UMask": "0x10", 2037 "Unit": "iMC" 2038 }, 2039 { 2040 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)", 2041 "Counter": "0,1,2,3", 2042 "EventCode": "0xB7", 2043 "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", 2044 "PerPkg": "1", 2045 "UMask": "0x11", 2046 "Unit": "iMC" 2047 }, 2048 { 2049 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)", 2050 "Counter": "0,1,2,3", 2051 "EventCode": "0xB7", 2052 "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", 2053 "PerPkg": "1", 2054 "UMask": "0x12", 2055 "Unit": "iMC" 2056 }, 2057 { 2058 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)", 2059 "Counter": "0,1,2,3", 2060 "EventCode": "0xB7", 2061 "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", 2062 "PerPkg": "1", 2063 "UMask": "0x13", 2064 "Unit": "iMC" 2065 }, 2066 { 2067 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)", 2068 "Counter": "0,1,2,3", 2069 "EventCode": "0xB7", 2070 "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", 2071 "PerPkg": "1", 2072 "UMask": "0x14", 2073 "Unit": "iMC" 2074 }, 2075 { 2076 "BriefDescription": "Read Pending Queue Full Cycles", 2077 "Counter": "0,1,2,3", 2078 "EventCode": "0x12", 2079 "EventName": "UNC_M_RPQ_CYCLES_FULL", 2080 "PerPkg": "1", 2081 "Unit": "iMC" 2082 }, 2083 { 2084 "BriefDescription": "Read Pending Queue Not Empty", 2085 "Counter": "0,1,2,3", 2086 "EventCode": "0x11", 2087 "EventName": "UNC_M_RPQ_CYCLES_NE", 2088 "PerPkg": "1", 2089 "Unit": "iMC" 2090 }, 2091 { 2092 "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter", 2093 "Counter": "0,1,2,3", 2094 "EventCode": "0xC0", 2095 "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", 2096 "PerPkg": "1", 2097 "UMask": "0x1", 2098 "Unit": "iMC" 2099 }, 2100 { 2101 "BriefDescription": "Transition from WMM to RMM because of low threshold", 2102 "Counter": "0,1,2,3", 2103 "EventCode": "0xC0", 2104 "EventName": "UNC_M_WMM_TO_RMM.STARVE", 2105 "PerPkg": "1", 2106 "UMask": "0x2", 2107 "Unit": "iMC" 2108 }, 2109 { 2110 "BriefDescription": "Transition from WMM to RMM because of low threshold", 2111 "Counter": "0,1,2,3", 2112 "EventCode": "0xC0", 2113 "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", 2114 "PerPkg": "1", 2115 "UMask": "0x4", 2116 "Unit": "iMC" 2117 }, 2118 { 2119 "BriefDescription": "Write Pending Queue Full Cycles", 2120 "Counter": "0,1,2,3", 2121 "EventCode": "0x22", 2122 "EventName": "UNC_M_WPQ_CYCLES_FULL", 2123 "PerPkg": "1", 2124 "Unit": "iMC" 2125 }, 2126 { 2127 "BriefDescription": "Write Pending Queue Not Empty", 2128 "Counter": "0,1,2,3", 2129 "EventCode": "0x21", 2130 "EventName": "UNC_M_WPQ_CYCLES_NE", 2131 "PerPkg": "1", 2132 "Unit": "iMC" 2133 }, 2134 { 2135 "BriefDescription": "Write Pending Queue CAM Match", 2136 "Counter": "0,1,2,3", 2137 "EventCode": "0x23", 2138 "EventName": "UNC_M_WPQ_READ_HIT", 2139 "PerPkg": "1", 2140 "Unit": "iMC" 2141 }, 2142 { 2143 "BriefDescription": "Write Pending Queue CAM Match", 2144 "Counter": "0,1,2,3", 2145 "EventCode": "0x24", 2146 "EventName": "UNC_M_WPQ_WRITE_HIT", 2147 "PerPkg": "1", 2148 "Unit": "iMC" 2149 }, 2150 { 2151 "BriefDescription": "Not getting the requested Major Mode", 2152 "Counter": "0,1,2,3", 2153 "EventCode": "0xC1", 2154 "EventName": "UNC_M_WRONG_MM", 2155 "PerPkg": "1", 2156 "Unit": "iMC" 2157 }, 2158 { 2159 "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", 2160 "Counter": "0,1,2,3", 2161 "EventCode": "0xB8", 2162 "EventName": "UNC_M_WR_CAS_RANK0.BANK0", 2163 "PerPkg": "1", 2164 "Unit": "iMC" 2165 }, 2166 { 2167 "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", 2168 "Counter": "0,1,2,3", 2169 "EventCode": "0xB8", 2170 "EventName": "UNC_M_WR_CAS_RANK0.BANK1", 2171 "PerPkg": "1", 2172 "UMask": "0x1", 2173 "Unit": "iMC" 2174 }, 2175 { 2176 "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", 2177 "Counter": "0,1,2,3", 2178 "EventCode": "0xB8", 2179 "EventName": "UNC_M_WR_CAS_RANK0.BANK2", 2180 "PerPkg": "1", 2181 "UMask": "0x2", 2182 "Unit": "iMC" 2183 }, 2184 { 2185 "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", 2186 "Counter": "0,1,2,3", 2187 "EventCode": "0xB8", 2188 "EventName": "UNC_M_WR_CAS_RANK0.BANK3", 2189 "PerPkg": "1", 2190 "UMask": "0x3", 2191 "Unit": "iMC" 2192 }, 2193 { 2194 "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", 2195 "Counter": "0,1,2,3", 2196 "EventCode": "0xB8", 2197 "EventName": "UNC_M_WR_CAS_RANK0.BANK4", 2198 "PerPkg": "1", 2199 "UMask": "0x4", 2200 "Unit": "iMC" 2201 }, 2202 { 2203 "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", 2204 "Counter": "0,1,2,3", 2205 "EventCode": "0xB8", 2206 "EventName": "UNC_M_WR_CAS_RANK0.BANK5", 2207 "PerPkg": "1", 2208 "UMask": "0x5", 2209 "Unit": "iMC" 2210 }, 2211 { 2212 "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", 2213 "Counter": "0,1,2,3", 2214 "EventCode": "0xB8", 2215 "EventName": "UNC_M_WR_CAS_RANK0.BANK6", 2216 "PerPkg": "1", 2217 "UMask": "0x6", 2218 "Unit": "iMC" 2219 }, 2220 { 2221 "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", 2222 "Counter": "0,1,2,3", 2223 "EventCode": "0xB8", 2224 "EventName": "UNC_M_WR_CAS_RANK0.BANK7", 2225 "PerPkg": "1", 2226 "UMask": "0x7", 2227 "Unit": "iMC" 2228 }, 2229 { 2230 "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", 2231 "Counter": "0,1,2,3", 2232 "EventCode": "0xB8", 2233 "EventName": "UNC_M_WR_CAS_RANK0.BANK8", 2234 "PerPkg": "1", 2235 "UMask": "0x8", 2236 "Unit": "iMC" 2237 }, 2238 { 2239 "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", 2240 "Counter": "0,1,2,3", 2241 "EventCode": "0xB8", 2242 "EventName": "UNC_M_WR_CAS_RANK0.BANK9", 2243 "PerPkg": "1", 2244 "UMask": "0x9", 2245 "Unit": "iMC" 2246 }, 2247 { 2248 "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", 2249 "Counter": "0,1,2,3", 2250 "EventCode": "0xB8", 2251 "EventName": "UNC_M_WR_CAS_RANK0.BANK10", 2252 "PerPkg": "1", 2253 "UMask": "0xA", 2254 "Unit": "iMC" 2255 }, 2256 { 2257 "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", 2258 "Counter": "0,1,2,3", 2259 "EventCode": "0xB8", 2260 "EventName": "UNC_M_WR_CAS_RANK0.BANK11", 2261 "PerPkg": "1", 2262 "UMask": "0xB", 2263 "Unit": "iMC" 2264 }, 2265 { 2266 "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", 2267 "Counter": "0,1,2,3", 2268 "EventCode": "0xB8", 2269 "EventName": "UNC_M_WR_CAS_RANK0.BANK12", 2270 "PerPkg": "1", 2271 "UMask": "0xC", 2272 "Unit": "iMC" 2273 }, 2274 { 2275 "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", 2276 "Counter": "0,1,2,3", 2277 "EventCode": "0xB8", 2278 "EventName": "UNC_M_WR_CAS_RANK0.BANK13", 2279 "PerPkg": "1", 2280 "UMask": "0xD", 2281 "Unit": "iMC" 2282 }, 2283 { 2284 "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", 2285 "Counter": "0,1,2,3", 2286 "EventCode": "0xB8", 2287 "EventName": "UNC_M_WR_CAS_RANK0.BANK14", 2288 "PerPkg": "1", 2289 "UMask": "0xE", 2290 "Unit": "iMC" 2291 }, 2292 { 2293 "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", 2294 "Counter": "0,1,2,3", 2295 "EventCode": "0xB8", 2296 "EventName": "UNC_M_WR_CAS_RANK0.BANK15", 2297 "PerPkg": "1", 2298 "UMask": "0xF", 2299 "Unit": "iMC" 2300 }, 2301 { 2302 "BriefDescription": "WR_CAS Access to Rank 0; All Banks", 2303 "Counter": "0,1,2,3", 2304 "EventCode": "0xB8", 2305 "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", 2306 "PerPkg": "1", 2307 "UMask": "0x10", 2308 "Unit": "iMC" 2309 }, 2310 { 2311 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", 2312 "Counter": "0,1,2,3", 2313 "EventCode": "0xB8", 2314 "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", 2315 "PerPkg": "1", 2316 "UMask": "0x11", 2317 "Unit": "iMC" 2318 }, 2319 { 2320 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", 2321 "Counter": "0,1,2,3", 2322 "EventCode": "0xB8", 2323 "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", 2324 "PerPkg": "1", 2325 "UMask": "0x12", 2326 "Unit": "iMC" 2327 }, 2328 { 2329 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", 2330 "Counter": "0,1,2,3", 2331 "EventCode": "0xB8", 2332 "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", 2333 "PerPkg": "1", 2334 "UMask": "0x13", 2335 "Unit": "iMC" 2336 }, 2337 { 2338 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", 2339 "Counter": "0,1,2,3", 2340 "EventCode": "0xB8", 2341 "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", 2342 "PerPkg": "1", 2343 "UMask": "0x14", 2344 "Unit": "iMC" 2345 }, 2346 { 2347 "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", 2348 "Counter": "0,1,2,3", 2349 "EventCode": "0xB9", 2350 "EventName": "UNC_M_WR_CAS_RANK1.BANK0", 2351 "PerPkg": "1", 2352 "Unit": "iMC" 2353 }, 2354 { 2355 "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", 2356 "Counter": "0,1,2,3", 2357 "EventCode": "0xB9", 2358 "EventName": "UNC_M_WR_CAS_RANK1.BANK1", 2359 "PerPkg": "1", 2360 "UMask": "0x1", 2361 "Unit": "iMC" 2362 }, 2363 { 2364 "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", 2365 "Counter": "0,1,2,3", 2366 "EventCode": "0xB9", 2367 "EventName": "UNC_M_WR_CAS_RANK1.BANK2", 2368 "PerPkg": "1", 2369 "UMask": "0x2", 2370 "Unit": "iMC" 2371 }, 2372 { 2373 "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", 2374 "Counter": "0,1,2,3", 2375 "EventCode": "0xB9", 2376 "EventName": "UNC_M_WR_CAS_RANK1.BANK3", 2377 "PerPkg": "1", 2378 "UMask": "0x3", 2379 "Unit": "iMC" 2380 }, 2381 { 2382 "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", 2383 "Counter": "0,1,2,3", 2384 "EventCode": "0xB9", 2385 "EventName": "UNC_M_WR_CAS_RANK1.BANK4", 2386 "PerPkg": "1", 2387 "UMask": "0x4", 2388 "Unit": "iMC" 2389 }, 2390 { 2391 "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", 2392 "Counter": "0,1,2,3", 2393 "EventCode": "0xB9", 2394 "EventName": "UNC_M_WR_CAS_RANK1.BANK5", 2395 "PerPkg": "1", 2396 "UMask": "0x5", 2397 "Unit": "iMC" 2398 }, 2399 { 2400 "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", 2401 "Counter": "0,1,2,3", 2402 "EventCode": "0xB9", 2403 "EventName": "UNC_M_WR_CAS_RANK1.BANK6", 2404 "PerPkg": "1", 2405 "UMask": "0x6", 2406 "Unit": "iMC" 2407 }, 2408 { 2409 "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", 2410 "Counter": "0,1,2,3", 2411 "EventCode": "0xB9", 2412 "EventName": "UNC_M_WR_CAS_RANK1.BANK7", 2413 "PerPkg": "1", 2414 "UMask": "0x7", 2415 "Unit": "iMC" 2416 }, 2417 { 2418 "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", 2419 "Counter": "0,1,2,3", 2420 "EventCode": "0xB9", 2421 "EventName": "UNC_M_WR_CAS_RANK1.BANK8", 2422 "PerPkg": "1", 2423 "UMask": "0x8", 2424 "Unit": "iMC" 2425 }, 2426 { 2427 "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", 2428 "Counter": "0,1,2,3", 2429 "EventCode": "0xB9", 2430 "EventName": "UNC_M_WR_CAS_RANK1.BANK9", 2431 "PerPkg": "1", 2432 "UMask": "0x9", 2433 "Unit": "iMC" 2434 }, 2435 { 2436 "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", 2437 "Counter": "0,1,2,3", 2438 "EventCode": "0xB9", 2439 "EventName": "UNC_M_WR_CAS_RANK1.BANK10", 2440 "PerPkg": "1", 2441 "UMask": "0xA", 2442 "Unit": "iMC" 2443 }, 2444 { 2445 "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", 2446 "Counter": "0,1,2,3", 2447 "EventCode": "0xB9", 2448 "EventName": "UNC_M_WR_CAS_RANK1.BANK11", 2449 "PerPkg": "1", 2450 "UMask": "0xB", 2451 "Unit": "iMC" 2452 }, 2453 { 2454 "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", 2455 "Counter": "0,1,2,3", 2456 "EventCode": "0xB9", 2457 "EventName": "UNC_M_WR_CAS_RANK1.BANK12", 2458 "PerPkg": "1", 2459 "UMask": "0xC", 2460 "Unit": "iMC" 2461 }, 2462 { 2463 "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", 2464 "Counter": "0,1,2,3", 2465 "EventCode": "0xB9", 2466 "EventName": "UNC_M_WR_CAS_RANK1.BANK13", 2467 "PerPkg": "1", 2468 "UMask": "0xD", 2469 "Unit": "iMC" 2470 }, 2471 { 2472 "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", 2473 "Counter": "0,1,2,3", 2474 "EventCode": "0xB9", 2475 "EventName": "UNC_M_WR_CAS_RANK1.BANK14", 2476 "PerPkg": "1", 2477 "UMask": "0xE", 2478 "Unit": "iMC" 2479 }, 2480 { 2481 "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", 2482 "Counter": "0,1,2,3", 2483 "EventCode": "0xB9", 2484 "EventName": "UNC_M_WR_CAS_RANK1.BANK15", 2485 "PerPkg": "1", 2486 "UMask": "0xF", 2487 "Unit": "iMC" 2488 }, 2489 { 2490 "BriefDescription": "WR_CAS Access to Rank 1; All Banks", 2491 "Counter": "0,1,2,3", 2492 "EventCode": "0xB9", 2493 "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", 2494 "PerPkg": "1", 2495 "UMask": "0x10", 2496 "Unit": "iMC" 2497 }, 2498 { 2499 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", 2500 "Counter": "0,1,2,3", 2501 "EventCode": "0xB9", 2502 "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", 2503 "PerPkg": "1", 2504 "UMask": "0x11", 2505 "Unit": "iMC" 2506 }, 2507 { 2508 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", 2509 "Counter": "0,1,2,3", 2510 "EventCode": "0xB9", 2511 "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", 2512 "PerPkg": "1", 2513 "UMask": "0x12", 2514 "Unit": "iMC" 2515 }, 2516 { 2517 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)", 2518 "Counter": "0,1,2,3", 2519 "EventCode": "0xB9", 2520 "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", 2521 "PerPkg": "1", 2522 "UMask": "0x13", 2523 "Unit": "iMC" 2524 }, 2525 { 2526 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)", 2527 "Counter": "0,1,2,3", 2528 "EventCode": "0xB9", 2529 "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", 2530 "PerPkg": "1", 2531 "UMask": "0x14", 2532 "Unit": "iMC" 2533 }, 2534 { 2535 "BriefDescription": "WR_CAS Access to Rank 2; Bank 0", 2536 "Counter": "0,1,2,3", 2537 "EventCode": "0xBA", 2538 "EventName": "UNC_M_WR_CAS_RANK2.BANK0", 2539 "PerPkg": "1", 2540 "Unit": "iMC" 2541 }, 2542 { 2543 "BriefDescription": "WR_CAS Access to Rank 2; Bank 1", 2544 "Counter": "0,1,2,3", 2545 "EventCode": "0xBA", 2546 "EventName": "UNC_M_WR_CAS_RANK2.BANK1", 2547 "PerPkg": "1", 2548 "UMask": "0x1", 2549 "Unit": "iMC" 2550 }, 2551 { 2552 "BriefDescription": "WR_CAS Access to Rank 2; Bank 2", 2553 "Counter": "0,1,2,3", 2554 "EventCode": "0xBA", 2555 "EventName": "UNC_M_WR_CAS_RANK2.BANK2", 2556 "PerPkg": "1", 2557 "UMask": "0x2", 2558 "Unit": "iMC" 2559 }, 2560 { 2561 "BriefDescription": "WR_CAS Access to Rank 2; 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