1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // mt8186-afe-clk.c -- Mediatek 8186 afe clock ctrl
4 //
5 // Copyright (c) 2022 MediaTek Inc.
6 // Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
7
8 #include <linux/clk.h>
9 #include <linux/regmap.h>
10 #include <linux/mfd/syscon.h>
11
12 #include "mt8186-afe-common.h"
13 #include "mt8186-afe-clk.h"
14 #include "mt8186-audsys-clk.h"
15
16 static DEFINE_MUTEX(mutex_request_dram);
17
18 static const char *aud_clks[CLK_NUM] = {
19 [CLK_AFE] = "aud_afe_clk",
20 [CLK_DAC] = "aud_dac_clk",
21 [CLK_DAC_PREDIS] = "aud_dac_predis_clk",
22 [CLK_ADC] = "aud_adc_clk",
23 [CLK_TML] = "aud_tml_clk",
24 [CLK_APLL22M] = "aud_apll22m_clk",
25 [CLK_APLL24M] = "aud_apll24m_clk",
26 [CLK_APLL1_TUNER] = "aud_apll_tuner_clk",
27 [CLK_APLL2_TUNER] = "aud_apll2_tuner_clk",
28 [CLK_TDM] = "aud_tdm_clk",
29 [CLK_NLE] = "aud_nle_clk",
30 [CLK_DAC_HIRES] = "aud_dac_hires_clk",
31 [CLK_ADC_HIRES] = "aud_adc_hires_clk",
32 [CLK_I2S1_BCLK] = "aud_i2s1_bclk",
33 [CLK_I2S2_BCLK] = "aud_i2s2_bclk",
34 [CLK_I2S3_BCLK] = "aud_i2s3_bclk",
35 [CLK_I2S4_BCLK] = "aud_i2s4_bclk",
36 [CLK_CONNSYS_I2S_ASRC] = "aud_connsys_i2s_asrc",
37 [CLK_GENERAL1_ASRC] = "aud_general1_asrc",
38 [CLK_GENERAL2_ASRC] = "aud_general2_asrc",
39 [CLK_ADC_HIRES_TML] = "aud_adc_hires_tml",
40 [CLK_ADDA6_ADC] = "aud_adda6_adc",
41 [CLK_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires",
42 [CLK_3RD_DAC] = "aud_3rd_dac",
43 [CLK_3RD_DAC_PREDIS] = "aud_3rd_dac_predis",
44 [CLK_3RD_DAC_TML] = "aud_3rd_dac_tml",
45 [CLK_3RD_DAC_HIRES] = "aud_3rd_dac_hires",
46 [CLK_ETDM_IN1_BCLK] = "aud_etdm_in1_bclk",
47 [CLK_ETDM_OUT1_BCLK] = "aud_etdm_out1_bclk",
48 [CLK_INFRA_SYS_AUDIO] = "aud_infra_clk",
49 [CLK_INFRA_AUDIO_26M] = "mtkaif_26m_clk",
50 [CLK_MUX_AUDIO] = "top_mux_audio",
51 [CLK_MUX_AUDIOINTBUS] = "top_mux_audio_int",
52 [CLK_TOP_MAINPLL_D2_D4] = "top_mainpll_d2_d4",
53 [CLK_TOP_MUX_AUD_1] = "top_mux_aud_1",
54 [CLK_TOP_APLL1_CK] = "top_apll1_ck",
55 [CLK_TOP_MUX_AUD_2] = "top_mux_aud_2",
56 [CLK_TOP_APLL2_CK] = "top_apll2_ck",
57 [CLK_TOP_MUX_AUD_ENG1] = "top_mux_aud_eng1",
58 [CLK_TOP_APLL1_D8] = "top_apll1_d8",
59 [CLK_TOP_MUX_AUD_ENG2] = "top_mux_aud_eng2",
60 [CLK_TOP_APLL2_D8] = "top_apll2_d8",
61 [CLK_TOP_MUX_AUDIO_H] = "top_mux_audio_h",
62 [CLK_TOP_I2S0_M_SEL] = "top_i2s0_m_sel",
63 [CLK_TOP_I2S1_M_SEL] = "top_i2s1_m_sel",
64 [CLK_TOP_I2S2_M_SEL] = "top_i2s2_m_sel",
65 [CLK_TOP_I2S4_M_SEL] = "top_i2s4_m_sel",
66 [CLK_TOP_TDM_M_SEL] = "top_tdm_m_sel",
67 [CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
68 [CLK_TOP_APLL12_DIV1] = "top_apll12_div1",
69 [CLK_TOP_APLL12_DIV2] = "top_apll12_div2",
70 [CLK_TOP_APLL12_DIV4] = "top_apll12_div4",
71 [CLK_TOP_APLL12_DIV_TDM] = "top_apll12_div_tdm",
72 [CLK_CLK26M] = "top_clk26m_clk",
73 };
74
mt8186_set_audio_int_bus_parent(struct mtk_base_afe * afe,int clk_id)75 int mt8186_set_audio_int_bus_parent(struct mtk_base_afe *afe,
76 int clk_id)
77 {
78 struct mt8186_afe_private *afe_priv = afe->platform_priv;
79 int ret;
80
81 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
82 afe_priv->clk[clk_id]);
83 if (ret) {
84 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
85 __func__, aud_clks[CLK_MUX_AUDIOINTBUS],
86 aud_clks[clk_id], ret);
87 return ret;
88 }
89
90 return 0;
91 }
92
apll1_mux_setting(struct mtk_base_afe * afe,bool enable)93 static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
94 {
95 struct mt8186_afe_private *afe_priv = afe->platform_priv;
96 int ret;
97
98 if (enable) {
99 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
100 if (ret) {
101 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
102 __func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);
103 return ret;
104 }
105 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
106 afe_priv->clk[CLK_TOP_APLL1_CK]);
107 if (ret) {
108 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
109 __func__, aud_clks[CLK_TOP_MUX_AUD_1],
110 aud_clks[CLK_TOP_APLL1_CK], ret);
111 return ret;
112 }
113
114 /* 180.6336 / 8 = 22.5792MHz */
115 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
116 if (ret) {
117 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
118 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);
119 return ret;
120 }
121 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
122 afe_priv->clk[CLK_TOP_APLL1_D8]);
123 if (ret) {
124 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
125 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
126 aud_clks[CLK_TOP_APLL1_D8], ret);
127 return ret;
128 }
129 } else {
130 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
131 afe_priv->clk[CLK_CLK26M]);
132 if (ret) {
133 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
134 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
135 aud_clks[CLK_CLK26M], ret);
136 return ret;
137 }
138 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
139
140 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
141 afe_priv->clk[CLK_CLK26M]);
142 if (ret) {
143 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
144 __func__, aud_clks[CLK_TOP_MUX_AUD_1],
145 aud_clks[CLK_CLK26M], ret);
146 return ret;
147 }
148 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
149 }
150
151 return 0;
152 }
153
apll2_mux_setting(struct mtk_base_afe * afe,bool enable)154 static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
155 {
156 struct mt8186_afe_private *afe_priv = afe->platform_priv;
157 int ret;
158
159 if (enable) {
160 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
161 if (ret) {
162 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
163 __func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);
164 return ret;
165 }
166 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
167 afe_priv->clk[CLK_TOP_APLL2_CK]);
168 if (ret) {
169 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
170 __func__, aud_clks[CLK_TOP_MUX_AUD_2],
171 aud_clks[CLK_TOP_APLL2_CK], ret);
172 return ret;
173 }
174
175 /* 196.608 / 8 = 24.576MHz */
176 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
177 if (ret) {
178 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
179 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);
180 return ret;
181 }
182 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
183 afe_priv->clk[CLK_TOP_APLL2_D8]);
184 if (ret) {
185 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
186 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
187 aud_clks[CLK_TOP_APLL2_D8], ret);
188 return ret;
189 }
190 } else {
191 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
192 afe_priv->clk[CLK_CLK26M]);
193 if (ret) {
194 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
195 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
196 aud_clks[CLK_CLK26M], ret);
197 return ret;
198 }
199 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
200
201 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
202 afe_priv->clk[CLK_CLK26M]);
203 if (ret) {
204 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
205 __func__, aud_clks[CLK_TOP_MUX_AUD_2],
206 aud_clks[CLK_CLK26M], ret);
207 return ret;
208 }
209 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
210 }
211
212 return 0;
213 }
214
mt8186_afe_enable_cgs(struct mtk_base_afe * afe)215 int mt8186_afe_enable_cgs(struct mtk_base_afe *afe)
216 {
217 struct mt8186_afe_private *afe_priv = afe->platform_priv;
218 int ret = 0;
219 int i;
220
221 for (i = CLK_I2S1_BCLK; i <= CLK_ETDM_OUT1_BCLK; i++) {
222 ret = clk_prepare_enable(afe_priv->clk[i]);
223 if (ret) {
224 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
225 __func__, aud_clks[i], ret);
226 return ret;
227 }
228 }
229
230 return 0;
231 }
232
mt8186_afe_disable_cgs(struct mtk_base_afe * afe)233 void mt8186_afe_disable_cgs(struct mtk_base_afe *afe)
234 {
235 struct mt8186_afe_private *afe_priv = afe->platform_priv;
236 int i;
237
238 for (i = CLK_I2S1_BCLK; i <= CLK_ETDM_OUT1_BCLK; i++)
239 clk_disable_unprepare(afe_priv->clk[i]);
240 }
241
mt8186_afe_enable_clock(struct mtk_base_afe * afe)242 int mt8186_afe_enable_clock(struct mtk_base_afe *afe)
243 {
244 struct mt8186_afe_private *afe_priv = afe->platform_priv;
245 int ret = 0;
246
247 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
248 if (ret) {
249 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
250 __func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);
251 goto clk_infra_sys_audio_err;
252 }
253
254 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
255 if (ret) {
256 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
257 __func__, aud_clks[CLK_INFRA_AUDIO_26M], ret);
258 goto clk_infra_audio_26m_err;
259 }
260
261 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
262 if (ret) {
263 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
264 __func__, aud_clks[CLK_MUX_AUDIO], ret);
265 goto clk_mux_audio_err;
266 }
267 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
268 afe_priv->clk[CLK_CLK26M]);
269 if (ret) {
270 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
271 __func__, aud_clks[CLK_MUX_AUDIO],
272 aud_clks[CLK_CLK26M], ret);
273 goto clk_mux_audio_err;
274 }
275
276 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
277 if (ret) {
278 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
279 __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
280 goto clk_mux_audio_intbus_err;
281 }
282 ret = mt8186_set_audio_int_bus_parent(afe,
283 CLK_TOP_MAINPLL_D2_D4);
284 if (ret)
285 goto clk_mux_audio_intbus_parent_err;
286
287 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H],
288 afe_priv->clk[CLK_TOP_APLL2_CK]);
289 if (ret) {
290 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
291 __func__, aud_clks[CLK_TOP_MUX_AUDIO_H],
292 aud_clks[CLK_TOP_APLL2_CK], ret);
293 goto clk_mux_audio_h_parent_err;
294 }
295
296 ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
297 if (ret) {
298 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
299 __func__, aud_clks[CLK_AFE], ret);
300 goto clk_afe_err;
301 }
302
303 return 0;
304
305 clk_afe_err:
306 clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
307 clk_mux_audio_h_parent_err:
308 clk_mux_audio_intbus_parent_err:
309 mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
310 clk_mux_audio_intbus_err:
311 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
312 clk_mux_audio_err:
313 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
314 clk_infra_sys_audio_err:
315 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
316 clk_infra_audio_26m_err:
317 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
318
319 return ret;
320 }
321
mt8186_afe_disable_clock(struct mtk_base_afe * afe)322 void mt8186_afe_disable_clock(struct mtk_base_afe *afe)
323 {
324 struct mt8186_afe_private *afe_priv = afe->platform_priv;
325
326 clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
327 mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
328 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
329 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
330 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
331 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
332 }
333
mt8186_afe_suspend_clock(struct mtk_base_afe * afe)334 int mt8186_afe_suspend_clock(struct mtk_base_afe *afe)
335 {
336 struct mt8186_afe_private *afe_priv = afe->platform_priv;
337 int ret;
338
339 /* set audio int bus to 26M */
340 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
341 if (ret) {
342 dev_info(afe->dev, "%s clk_prepare_enable %s fail %d\n",
343 __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
344 goto clk_mux_audio_intbus_err;
345 }
346 ret = mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
347 if (ret)
348 goto clk_mux_audio_intbus_parent_err;
349
350 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
351
352 return 0;
353
354 clk_mux_audio_intbus_parent_err:
355 mt8186_set_audio_int_bus_parent(afe, CLK_TOP_MAINPLL_D2_D4);
356 clk_mux_audio_intbus_err:
357 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
358 return ret;
359 }
360
mt8186_afe_resume_clock(struct mtk_base_afe * afe)361 int mt8186_afe_resume_clock(struct mtk_base_afe *afe)
362 {
363 struct mt8186_afe_private *afe_priv = afe->platform_priv;
364 int ret;
365
366 /* set audio int bus to normal working clock */
367 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
368 if (ret) {
369 dev_info(afe->dev, "%s clk_prepare_enable %s fail %d\n",
370 __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
371 goto clk_mux_audio_intbus_err;
372 }
373 ret = mt8186_set_audio_int_bus_parent(afe,
374 CLK_TOP_MAINPLL_D2_D4);
375 if (ret)
376 goto clk_mux_audio_intbus_parent_err;
377
378 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
379
380 return 0;
381
382 clk_mux_audio_intbus_parent_err:
383 mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
384 clk_mux_audio_intbus_err:
385 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
386 return ret;
387 }
388
mt8186_apll1_enable(struct mtk_base_afe * afe)389 int mt8186_apll1_enable(struct mtk_base_afe *afe)
390 {
391 struct mt8186_afe_private *afe_priv = afe->platform_priv;
392 int ret;
393
394 /* setting for APLL */
395 apll1_mux_setting(afe, true);
396
397 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
398 if (ret) {
399 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
400 __func__, aud_clks[CLK_APLL22M], ret);
401 goto err_clk_apll22m;
402 }
403
404 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
405 if (ret) {
406 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
407 __func__, aud_clks[CLK_APLL1_TUNER], ret);
408 goto err_clk_apll1_tuner;
409 }
410
411 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0xfff7, 0x832);
412 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1);
413
414 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
415 AFE_22M_ON_MASK_SFT, BIT(AFE_22M_ON_SFT));
416
417 return 0;
418
419 err_clk_apll1_tuner:
420 clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
421 err_clk_apll22m:
422 clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
423
424 return ret;
425 }
426
mt8186_apll1_disable(struct mtk_base_afe * afe)427 void mt8186_apll1_disable(struct mtk_base_afe *afe)
428 {
429 struct mt8186_afe_private *afe_priv = afe->platform_priv;
430
431 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
432 AFE_22M_ON_MASK_SFT, 0);
433
434 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0);
435
436 clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
437 clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
438
439 apll1_mux_setting(afe, false);
440 }
441
mt8186_apll2_enable(struct mtk_base_afe * afe)442 int mt8186_apll2_enable(struct mtk_base_afe *afe)
443 {
444 struct mt8186_afe_private *afe_priv = afe->platform_priv;
445 int ret;
446
447 /* setting for APLL */
448 apll2_mux_setting(afe, true);
449
450 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
451 if (ret) {
452 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
453 __func__, aud_clks[CLK_APLL24M], ret);
454 goto err_clk_apll24m;
455 }
456
457 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
458 if (ret) {
459 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
460 __func__, aud_clks[CLK_APLL2_TUNER], ret);
461 goto err_clk_apll2_tuner;
462 }
463
464 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0xfff7, 0x634);
465 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1);
466
467 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
468 AFE_24M_ON_MASK_SFT, BIT(AFE_24M_ON_SFT));
469
470 return 0;
471
472 err_clk_apll2_tuner:
473 clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
474 err_clk_apll24m:
475 clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
476
477 return ret;
478 }
479
mt8186_apll2_disable(struct mtk_base_afe * afe)480 void mt8186_apll2_disable(struct mtk_base_afe *afe)
481 {
482 struct mt8186_afe_private *afe_priv = afe->platform_priv;
483
484 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
485 AFE_24M_ON_MASK_SFT, 0);
486
487 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0);
488
489 clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
490 clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
491
492 apll2_mux_setting(afe, false);
493 }
494
mt8186_get_apll_rate(struct mtk_base_afe * afe,int apll)495 int mt8186_get_apll_rate(struct mtk_base_afe *afe, int apll)
496 {
497 return (apll == MT8186_APLL1) ? 180633600 : 196608000;
498 }
499
mt8186_get_apll_by_rate(struct mtk_base_afe * afe,int rate)500 int mt8186_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
501 {
502 return ((rate % 8000) == 0) ? MT8186_APLL2 : MT8186_APLL1;
503 }
504
mt8186_get_apll_by_name(struct mtk_base_afe * afe,const char * name)505 int mt8186_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
506 {
507 if (strcmp(name, APLL1_W_NAME) == 0)
508 return MT8186_APLL1;
509
510 return MT8186_APLL2;
511 }
512
513 /* mck */
514 struct mt8186_mck_div {
515 u32 m_sel_id;
516 u32 div_clk_id;
517 };
518
519 static const struct mt8186_mck_div mck_div[MT8186_MCK_NUM] = {
520 [MT8186_I2S0_MCK] = {
521 .m_sel_id = CLK_TOP_I2S0_M_SEL,
522 .div_clk_id = CLK_TOP_APLL12_DIV0,
523 },
524 [MT8186_I2S1_MCK] = {
525 .m_sel_id = CLK_TOP_I2S1_M_SEL,
526 .div_clk_id = CLK_TOP_APLL12_DIV1,
527 },
528 [MT8186_I2S2_MCK] = {
529 .m_sel_id = CLK_TOP_I2S2_M_SEL,
530 .div_clk_id = CLK_TOP_APLL12_DIV2,
531 },
532 [MT8186_I2S4_MCK] = {
533 .m_sel_id = CLK_TOP_I2S4_M_SEL,
534 .div_clk_id = CLK_TOP_APLL12_DIV4,
535 },
536 [MT8186_TDM_MCK] = {
537 .m_sel_id = CLK_TOP_TDM_M_SEL,
538 .div_clk_id = CLK_TOP_APLL12_DIV_TDM,
539 },
540 };
541
mt8186_mck_enable(struct mtk_base_afe * afe,int mck_id,int rate)542 int mt8186_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
543 {
544 struct mt8186_afe_private *afe_priv = afe->platform_priv;
545 int apll = mt8186_get_apll_by_rate(afe, rate);
546 int apll_clk_id = apll == MT8186_APLL1 ?
547 CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2;
548 int m_sel_id = mck_div[mck_id].m_sel_id;
549 int div_clk_id = mck_div[mck_id].div_clk_id;
550 int ret;
551
552 /* select apll */
553 if (m_sel_id >= 0) {
554 ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
555 if (ret) {
556 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
557 __func__, aud_clks[m_sel_id], ret);
558 return ret;
559 }
560 ret = clk_set_parent(afe_priv->clk[m_sel_id],
561 afe_priv->clk[apll_clk_id]);
562 if (ret) {
563 dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
564 __func__, aud_clks[m_sel_id],
565 aud_clks[apll_clk_id], ret);
566 return ret;
567 }
568 }
569
570 /* enable div, set rate */
571 ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
572 if (ret) {
573 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
574 __func__, aud_clks[div_clk_id], ret);
575 return ret;
576 }
577 ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
578 if (ret) {
579 dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",
580 __func__, aud_clks[div_clk_id], rate, ret);
581 return ret;
582 }
583
584 return 0;
585 }
586
mt8186_mck_disable(struct mtk_base_afe * afe,int mck_id)587 void mt8186_mck_disable(struct mtk_base_afe *afe, int mck_id)
588 {
589 struct mt8186_afe_private *afe_priv = afe->platform_priv;
590 int m_sel_id = mck_div[mck_id].m_sel_id;
591 int div_clk_id = mck_div[mck_id].div_clk_id;
592
593 clk_disable_unprepare(afe_priv->clk[div_clk_id]);
594 if (m_sel_id >= 0)
595 clk_disable_unprepare(afe_priv->clk[m_sel_id]);
596 }
597
mt8186_init_clock(struct mtk_base_afe * afe)598 int mt8186_init_clock(struct mtk_base_afe *afe)
599 {
600 struct mt8186_afe_private *afe_priv = afe->platform_priv;
601 struct device_node *of_node = afe->dev->of_node;
602 int i = 0;
603
604 mt8186_audsys_clk_register(afe);
605
606 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
607 GFP_KERNEL);
608 if (!afe_priv->clk)
609 return -ENOMEM;
610
611 for (i = 0; i < CLK_NUM; i++) {
612 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
613 if (IS_ERR(afe_priv->clk[i])) {
614 dev_err(afe->dev, "%s devm_clk_get %s fail, ret %ld\n",
615 __func__,
616 aud_clks[i], PTR_ERR(afe_priv->clk[i]));
617 afe_priv->clk[i] = NULL;
618 }
619 }
620
621 afe_priv->apmixedsys = syscon_regmap_lookup_by_phandle(of_node,
622 "mediatek,apmixedsys");
623 if (IS_ERR(afe_priv->apmixedsys)) {
624 dev_err(afe->dev, "%s() Cannot find apmixedsys controller: %ld\n",
625 __func__, PTR_ERR(afe_priv->apmixedsys));
626 return PTR_ERR(afe_priv->apmixedsys);
627 }
628
629 afe_priv->topckgen = syscon_regmap_lookup_by_phandle(of_node,
630 "mediatek,topckgen");
631 if (IS_ERR(afe_priv->topckgen)) {
632 dev_err(afe->dev, "%s() Cannot find topckgen controller: %ld\n",
633 __func__, PTR_ERR(afe_priv->topckgen));
634 return PTR_ERR(afe_priv->topckgen);
635 }
636
637 afe_priv->infracfg = syscon_regmap_lookup_by_phandle(of_node,
638 "mediatek,infracfg");
639 if (IS_ERR(afe_priv->infracfg)) {
640 dev_err(afe->dev, "%s() Cannot find infracfg: %ld\n",
641 __func__, PTR_ERR(afe_priv->infracfg));
642 return PTR_ERR(afe_priv->infracfg);
643 }
644
645 return 0;
646 }
647
mt8186_deinit_clock(void * priv)648 void mt8186_deinit_clock(void *priv)
649 {
650 struct mtk_base_afe *afe = priv;
651 mt8186_audsys_clk_unregister(afe);
652 }
653
