1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright 2018 NXP
3
4 #include <linux/bitfield.h>
5 #include <linux/clk.h>
6 #include <linux/device.h>
7 #include <linux/interrupt.h>
8 #include <linux/kobject.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/of_irq.h>
14 #include <linux/of_platform.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/sysfs.h>
18 #include <linux/types.h>
19 #include <linux/dma/imx-dma.h>
20 #include <sound/dmaengine_pcm.h>
21 #include <sound/pcm.h>
22 #include <sound/soc.h>
23 #include <sound/tlv.h>
24 #include <sound/core.h>
25
26 #include "fsl_micfil.h"
27 #include "fsl_utils.h"
28
29 #define MICFIL_OSR_DEFAULT 16
30
31 enum quality {
32 QUALITY_HIGH,
33 QUALITY_MEDIUM,
34 QUALITY_LOW,
35 QUALITY_VLOW0,
36 QUALITY_VLOW1,
37 QUALITY_VLOW2,
38 };
39
40 struct fsl_micfil {
41 struct platform_device *pdev;
42 struct regmap *regmap;
43 const struct fsl_micfil_soc_data *soc;
44 struct clk *busclk;
45 struct clk *mclk;
46 struct clk *pll8k_clk;
47 struct clk *pll11k_clk;
48 struct snd_dmaengine_dai_dma_data dma_params_rx;
49 struct sdma_peripheral_config sdmacfg;
50 unsigned int dataline;
51 char name[32];
52 int irq[MICFIL_IRQ_LINES];
53 enum quality quality;
54 int dc_remover;
55 };
56
57 struct fsl_micfil_soc_data {
58 unsigned int fifos;
59 unsigned int fifo_depth;
60 unsigned int dataline;
61 bool imx;
62 u64 formats;
63 };
64
65 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
66 .imx = true,
67 .fifos = 8,
68 .fifo_depth = 8,
69 .dataline = 0xf,
70 .formats = SNDRV_PCM_FMTBIT_S16_LE,
71 };
72
73 static struct fsl_micfil_soc_data fsl_micfil_imx8mp = {
74 .imx = true,
75 .fifos = 8,
76 .fifo_depth = 32,
77 .dataline = 0xf,
78 .formats = SNDRV_PCM_FMTBIT_S32_LE,
79 };
80
81 static const struct of_device_id fsl_micfil_dt_ids[] = {
82 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
83 { .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp },
84 {}
85 };
86 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
87
88 static const char * const micfil_quality_select_texts[] = {
89 [QUALITY_HIGH] = "High",
90 [QUALITY_MEDIUM] = "Medium",
91 [QUALITY_LOW] = "Low",
92 [QUALITY_VLOW0] = "VLow0",
93 [QUALITY_VLOW1] = "Vlow1",
94 [QUALITY_VLOW2] = "Vlow2",
95 };
96
97 static const struct soc_enum fsl_micfil_quality_enum =
98 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts),
99 micfil_quality_select_texts);
100
101 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
102
micfil_set_quality(struct fsl_micfil * micfil)103 static int micfil_set_quality(struct fsl_micfil *micfil)
104 {
105 u32 qsel;
106
107 switch (micfil->quality) {
108 case QUALITY_HIGH:
109 qsel = MICFIL_QSEL_HIGH_QUALITY;
110 break;
111 case QUALITY_MEDIUM:
112 qsel = MICFIL_QSEL_MEDIUM_QUALITY;
113 break;
114 case QUALITY_LOW:
115 qsel = MICFIL_QSEL_LOW_QUALITY;
116 break;
117 case QUALITY_VLOW0:
118 qsel = MICFIL_QSEL_VLOW0_QUALITY;
119 break;
120 case QUALITY_VLOW1:
121 qsel = MICFIL_QSEL_VLOW1_QUALITY;
122 break;
123 case QUALITY_VLOW2:
124 qsel = MICFIL_QSEL_VLOW2_QUALITY;
125 break;
126 }
127
128 return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
129 MICFIL_CTRL2_QSEL,
130 FIELD_PREP(MICFIL_CTRL2_QSEL, qsel));
131 }
132
micfil_quality_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)133 static int micfil_quality_get(struct snd_kcontrol *kcontrol,
134 struct snd_ctl_elem_value *ucontrol)
135 {
136 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
137 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
138
139 ucontrol->value.integer.value[0] = micfil->quality;
140
141 return 0;
142 }
143
micfil_quality_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)144 static int micfil_quality_set(struct snd_kcontrol *kcontrol,
145 struct snd_ctl_elem_value *ucontrol)
146 {
147 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
148 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
149
150 micfil->quality = ucontrol->value.integer.value[0];
151
152 return micfil_set_quality(micfil);
153 }
154
155 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
156 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
157 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv),
158 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
159 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0x7, gain_tlv),
160 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
161 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0x7, gain_tlv),
162 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
163 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0x7, gain_tlv),
164 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
165 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0x7, gain_tlv),
166 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
167 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0x7, gain_tlv),
168 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
169 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0x7, gain_tlv),
170 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
171 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv),
172 SOC_ENUM_EXT("MICFIL Quality Select",
173 fsl_micfil_quality_enum,
174 micfil_quality_get, micfil_quality_set),
175 };
176
177 /* The SRES is a self-negated bit which provides the CPU with the
178 * capability to initialize the PDM Interface module through the
179 * slave-bus interface. This bit always reads as zero, and this
180 * bit is only effective when MDIS is cleared
181 */
fsl_micfil_reset(struct device * dev)182 static int fsl_micfil_reset(struct device *dev)
183 {
184 struct fsl_micfil *micfil = dev_get_drvdata(dev);
185 int ret;
186
187 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
188 MICFIL_CTRL1_MDIS);
189 if (ret)
190 return ret;
191
192 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
193 MICFIL_CTRL1_SRES);
194 if (ret)
195 return ret;
196
197 /*
198 * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined
199 * as non-volatile register, so SRES still remain in regmap
200 * cache after set, that every update of REG_MICFIL_CTRL1,
201 * software reset happens. so clear it explicitly.
202 */
203 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
204 MICFIL_CTRL1_SRES);
205 if (ret)
206 return ret;
207
208 /*
209 * Set SRES should clear CHnF flags, But even add delay here
210 * the CHnF may not be cleared sometimes, so clear CHnF explicitly.
211 */
212 ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF);
213 if (ret)
214 return ret;
215
216 return 0;
217 }
218
fsl_micfil_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)219 static int fsl_micfil_startup(struct snd_pcm_substream *substream,
220 struct snd_soc_dai *dai)
221 {
222 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
223
224 if (!micfil) {
225 dev_err(dai->dev, "micfil dai priv_data not set\n");
226 return -EINVAL;
227 }
228
229 return 0;
230 }
231
fsl_micfil_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)232 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
233 struct snd_soc_dai *dai)
234 {
235 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
236 struct device *dev = &micfil->pdev->dev;
237 int ret;
238
239 switch (cmd) {
240 case SNDRV_PCM_TRIGGER_START:
241 case SNDRV_PCM_TRIGGER_RESUME:
242 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
243 ret = fsl_micfil_reset(dev);
244 if (ret) {
245 dev_err(dev, "failed to soft reset\n");
246 return ret;
247 }
248
249 /* DMA Interrupt Selection - DISEL bits
250 * 00 - DMA and IRQ disabled
251 * 01 - DMA req enabled
252 * 10 - IRQ enabled
253 * 11 - reserved
254 */
255 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
256 MICFIL_CTRL1_DISEL,
257 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
258 if (ret)
259 return ret;
260
261 /* Enable the module */
262 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
263 MICFIL_CTRL1_PDMIEN);
264 if (ret)
265 return ret;
266
267 break;
268 case SNDRV_PCM_TRIGGER_STOP:
269 case SNDRV_PCM_TRIGGER_SUSPEND:
270 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
271 /* Disable the module */
272 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
273 MICFIL_CTRL1_PDMIEN);
274 if (ret)
275 return ret;
276
277 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
278 MICFIL_CTRL1_DISEL,
279 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
280 if (ret)
281 return ret;
282 break;
283 default:
284 return -EINVAL;
285 }
286 return 0;
287 }
288
fsl_micfil_reparent_rootclk(struct fsl_micfil * micfil,unsigned int sample_rate)289 static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate)
290 {
291 struct device *dev = &micfil->pdev->dev;
292 u64 ratio = sample_rate;
293 struct clk *clk;
294 int ret;
295
296 /* Get root clock */
297 clk = micfil->mclk;
298
299 /* Disable clock first, for it was enabled by pm_runtime */
300 clk_disable_unprepare(clk);
301 fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk,
302 micfil->pll11k_clk, ratio);
303 ret = clk_prepare_enable(clk);
304 if (ret)
305 return ret;
306
307 return 0;
308 }
309
fsl_micfil_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)310 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
311 struct snd_pcm_hw_params *params,
312 struct snd_soc_dai *dai)
313 {
314 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
315 unsigned int channels = params_channels(params);
316 unsigned int rate = params_rate(params);
317 int clk_div = 8;
318 int osr = MICFIL_OSR_DEFAULT;
319 int ret;
320
321 /* 1. Disable the module */
322 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
323 MICFIL_CTRL1_PDMIEN);
324 if (ret)
325 return ret;
326
327 /* enable channels */
328 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
329 0xFF, ((1 << channels) - 1));
330 if (ret)
331 return ret;
332
333 ret = fsl_micfil_reparent_rootclk(micfil, rate);
334 if (ret)
335 return ret;
336
337 ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);
338 if (ret)
339 return ret;
340
341 ret = micfil_set_quality(micfil);
342 if (ret)
343 return ret;
344
345 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
346 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
347 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
348 FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
349
350 micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
351 micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
352 micfil->sdmacfg.n_fifos_src = channels;
353 micfil->sdmacfg.sw_done = true;
354 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
355
356 return 0;
357 }
358
359 static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
360 .startup = fsl_micfil_startup,
361 .trigger = fsl_micfil_trigger,
362 .hw_params = fsl_micfil_hw_params,
363 };
364
fsl_micfil_dai_probe(struct snd_soc_dai * cpu_dai)365 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
366 {
367 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
368 struct device *dev = cpu_dai->dev;
369 unsigned int val = 0;
370 int ret, i;
371
372 micfil->quality = QUALITY_VLOW0;
373
374 /* set default gain to 2 */
375 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222);
376
377 /* set DC Remover in bypass mode*/
378 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
379 val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i);
380 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL,
381 MICFIL_DC_CTRL_CONFIG, val);
382 if (ret) {
383 dev_err(dev, "failed to set DC Remover mode bits\n");
384 return ret;
385 }
386 micfil->dc_remover = MICFIL_DC_BYPASS;
387
388 snd_soc_dai_init_dma_data(cpu_dai, NULL,
389 &micfil->dma_params_rx);
390
391 /* FIFO Watermark Control - FIFOWMK*/
392 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
393 MICFIL_FIFO_CTRL_FIFOWMK,
394 FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
395 if (ret)
396 return ret;
397
398 return 0;
399 }
400
401 static struct snd_soc_dai_driver fsl_micfil_dai = {
402 .probe = fsl_micfil_dai_probe,
403 .capture = {
404 .stream_name = "CPU-Capture",
405 .channels_min = 1,
406 .channels_max = 8,
407 .rates = SNDRV_PCM_RATE_8000_48000,
408 .formats = SNDRV_PCM_FMTBIT_S16_LE,
409 },
410 .ops = &fsl_micfil_dai_ops,
411 };
412
413 static const struct snd_soc_component_driver fsl_micfil_component = {
414 .name = "fsl-micfil-dai",
415 .controls = fsl_micfil_snd_controls,
416 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),
417 .legacy_dai_naming = 1,
418 };
419
420 /* REGMAP */
421 static const struct reg_default fsl_micfil_reg_defaults[] = {
422 {REG_MICFIL_CTRL1, 0x00000000},
423 {REG_MICFIL_CTRL2, 0x00000000},
424 {REG_MICFIL_STAT, 0x00000000},
425 {REG_MICFIL_FIFO_CTRL, 0x00000007},
426 {REG_MICFIL_FIFO_STAT, 0x00000000},
427 {REG_MICFIL_DATACH0, 0x00000000},
428 {REG_MICFIL_DATACH1, 0x00000000},
429 {REG_MICFIL_DATACH2, 0x00000000},
430 {REG_MICFIL_DATACH3, 0x00000000},
431 {REG_MICFIL_DATACH4, 0x00000000},
432 {REG_MICFIL_DATACH5, 0x00000000},
433 {REG_MICFIL_DATACH6, 0x00000000},
434 {REG_MICFIL_DATACH7, 0x00000000},
435 {REG_MICFIL_DC_CTRL, 0x00000000},
436 {REG_MICFIL_OUT_CTRL, 0x00000000},
437 {REG_MICFIL_OUT_STAT, 0x00000000},
438 {REG_MICFIL_VAD0_CTRL1, 0x00000000},
439 {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
440 {REG_MICFIL_VAD0_STAT, 0x00000000},
441 {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
442 {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
443 {REG_MICFIL_VAD0_NDATA, 0x00000000},
444 {REG_MICFIL_VAD0_ZCD, 0x00000004},
445 };
446
fsl_micfil_readable_reg(struct device * dev,unsigned int reg)447 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
448 {
449 switch (reg) {
450 case REG_MICFIL_CTRL1:
451 case REG_MICFIL_CTRL2:
452 case REG_MICFIL_STAT:
453 case REG_MICFIL_FIFO_CTRL:
454 case REG_MICFIL_FIFO_STAT:
455 case REG_MICFIL_DATACH0:
456 case REG_MICFIL_DATACH1:
457 case REG_MICFIL_DATACH2:
458 case REG_MICFIL_DATACH3:
459 case REG_MICFIL_DATACH4:
460 case REG_MICFIL_DATACH5:
461 case REG_MICFIL_DATACH6:
462 case REG_MICFIL_DATACH7:
463 case REG_MICFIL_DC_CTRL:
464 case REG_MICFIL_OUT_CTRL:
465 case REG_MICFIL_OUT_STAT:
466 case REG_MICFIL_VAD0_CTRL1:
467 case REG_MICFIL_VAD0_CTRL2:
468 case REG_MICFIL_VAD0_STAT:
469 case REG_MICFIL_VAD0_SCONFIG:
470 case REG_MICFIL_VAD0_NCONFIG:
471 case REG_MICFIL_VAD0_NDATA:
472 case REG_MICFIL_VAD0_ZCD:
473 return true;
474 default:
475 return false;
476 }
477 }
478
fsl_micfil_writeable_reg(struct device * dev,unsigned int reg)479 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
480 {
481 switch (reg) {
482 case REG_MICFIL_CTRL1:
483 case REG_MICFIL_CTRL2:
484 case REG_MICFIL_STAT: /* Write 1 to Clear */
485 case REG_MICFIL_FIFO_CTRL:
486 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
487 case REG_MICFIL_DC_CTRL:
488 case REG_MICFIL_OUT_CTRL:
489 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
490 case REG_MICFIL_VAD0_CTRL1:
491 case REG_MICFIL_VAD0_CTRL2:
492 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
493 case REG_MICFIL_VAD0_SCONFIG:
494 case REG_MICFIL_VAD0_NCONFIG:
495 case REG_MICFIL_VAD0_ZCD:
496 return true;
497 default:
498 return false;
499 }
500 }
501
fsl_micfil_volatile_reg(struct device * dev,unsigned int reg)502 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
503 {
504 switch (reg) {
505 case REG_MICFIL_STAT:
506 case REG_MICFIL_DATACH0:
507 case REG_MICFIL_DATACH1:
508 case REG_MICFIL_DATACH2:
509 case REG_MICFIL_DATACH3:
510 case REG_MICFIL_DATACH4:
511 case REG_MICFIL_DATACH5:
512 case REG_MICFIL_DATACH6:
513 case REG_MICFIL_DATACH7:
514 case REG_MICFIL_VAD0_STAT:
515 case REG_MICFIL_VAD0_NDATA:
516 return true;
517 default:
518 return false;
519 }
520 }
521
522 static const struct regmap_config fsl_micfil_regmap_config = {
523 .reg_bits = 32,
524 .reg_stride = 4,
525 .val_bits = 32,
526
527 .max_register = REG_MICFIL_VAD0_ZCD,
528 .reg_defaults = fsl_micfil_reg_defaults,
529 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
530 .readable_reg = fsl_micfil_readable_reg,
531 .volatile_reg = fsl_micfil_volatile_reg,
532 .writeable_reg = fsl_micfil_writeable_reg,
533 .cache_type = REGCACHE_RBTREE,
534 };
535
536 /* END OF REGMAP */
537
micfil_isr(int irq,void * devid)538 static irqreturn_t micfil_isr(int irq, void *devid)
539 {
540 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
541 struct platform_device *pdev = micfil->pdev;
542 u32 stat_reg;
543 u32 fifo_stat_reg;
544 u32 ctrl1_reg;
545 bool dma_enabled;
546 int i;
547
548 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
549 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
550 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
551
552 dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;
553
554 /* Channel 0-7 Output Data Flags */
555 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
556 if (stat_reg & MICFIL_STAT_CHXF(i))
557 dev_dbg(&pdev->dev,
558 "Data available in Data Channel %d\n", i);
559 /* if DMA is not enabled, field must be written with 1
560 * to clear
561 */
562 if (!dma_enabled)
563 regmap_write_bits(micfil->regmap,
564 REG_MICFIL_STAT,
565 MICFIL_STAT_CHXF(i),
566 1);
567 }
568
569 for (i = 0; i < MICFIL_FIFO_NUM; i++) {
570 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))
571 dev_dbg(&pdev->dev,
572 "FIFO Overflow Exception flag for channel %d\n",
573 i);
574
575 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))
576 dev_dbg(&pdev->dev,
577 "FIFO Underflow Exception flag for channel %d\n",
578 i);
579 }
580
581 return IRQ_HANDLED;
582 }
583
micfil_err_isr(int irq,void * devid)584 static irqreturn_t micfil_err_isr(int irq, void *devid)
585 {
586 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
587 struct platform_device *pdev = micfil->pdev;
588 u32 stat_reg;
589
590 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
591
592 if (stat_reg & MICFIL_STAT_BSY_FIL)
593 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
594
595 if (stat_reg & MICFIL_STAT_FIR_RDY)
596 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
597
598 if (stat_reg & MICFIL_STAT_LOWFREQF) {
599 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
600 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
601 MICFIL_STAT_LOWFREQF, 1);
602 }
603
604 return IRQ_HANDLED;
605 }
606
fsl_micfil_probe(struct platform_device * pdev)607 static int fsl_micfil_probe(struct platform_device *pdev)
608 {
609 struct device_node *np = pdev->dev.of_node;
610 struct fsl_micfil *micfil;
611 struct resource *res;
612 void __iomem *regs;
613 int ret, i;
614
615 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
616 if (!micfil)
617 return -ENOMEM;
618
619 micfil->pdev = pdev;
620 strncpy(micfil->name, np->name, sizeof(micfil->name) - 1);
621
622 micfil->soc = of_device_get_match_data(&pdev->dev);
623
624 /* ipg_clk is used to control the registers
625 * ipg_clk_app is used to operate the filter
626 */
627 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
628 if (IS_ERR(micfil->mclk)) {
629 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
630 PTR_ERR(micfil->mclk));
631 return PTR_ERR(micfil->mclk);
632 }
633
634 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk");
635 if (IS_ERR(micfil->busclk)) {
636 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n",
637 PTR_ERR(micfil->busclk));
638 return PTR_ERR(micfil->busclk);
639 }
640
641 fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk,
642 &micfil->pll11k_clk);
643
644 /* init regmap */
645 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
646 if (IS_ERR(regs))
647 return PTR_ERR(regs);
648
649 micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
650 regs,
651 &fsl_micfil_regmap_config);
652 if (IS_ERR(micfil->regmap)) {
653 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
654 PTR_ERR(micfil->regmap));
655 return PTR_ERR(micfil->regmap);
656 }
657
658 /* dataline mask for RX */
659 ret = of_property_read_u32_index(np,
660 "fsl,dataline",
661 0,
662 &micfil->dataline);
663 if (ret)
664 micfil->dataline = 1;
665
666 if (micfil->dataline & ~micfil->soc->dataline) {
667 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
668 micfil->soc->dataline);
669 return -EINVAL;
670 }
671
672 /* get IRQs */
673 for (i = 0; i < MICFIL_IRQ_LINES; i++) {
674 micfil->irq[i] = platform_get_irq(pdev, i);
675 if (micfil->irq[i] < 0)
676 return micfil->irq[i];
677 }
678
679 /* Digital Microphone interface interrupt */
680 ret = devm_request_irq(&pdev->dev, micfil->irq[0],
681 micfil_isr, IRQF_SHARED,
682 micfil->name, micfil);
683 if (ret) {
684 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
685 micfil->irq[0]);
686 return ret;
687 }
688
689 /* Digital Microphone interface error interrupt */
690 ret = devm_request_irq(&pdev->dev, micfil->irq[1],
691 micfil_err_isr, IRQF_SHARED,
692 micfil->name, micfil);
693 if (ret) {
694 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
695 micfil->irq[1]);
696 return ret;
697 }
698
699 micfil->dma_params_rx.chan_name = "rx";
700 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
701 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
702
703 platform_set_drvdata(pdev, micfil);
704
705 pm_runtime_enable(&pdev->dev);
706 regcache_cache_only(micfil->regmap, true);
707
708 /*
709 * Register platform component before registering cpu dai for there
710 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
711 */
712 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
713 if (ret) {
714 dev_err(&pdev->dev, "failed to pcm register\n");
715 return ret;
716 }
717
718 fsl_micfil_dai.capture.formats = micfil->soc->formats;
719
720 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
721 &fsl_micfil_dai, 1);
722 if (ret) {
723 dev_err(&pdev->dev, "failed to register component %s\n",
724 fsl_micfil_component.name);
725 }
726
727 return ret;
728 }
729
fsl_micfil_runtime_suspend(struct device * dev)730 static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev)
731 {
732 struct fsl_micfil *micfil = dev_get_drvdata(dev);
733
734 regcache_cache_only(micfil->regmap, true);
735
736 clk_disable_unprepare(micfil->mclk);
737 clk_disable_unprepare(micfil->busclk);
738
739 return 0;
740 }
741
fsl_micfil_runtime_resume(struct device * dev)742 static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev)
743 {
744 struct fsl_micfil *micfil = dev_get_drvdata(dev);
745 int ret;
746
747 ret = clk_prepare_enable(micfil->busclk);
748 if (ret < 0)
749 return ret;
750
751 ret = clk_prepare_enable(micfil->mclk);
752 if (ret < 0) {
753 clk_disable_unprepare(micfil->busclk);
754 return ret;
755 }
756
757 regcache_cache_only(micfil->regmap, false);
758 regcache_mark_dirty(micfil->regmap);
759 regcache_sync(micfil->regmap);
760
761 return 0;
762 }
763
fsl_micfil_suspend(struct device * dev)764 static int __maybe_unused fsl_micfil_suspend(struct device *dev)
765 {
766 pm_runtime_force_suspend(dev);
767
768 return 0;
769 }
770
fsl_micfil_resume(struct device * dev)771 static int __maybe_unused fsl_micfil_resume(struct device *dev)
772 {
773 pm_runtime_force_resume(dev);
774
775 return 0;
776 }
777
778 static const struct dev_pm_ops fsl_micfil_pm_ops = {
779 SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
780 fsl_micfil_runtime_resume,
781 NULL)
782 SET_SYSTEM_SLEEP_PM_OPS(fsl_micfil_suspend,
783 fsl_micfil_resume)
784 };
785
786 static struct platform_driver fsl_micfil_driver = {
787 .probe = fsl_micfil_probe,
788 .driver = {
789 .name = "fsl-micfil-dai",
790 .pm = &fsl_micfil_pm_ops,
791 .of_match_table = fsl_micfil_dt_ids,
792 },
793 };
794 module_platform_driver(fsl_micfil_driver);
795
796 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
797 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
798 MODULE_LICENSE("GPL v2");
799
