1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board
4 *
5 * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
6 *
7 * Author: Horatiu Vultur <horatiu.vultur@microchip.com>
8 */
9/dts-v1/;
10#include "lan966x.dtsi"
11#include "dt-bindings/phy/phy-lan966x-serdes.h"
12
13/ {
14	model = "Microchip EVB LAN9668";
15	compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966";
16
17	gpio-restart {
18		compatible = "gpio-restart";
19		gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
20		priority = <200>;
21	};
22};
23
24&aes {
25	status = "disabled"; /* Reserved by secure OS */
26};
27
28&gpio {
29	miim_a_pins: mdio-pins {
30		/* MDC, MDIO */
31		pins =  "GPIO_28", "GPIO_29";
32		function = "miim_a";
33	};
34
35	pps_out_pins: pps-out-pins {
36		/* 1pps output */
37		pins = "GPIO_38";
38		function = "ptpsync_3";
39	};
40
41	ptp_ext_pins: ptp-ext-pins {
42		/* 1pps input */
43		pins = "GPIO_35";
44		function = "ptpsync_0";
45	};
46
47	udc_pins: ucd-pins {
48		/* VBUS_DET B */
49		pins = "GPIO_8";
50		function = "usb_slave_b";
51	};
52};
53
54&mdio0 {
55	pinctrl-0 = <&miim_a_pins>;
56	pinctrl-names = "default";
57	status = "okay";
58
59	ext_phy0: ethernet-phy@7 {
60		reg = <7>;
61		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
62	};
63
64	ext_phy1: ethernet-phy@8 {
65		reg = <8>;
66		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
67	};
68
69	ext_phy2: ethernet-phy@9 {
70		reg = <9>;
71		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
72	};
73
74	ext_phy3: ethernet-phy@10 {
75		reg = <10>;
76		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
77	};
78
79	ext_phy4: ethernet-phy@15 {
80		reg = <15>;
81		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
82	};
83
84	ext_phy5: ethernet-phy@16 {
85		reg = <16>;
86		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
87	};
88
89	ext_phy6: ethernet-phy@17 {
90		reg = <17>;
91		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
92	};
93
94	ext_phy7: ethernet-phy@18 {
95		reg = <18>;
96		coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
97	};
98};
99
100&port0 {
101	reg = <2>;
102	phy-handle = <&ext_phy2>;
103	phy-mode = "qsgmii";
104	phys = <&serdes 0 SERDES6G(1)>;
105	status = "okay";
106};
107
108&port1 {
109	reg = <3>;
110	phy-handle = <&ext_phy3>;
111	phy-mode = "qsgmii";
112	phys = <&serdes 1 SERDES6G(1)>;
113	status = "okay";
114};
115
116&port2 {
117	reg = <0>;
118	phy-handle = <&ext_phy0>;
119	phy-mode = "qsgmii";
120	phys = <&serdes 2 SERDES6G(1)>;
121	status = "okay";
122};
123
124&port3 {
125	reg = <1>;
126	phy-handle = <&ext_phy1>;
127	phy-mode = "qsgmii";
128	phys = <&serdes 3 SERDES6G(1)>;
129	status = "okay";
130};
131
132&port4 {
133	reg = <6>;
134	phy-handle = <&ext_phy6>;
135	phy-mode = "qsgmii";
136	phys = <&serdes 4 SERDES6G(2)>;
137	status = "okay";
138};
139
140&port5 {
141	reg = <7>;
142	phy-handle = <&ext_phy7>;
143	phy-mode = "qsgmii";
144	phys = <&serdes 5 SERDES6G(2)>;
145	status = "okay";
146};
147
148&port6 {
149	reg = <4>;
150	phy-handle = <&ext_phy4>;
151	phy-mode = "qsgmii";
152	phys = <&serdes 6 SERDES6G(2)>;
153	status = "okay";
154};
155
156&port7 {
157	reg = <5>;
158	phy-handle = <&ext_phy5>;
159	phy-mode = "qsgmii";
160	phys = <&serdes 7 SERDES6G(2)>;
161	status = "okay";
162};
163
164&serdes {
165	status = "okay";
166};
167
168&switch {
169	pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>;
170	pinctrl-names = "default";
171	status = "okay";
172};
173
174&udc {
175	pinctrl-0 = <&udc_pins>;
176	pinctrl-names = "default";
177	atmel,vbus-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
178	status = "okay";
179};
180