1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree file for the Turris Omnia
4 *
5 * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
6 * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
7 *
8 * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
9 */
10
11/dts-v1/;
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/leds/common.h>
16#include "armada-385.dtsi"
17
18/ {
19	model = "Turris Omnia";
20	compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
21
22	chosen {
23		stdout-path = &uart0;
24	};
25
26	memory {
27		device_type = "memory";
28		reg = <0x00000000 0x40000000>; /* 1024 MB */
29	};
30
31	soc {
32		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
33			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
34			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
35			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
36			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
37
38		internal-regs {
39
40			/* USB part of the PCIe2/USB 2.0 port */
41			usb@58000 {
42				status = "okay";
43			};
44
45			sata@a8000 {
46				status = "okay";
47			};
48
49			sdhci@d8000 {
50				pinctrl-names = "default";
51				pinctrl-0 = <&sdhci_pins>;
52				status = "okay";
53
54				bus-width = <8>;
55				no-1-8-v;
56				non-removable;
57			};
58
59			usb3@f0000 {
60				status = "okay";
61			};
62
63			usb3@f8000 {
64				status = "okay";
65			};
66		};
67
68		pcie {
69			status = "okay";
70
71			pcie@1,0 {
72				/* Port 0, Lane 0 */
73				status = "okay";
74				slot-power-limit-milliwatt = <10000>;
75			};
76
77			pcie@2,0 {
78				/* Port 1, Lane 0 */
79				status = "okay";
80				slot-power-limit-milliwatt = <10000>;
81			};
82
83			pcie@3,0 {
84				/* Port 2, Lane 0 */
85				status = "okay";
86				slot-power-limit-milliwatt = <10000>;
87			};
88		};
89	};
90
91	sfp: sfp {
92		compatible = "sff,sfp";
93		i2c-bus = <&sfp_i2c>;
94		tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>;
95		tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>;
96		rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>;
97		los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>;
98		mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>;
99		maximum-power-milliwatt = <3000>;
100
101		/*
102		 * For now this has to be enabled at boot time by U-Boot when
103		 * a SFP module is present. Read more in the comment in the
104		 * eth2 node below.
105		 */
106		status = "disabled";
107	};
108
109	sound {
110		compatible = "simple-audio-card";
111		simple-audio-card,name = "SPDIF";
112		simple-audio-card,format = "i2s";
113
114		simple-audio-card,cpu {
115			sound-dai = <&audio_controller 1>;
116		};
117
118		simple-audio-card,codec {
119			sound-dai = <&spdif_out>;
120		};
121	};
122
123	spdif_out: spdif-out {
124		#sound-dai-cells = <0>;
125		compatible = "linux,spdif-dit";
126	};
127};
128
129&audio_controller {
130	/* Pin header U16, GPIO51 in SPDIFO mode */
131	pinctrl-0 = <&spdif_pins>;
132	pinctrl-names = "default";
133	spdif-mode;
134	status = "okay";
135};
136
137&bm {
138	status = "okay";
139};
140
141&bm_bppi {
142	status = "okay";
143};
144
145/* Connected to 88E6176 switch, port 6 */
146&eth0 {
147	pinctrl-names = "default";
148	pinctrl-0 = <&ge0_rgmii_pins>;
149	status = "okay";
150	phy-mode = "rgmii";
151	buffer-manager = <&bm>;
152	bm,pool-long = <0>;
153	bm,pool-short = <3>;
154
155	fixed-link {
156		speed = <1000>;
157		full-duplex;
158	};
159};
160
161/* Connected to 88E6176 switch, port 5 */
162&eth1 {
163	pinctrl-names = "default";
164	pinctrl-0 = <&ge1_rgmii_pins>;
165	status = "okay";
166	phy-mode = "rgmii";
167	buffer-manager = <&bm>;
168	bm,pool-long = <1>;
169	bm,pool-short = <3>;
170
171	fixed-link {
172		speed = <1000>;
173		full-duplex;
174	};
175};
176
177/* WAN port */
178&eth2 {
179	/*
180	 * eth2 is connected via a multiplexor to both the SFP cage and to
181	 * ethernet-phy@1. The multiplexor switches the signal to SFP cage when
182	 * a SFP module is present, as determined by the mode-def0 GPIO.
183	 *
184	 * Until kernel supports this configuration properly, in case SFP module
185	 * is present, U-Boot has to enable the sfp node above, remove phy
186	 * handle and add managed = "in-band-status" property.
187	 */
188	status = "okay";
189	phy-mode = "sgmii";
190	phy-handle = <&phy1>;
191	phys = <&comphy5 2>;
192	sfp = <&sfp>;
193	buffer-manager = <&bm>;
194	bm,pool-long = <2>;
195	bm,pool-short = <3>;
196	label = "wan";
197};
198
199&i2c0 {
200	pinctrl-names = "default";
201	pinctrl-0 = <&i2c0_pins>;
202	status = "okay";
203
204	i2cmux@70 {
205		compatible = "nxp,pca9547";
206		#address-cells = <1>;
207		#size-cells = <0>;
208		reg = <0x70>;
209
210		i2c@0 {
211			#address-cells = <1>;
212			#size-cells = <0>;
213			reg = <0>;
214
215			/* STM32F0 command interface at address 0x2a */
216
217			led-controller@2b {
218				compatible = "cznic,turris-omnia-leds";
219				reg = <0x2b>;
220				#address-cells = <1>;
221				#size-cells = <0>;
222				status = "okay";
223
224				/*
225				 * LEDs are controlled by MCU (STM32F0) at
226				 * address 0x2b.
227				 *
228				 * LED functions are not stable yet:
229				 * - there are 3 LEDs connected via MCU to PCIe
230				 *   ports. One of these ports supports mSATA.
231				 *   There is no mSATA nor PCIe function.
232				 *   For now we use LED_FUNCTION_WLAN, since
233				 *   in most cases users have wifi cards in
234				 *   these slots
235				 * - there are 2 LEDs dedicated for user: A and
236				 *   B. Again there is no such function defined.
237				 *   For now we use LED_FUNCTION_INDICATOR
238				 */
239
240				multi-led@0 {
241					reg = <0x0>;
242					color = <LED_COLOR_ID_RGB>;
243					function = LED_FUNCTION_INDICATOR;
244					function-enumerator = <2>;
245				};
246
247				multi-led@1 {
248					reg = <0x1>;
249					color = <LED_COLOR_ID_RGB>;
250					function = LED_FUNCTION_INDICATOR;
251					function-enumerator = <1>;
252				};
253
254				multi-led@2 {
255					reg = <0x2>;
256					color = <LED_COLOR_ID_RGB>;
257					function = LED_FUNCTION_WLAN;
258					function-enumerator = <3>;
259				};
260
261				multi-led@3 {
262					reg = <0x3>;
263					color = <LED_COLOR_ID_RGB>;
264					function = LED_FUNCTION_WLAN;
265					function-enumerator = <2>;
266				};
267
268				multi-led@4 {
269					reg = <0x4>;
270					color = <LED_COLOR_ID_RGB>;
271					function = LED_FUNCTION_WLAN;
272					function-enumerator = <1>;
273				};
274
275				multi-led@5 {
276					reg = <0x5>;
277					color = <LED_COLOR_ID_RGB>;
278					function = LED_FUNCTION_WAN;
279				};
280
281				multi-led@6 {
282					reg = <0x6>;
283					color = <LED_COLOR_ID_RGB>;
284					function = LED_FUNCTION_LAN;
285					function-enumerator = <4>;
286				};
287
288				multi-led@7 {
289					reg = <0x7>;
290					color = <LED_COLOR_ID_RGB>;
291					function = LED_FUNCTION_LAN;
292					function-enumerator = <3>;
293				};
294
295				multi-led@8 {
296					reg = <0x8>;
297					color = <LED_COLOR_ID_RGB>;
298					function = LED_FUNCTION_LAN;
299					function-enumerator = <2>;
300				};
301
302				multi-led@9 {
303					reg = <0x9>;
304					color = <LED_COLOR_ID_RGB>;
305					function = LED_FUNCTION_LAN;
306					function-enumerator = <1>;
307				};
308
309				multi-led@a {
310					reg = <0xa>;
311					color = <LED_COLOR_ID_RGB>;
312					function = LED_FUNCTION_LAN;
313					function-enumerator = <0>;
314				};
315
316				multi-led@b {
317					reg = <0xb>;
318					color = <LED_COLOR_ID_RGB>;
319					function = LED_FUNCTION_POWER;
320				};
321			};
322
323			eeprom@54 {
324				compatible = "atmel,24c64";
325				reg = <0x54>;
326
327				/* The EEPROM contains data for bootloader.
328				 * Contents:
329				 * 	struct omnia_eeprom {
330				 * 		u32 magic; (=0x0341a034 in LE)
331				 *		u32 ramsize; (in GiB)
332				 * 		char regdomain[4];
333				 * 		u32 crc32;
334				 * 	};
335				 */
336			};
337		};
338
339		i2c@1 {
340			#address-cells = <1>;
341			#size-cells = <0>;
342			reg = <1>;
343
344			/* routed to PCIe0/mSATA connector (CN7A) */
345		};
346
347		i2c@2 {
348			#address-cells = <1>;
349			#size-cells = <0>;
350			reg = <2>;
351
352			/* routed to PCIe1/USB2 connector (CN61A) */
353		};
354
355		i2c@3 {
356			#address-cells = <1>;
357			#size-cells = <0>;
358			reg = <3>;
359
360			/* routed to PCIe2 connector (CN62A) */
361		};
362
363		sfp_i2c: i2c@4 {
364			#address-cells = <1>;
365			#size-cells = <0>;
366			reg = <4>;
367
368			/* routed to SFP+ */
369		};
370
371		i2c@5 {
372			#address-cells = <1>;
373			#size-cells = <0>;
374			reg = <5>;
375
376			/* ATSHA204A-MAHDA-T crypto module */
377			crypto@64 {
378				compatible = "atmel,atsha204a";
379				reg = <0x64>;
380			};
381		};
382
383		i2c@6 {
384			#address-cells = <1>;
385			#size-cells = <0>;
386			reg = <6>;
387
388			/* exposed on pin header */
389		};
390
391		i2c@7 {
392			#address-cells = <1>;
393			#size-cells = <0>;
394			reg = <7>;
395
396			pcawan: gpio@71 {
397				/*
398				 * GPIO expander for SFP+ signals and
399				 * and phy irq
400				 */
401				compatible = "nxp,pca9538";
402				reg = <0x71>;
403
404				pinctrl-names = "default";
405				pinctrl-0 = <&pcawan_pins>;
406
407				interrupt-parent = <&gpio1>;
408				interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
409
410				gpio-controller;
411				#gpio-cells = <2>;
412			};
413		};
414	};
415};
416
417&mdio {
418	pinctrl-names = "default";
419	pinctrl-0 = <&mdio_pins>;
420	status = "okay";
421
422	phy1: ethernet-phy@1 {
423		compatible = "ethernet-phy-ieee802.3-c22";
424		reg = <1>;
425		marvell,reg-init = <3 18 0 0x4985>,
426				   <3 16 0xfff0 0x0001>;
427
428		/* irq is connected to &pcawan pin 7 */
429	};
430
431	/* Switch MV88E6176 at address 0x10 */
432	switch@10 {
433		pinctrl-names = "default";
434		pinctrl-0 = <&swint_pins>;
435		compatible = "marvell,mv88e6085";
436		#address-cells = <1>;
437		#size-cells = <0>;
438
439		dsa,member = <0 0>;
440		reg = <0x10>;
441
442		interrupt-parent = <&gpio1>;
443		interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
444
445		ports {
446			#address-cells = <1>;
447			#size-cells = <0>;
448
449			ports@0 {
450				reg = <0>;
451				label = "lan0";
452			};
453
454			ports@1 {
455				reg = <1>;
456				label = "lan1";
457			};
458
459			ports@2 {
460				reg = <2>;
461				label = "lan2";
462			};
463
464			ports@3 {
465				reg = <3>;
466				label = "lan3";
467			};
468
469			ports@4 {
470				reg = <4>;
471				label = "lan4";
472			};
473
474			ports@5 {
475				reg = <5>;
476				label = "cpu";
477				ethernet = <&eth1>;
478				phy-mode = "rgmii-id";
479
480				fixed-link {
481					speed = <1000>;
482					full-duplex;
483				};
484			};
485
486			/* port 6 is connected to eth0 */
487		};
488	};
489};
490
491&pinctrl {
492	pcawan_pins: pcawan-pins {
493		marvell,pins = "mpp46";
494		marvell,function = "gpio";
495	};
496
497	swint_pins: swint-pins {
498		marvell,pins = "mpp45";
499		marvell,function = "gpio";
500	};
501
502	spi0cs0_pins: spi0cs0-pins {
503		marvell,pins = "mpp25";
504		marvell,function = "spi0";
505	};
506
507	spi0cs2_pins: spi0cs2-pins {
508		marvell,pins = "mpp26";
509		marvell,function = "spi0";
510	};
511};
512
513&spi0 {
514	pinctrl-names = "default";
515	pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
516	status = "okay";
517
518	flash@0 {
519		compatible = "spansion,s25fl164k", "jedec,spi-nor";
520		#address-cells = <1>;
521		#size-cells = <1>;
522		reg = <0>;
523		spi-max-frequency = <40000000>;
524
525		partitions {
526			compatible = "fixed-partitions";
527			#address-cells = <1>;
528			#size-cells = <1>;
529
530			partition@0 {
531				reg = <0x0 0x00100000>;
532				label = "U-Boot";
533			};
534
535			partition@100000 {
536				reg = <0x00100000 0x00700000>;
537				label = "Rescue system";
538			};
539		};
540	};
541
542	/* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
543};
544
545&uart0 {
546	/* Pin header CN10 */
547	pinctrl-names = "default";
548	pinctrl-0 = <&uart0_pins>;
549	status = "okay";
550};
551
552&uart1 {
553	/* Pin header CN11 */
554	pinctrl-names = "default";
555	pinctrl-0 = <&uart1_pins>;
556	status = "okay";
557};
558