1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RZ/G2L WDT Watchdog Driver
4 *
5 * Copyright (C) 2021 Renesas Electronics Corporation
6 */
7 #include <linux/bitops.h>
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/io.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/reset.h>
17 #include <linux/units.h>
18 #include <linux/watchdog.h>
19
20 #define WDTCNT 0x00
21 #define WDTSET 0x04
22 #define WDTTIM 0x08
23 #define WDTINT 0x0C
24 #define PECR 0x10
25 #define PEEN 0x14
26 #define WDTCNT_WDTEN BIT(0)
27 #define WDTINT_INTDISP BIT(0)
28 #define PEEN_FORCE BIT(0)
29
30 #define WDT_DEFAULT_TIMEOUT 60U
31
32 /* Setting period time register only 12 bit set in WDTSET[31:20] */
33 #define WDTSET_COUNTER_MASK (0xFFF00000)
34 #define WDTSET_COUNTER_VAL(f) ((f) << 20)
35
36 #define F2CYCLE_NSEC(f) (1000000000 / (f))
37
38 static bool nowayout = WATCHDOG_NOWAYOUT;
39 module_param(nowayout, bool, 0);
40 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
41 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
42
43 enum rz_wdt_type {
44 WDT_RZG2L,
45 WDT_RZV2M,
46 };
47
48 struct rzg2l_wdt_priv {
49 void __iomem *base;
50 struct watchdog_device wdev;
51 struct reset_control *rstc;
52 unsigned long osc_clk_rate;
53 unsigned long delay;
54 struct clk *pclk;
55 struct clk *osc_clk;
56 enum rz_wdt_type devtype;
57 };
58
rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv * priv)59 static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv)
60 {
61 /* delay timer when change the setting register */
62 ndelay(priv->delay);
63 }
64
rzg2l_wdt_get_cycle_usec(unsigned long cycle,u32 wdttime)65 static u32 rzg2l_wdt_get_cycle_usec(unsigned long cycle, u32 wdttime)
66 {
67 u64 timer_cycle_us = 1024 * 1024ULL * (wdttime + 1) * MICRO;
68
69 return div64_ul(timer_cycle_us, cycle);
70 }
71
rzg2l_wdt_write(struct rzg2l_wdt_priv * priv,u32 val,unsigned int reg)72 static void rzg2l_wdt_write(struct rzg2l_wdt_priv *priv, u32 val, unsigned int reg)
73 {
74 if (reg == WDTSET)
75 val &= WDTSET_COUNTER_MASK;
76
77 writel_relaxed(val, priv->base + reg);
78 /* Registers other than the WDTINT is always synchronized with WDT_CLK */
79 if (reg != WDTINT)
80 rzg2l_wdt_wait_delay(priv);
81 }
82
rzg2l_wdt_init_timeout(struct watchdog_device * wdev)83 static void rzg2l_wdt_init_timeout(struct watchdog_device *wdev)
84 {
85 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
86 u32 time_out;
87
88 /* Clear Lapsed Time Register and clear Interrupt */
89 rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
90 /* 2 consecutive overflow cycle needed to trigger reset */
91 time_out = (wdev->timeout * (MICRO / 2)) /
92 rzg2l_wdt_get_cycle_usec(priv->osc_clk_rate, 0);
93 rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(time_out), WDTSET);
94 }
95
rzg2l_wdt_start(struct watchdog_device * wdev)96 static int rzg2l_wdt_start(struct watchdog_device *wdev)
97 {
98 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
99
100 pm_runtime_get_sync(wdev->parent);
101
102 /* Initialize time out */
103 rzg2l_wdt_init_timeout(wdev);
104
105 /* Initialize watchdog counter register */
106 rzg2l_wdt_write(priv, 0, WDTTIM);
107
108 /* Enable watchdog timer*/
109 rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
110
111 return 0;
112 }
113
rzg2l_wdt_stop(struct watchdog_device * wdev)114 static int rzg2l_wdt_stop(struct watchdog_device *wdev)
115 {
116 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
117
118 pm_runtime_put(wdev->parent);
119 reset_control_reset(priv->rstc);
120
121 return 0;
122 }
123
rzg2l_wdt_set_timeout(struct watchdog_device * wdev,unsigned int timeout)124 static int rzg2l_wdt_set_timeout(struct watchdog_device *wdev, unsigned int timeout)
125 {
126 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
127
128 wdev->timeout = timeout;
129
130 /*
131 * If the watchdog is active, reset the module for updating the WDTSET
132 * register so that it is updated with new timeout values.
133 */
134 if (watchdog_active(wdev)) {
135 pm_runtime_put(wdev->parent);
136 reset_control_reset(priv->rstc);
137 rzg2l_wdt_start(wdev);
138 }
139
140 return 0;
141 }
142
rzg2l_wdt_restart(struct watchdog_device * wdev,unsigned long action,void * data)143 static int rzg2l_wdt_restart(struct watchdog_device *wdev,
144 unsigned long action, void *data)
145 {
146 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
147
148 clk_prepare_enable(priv->pclk);
149 clk_prepare_enable(priv->osc_clk);
150
151 if (priv->devtype == WDT_RZG2L) {
152 /* Generate Reset (WDTRSTB) Signal on parity error */
153 rzg2l_wdt_write(priv, 0, PECR);
154
155 /* Force parity error */
156 rzg2l_wdt_write(priv, PEEN_FORCE, PEEN);
157 } else {
158 /* RZ/V2M doesn't have parity error registers */
159
160 wdev->timeout = 0;
161
162 /* Initialize time out */
163 rzg2l_wdt_init_timeout(wdev);
164
165 /* Initialize watchdog counter register */
166 rzg2l_wdt_write(priv, 0, WDTTIM);
167
168 /* Enable watchdog timer*/
169 rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
170
171 /* Wait 2 consecutive overflow cycles for reset */
172 mdelay(DIV_ROUND_UP(2 * 0xFFFFF * 1000, priv->osc_clk_rate));
173 }
174
175 return 0;
176 }
177
178 static const struct watchdog_info rzg2l_wdt_ident = {
179 .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
180 .identity = "Renesas RZ/G2L WDT Watchdog",
181 };
182
rzg2l_wdt_ping(struct watchdog_device * wdev)183 static int rzg2l_wdt_ping(struct watchdog_device *wdev)
184 {
185 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
186
187 rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
188
189 return 0;
190 }
191
192 static const struct watchdog_ops rzg2l_wdt_ops = {
193 .owner = THIS_MODULE,
194 .start = rzg2l_wdt_start,
195 .stop = rzg2l_wdt_stop,
196 .ping = rzg2l_wdt_ping,
197 .set_timeout = rzg2l_wdt_set_timeout,
198 .restart = rzg2l_wdt_restart,
199 };
200
rzg2l_wdt_reset_assert_pm_disable(void * data)201 static void rzg2l_wdt_reset_assert_pm_disable(void *data)
202 {
203 struct watchdog_device *wdev = data;
204 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
205
206 pm_runtime_disable(wdev->parent);
207 reset_control_assert(priv->rstc);
208 }
209
rzg2l_wdt_probe(struct platform_device * pdev)210 static int rzg2l_wdt_probe(struct platform_device *pdev)
211 {
212 struct device *dev = &pdev->dev;
213 struct rzg2l_wdt_priv *priv;
214 unsigned long pclk_rate;
215 int ret;
216
217 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
218 if (!priv)
219 return -ENOMEM;
220
221 priv->base = devm_platform_ioremap_resource(pdev, 0);
222 if (IS_ERR(priv->base))
223 return PTR_ERR(priv->base);
224
225 /* Get watchdog main clock */
226 priv->osc_clk = devm_clk_get(&pdev->dev, "oscclk");
227 if (IS_ERR(priv->osc_clk))
228 return dev_err_probe(&pdev->dev, PTR_ERR(priv->osc_clk), "no oscclk");
229
230 priv->osc_clk_rate = clk_get_rate(priv->osc_clk);
231 if (!priv->osc_clk_rate)
232 return dev_err_probe(&pdev->dev, -EINVAL, "oscclk rate is 0");
233
234 /* Get Peripheral clock */
235 priv->pclk = devm_clk_get(&pdev->dev, "pclk");
236 if (IS_ERR(priv->pclk))
237 return dev_err_probe(&pdev->dev, PTR_ERR(priv->pclk), "no pclk");
238
239 pclk_rate = clk_get_rate(priv->pclk);
240 if (!pclk_rate)
241 return dev_err_probe(&pdev->dev, -EINVAL, "pclk rate is 0");
242
243 priv->delay = F2CYCLE_NSEC(priv->osc_clk_rate) * 6 + F2CYCLE_NSEC(pclk_rate) * 9;
244
245 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
246 if (IS_ERR(priv->rstc))
247 return dev_err_probe(&pdev->dev, PTR_ERR(priv->rstc),
248 "failed to get cpg reset");
249
250 ret = reset_control_deassert(priv->rstc);
251 if (ret)
252 return dev_err_probe(dev, ret, "failed to deassert");
253
254 priv->devtype = (uintptr_t)of_device_get_match_data(dev);
255
256 pm_runtime_enable(&pdev->dev);
257
258 priv->wdev.info = &rzg2l_wdt_ident;
259 priv->wdev.ops = &rzg2l_wdt_ops;
260 priv->wdev.parent = dev;
261 priv->wdev.min_timeout = 1;
262 priv->wdev.max_timeout = rzg2l_wdt_get_cycle_usec(priv->osc_clk_rate, 0xfff) /
263 USEC_PER_SEC;
264 priv->wdev.timeout = WDT_DEFAULT_TIMEOUT;
265
266 watchdog_set_drvdata(&priv->wdev, priv);
267 ret = devm_add_action_or_reset(&pdev->dev,
268 rzg2l_wdt_reset_assert_pm_disable,
269 &priv->wdev);
270 if (ret < 0)
271 return ret;
272
273 watchdog_set_nowayout(&priv->wdev, nowayout);
274 watchdog_stop_on_unregister(&priv->wdev);
275
276 ret = watchdog_init_timeout(&priv->wdev, 0, dev);
277 if (ret)
278 dev_warn(dev, "Specified timeout invalid, using default");
279
280 return devm_watchdog_register_device(&pdev->dev, &priv->wdev);
281 }
282
283 static const struct of_device_id rzg2l_wdt_ids[] = {
284 { .compatible = "renesas,rzg2l-wdt", .data = (void *)WDT_RZG2L },
285 { .compatible = "renesas,rzv2m-wdt", .data = (void *)WDT_RZV2M },
286 { /* sentinel */ }
287 };
288 MODULE_DEVICE_TABLE(of, rzg2l_wdt_ids);
289
290 static struct platform_driver rzg2l_wdt_driver = {
291 .driver = {
292 .name = "rzg2l_wdt",
293 .of_match_table = rzg2l_wdt_ids,
294 },
295 .probe = rzg2l_wdt_probe,
296 };
297 module_platform_driver(rzg2l_wdt_driver);
298
299 MODULE_DESCRIPTION("Renesas RZ/G2L WDT Watchdog Driver");
300 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
301 MODULE_LICENSE("GPL v2");
302
