1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * smscufx.c -- Framebuffer driver for SMSC UFX USB controller
4  *
5  * Copyright (C) 2011 Steve Glendinning <steve.glendinning@shawell.net>
6  * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it>
7  * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com>
8  * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
9  *
10  * Based on udlfb, with work from Florian Echtler, Henrik Bjerregaard Pedersen,
11  * and others.
12  *
13  * Works well with Bernie Thompson's X DAMAGE patch to xf86-video-fbdev
14  * available from http://git.plugable.com
15  *
16  * Layout is based on skeletonfb by James Simmons and Geert Uytterhoeven,
17  * usb-skeleton by GregKH.
18  */
19 
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/usb.h>
26 #include <linux/uaccess.h>
27 #include <linux/mm.h>
28 #include <linux/fb.h>
29 #include <linux/vmalloc.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include "edid.h"
33 
34 #define check_warn(status, fmt, args...) \
35 	({ if (status < 0) pr_warn(fmt, ##args); })
36 
37 #define check_warn_return(status, fmt, args...) \
38 	({ if (status < 0) { pr_warn(fmt, ##args); return status; } })
39 
40 #define check_warn_goto_error(status, fmt, args...) \
41 	({ if (status < 0) { pr_warn(fmt, ##args); goto error; } })
42 
43 #define all_bits_set(x, bits) (((x) & (bits)) == (bits))
44 
45 #define USB_VENDOR_REQUEST_WRITE_REGISTER	0xA0
46 #define USB_VENDOR_REQUEST_READ_REGISTER	0xA1
47 
48 /*
49  * TODO: Propose standard fb.h ioctl for reporting damage,
50  * using _IOWR() and one of the existing area structs from fb.h
51  * Consider these ioctls deprecated, but they're still used by the
52  * DisplayLink X server as yet - need both to be modified in tandem
53  * when new ioctl(s) are ready.
54  */
55 #define UFX_IOCTL_RETURN_EDID	(0xAD)
56 #define UFX_IOCTL_REPORT_DAMAGE	(0xAA)
57 
58 /* -BULK_SIZE as per usb-skeleton. Can we get full page and avoid overhead? */
59 #define BULK_SIZE		(512)
60 #define MAX_TRANSFER		(PAGE_SIZE*16 - BULK_SIZE)
61 #define WRITES_IN_FLIGHT	(4)
62 
63 #define GET_URB_TIMEOUT		(HZ)
64 #define FREE_URB_TIMEOUT	(HZ*2)
65 
66 #define BPP			2
67 
68 #define UFX_DEFIO_WRITE_DELAY	5 /* fb_deferred_io.delay in jiffies */
69 #define UFX_DEFIO_WRITE_DISABLE	(HZ*60) /* "disable" with long delay */
70 
71 struct dloarea {
72 	int x, y;
73 	int w, h;
74 };
75 
76 struct urb_node {
77 	struct list_head entry;
78 	struct ufx_data *dev;
79 	struct delayed_work release_urb_work;
80 	struct urb *urb;
81 };
82 
83 struct urb_list {
84 	struct list_head list;
85 	spinlock_t lock;
86 	struct semaphore limit_sem;
87 	int available;
88 	int count;
89 	size_t size;
90 };
91 
92 struct ufx_data {
93 	struct usb_device *udev;
94 	struct device *gdev; /* &udev->dev */
95 	struct fb_info *info;
96 	struct urb_list urbs;
97 	struct kref kref;
98 	int fb_count;
99 	bool virtualized; /* true when physical usb device not present */
100 	atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */
101 	atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */
102 	u8 *edid; /* null until we read edid from hw or get from sysfs */
103 	size_t edid_size;
104 	u32 pseudo_palette[256];
105 };
106 
107 static struct fb_fix_screeninfo ufx_fix = {
108 	.id =           "smscufx",
109 	.type =         FB_TYPE_PACKED_PIXELS,
110 	.visual =       FB_VISUAL_TRUECOLOR,
111 	.xpanstep =     0,
112 	.ypanstep =     0,
113 	.ywrapstep =    0,
114 	.accel =        FB_ACCEL_NONE,
115 };
116 
117 static const u32 smscufx_info_flags = FBINFO_DEFAULT | FBINFO_READS_FAST |
118 	FBINFO_VIRTFB |	FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT |
119 	FBINFO_HWACCEL_COPYAREA | FBINFO_MISC_ALWAYS_SETPAR;
120 
121 static const struct usb_device_id id_table[] = {
122 	{USB_DEVICE(0x0424, 0x9d00),},
123 	{USB_DEVICE(0x0424, 0x9d01),},
124 	{},
125 };
126 MODULE_DEVICE_TABLE(usb, id_table);
127 
128 /* module options */
129 static bool console;   /* Optionally allow fbcon to consume first framebuffer */
130 static bool fb_defio = true;  /* Optionally enable fb_defio mmap support */
131 
132 /* ufx keeps a list of urbs for efficient bulk transfers */
133 static void ufx_urb_completion(struct urb *urb);
134 static struct urb *ufx_get_urb(struct ufx_data *dev);
135 static int ufx_submit_urb(struct ufx_data *dev, struct urb * urb, size_t len);
136 static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size);
137 static void ufx_free_urb_list(struct ufx_data *dev);
138 
139 static DEFINE_MUTEX(disconnect_mutex);
140 
141 /* reads a control register */
ufx_reg_read(struct ufx_data * dev,u32 index,u32 * data)142 static int ufx_reg_read(struct ufx_data *dev, u32 index, u32 *data)
143 {
144 	u32 *buf = kmalloc(4, GFP_KERNEL);
145 	int ret;
146 
147 	BUG_ON(!dev);
148 
149 	if (!buf)
150 		return -ENOMEM;
151 
152 	ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
153 		USB_VENDOR_REQUEST_READ_REGISTER,
154 		USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
155 		00, index, buf, 4, USB_CTRL_GET_TIMEOUT);
156 
157 	le32_to_cpus(buf);
158 	*data = *buf;
159 	kfree(buf);
160 
161 	if (unlikely(ret < 0))
162 		pr_warn("Failed to read register index 0x%08x\n", index);
163 
164 	return ret;
165 }
166 
167 /* writes a control register */
ufx_reg_write(struct ufx_data * dev,u32 index,u32 data)168 static int ufx_reg_write(struct ufx_data *dev, u32 index, u32 data)
169 {
170 	u32 *buf = kmalloc(4, GFP_KERNEL);
171 	int ret;
172 
173 	BUG_ON(!dev);
174 
175 	if (!buf)
176 		return -ENOMEM;
177 
178 	*buf = data;
179 	cpu_to_le32s(buf);
180 
181 	ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
182 		USB_VENDOR_REQUEST_WRITE_REGISTER,
183 		USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
184 		00, index, buf, 4, USB_CTRL_SET_TIMEOUT);
185 
186 	kfree(buf);
187 
188 	if (unlikely(ret < 0))
189 		pr_warn("Failed to write register index 0x%08x with value "
190 			"0x%08x\n", index, data);
191 
192 	return ret;
193 }
194 
ufx_reg_clear_and_set_bits(struct ufx_data * dev,u32 index,u32 bits_to_clear,u32 bits_to_set)195 static int ufx_reg_clear_and_set_bits(struct ufx_data *dev, u32 index,
196 	u32 bits_to_clear, u32 bits_to_set)
197 {
198 	u32 data;
199 	int status = ufx_reg_read(dev, index, &data);
200 	check_warn_return(status, "ufx_reg_clear_and_set_bits error reading "
201 		"0x%x", index);
202 
203 	data &= (~bits_to_clear);
204 	data |= bits_to_set;
205 
206 	status = ufx_reg_write(dev, index, data);
207 	check_warn_return(status, "ufx_reg_clear_and_set_bits error writing "
208 		"0x%x", index);
209 
210 	return 0;
211 }
212 
ufx_reg_set_bits(struct ufx_data * dev,u32 index,u32 bits)213 static int ufx_reg_set_bits(struct ufx_data *dev, u32 index, u32 bits)
214 {
215 	return ufx_reg_clear_and_set_bits(dev, index, 0, bits);
216 }
217 
ufx_reg_clear_bits(struct ufx_data * dev,u32 index,u32 bits)218 static int ufx_reg_clear_bits(struct ufx_data *dev, u32 index, u32 bits)
219 {
220 	return ufx_reg_clear_and_set_bits(dev, index, bits, 0);
221 }
222 
ufx_lite_reset(struct ufx_data * dev)223 static int ufx_lite_reset(struct ufx_data *dev)
224 {
225 	int status;
226 	u32 value;
227 
228 	status = ufx_reg_write(dev, 0x3008, 0x00000001);
229 	check_warn_return(status, "ufx_lite_reset error writing 0x3008");
230 
231 	status = ufx_reg_read(dev, 0x3008, &value);
232 	check_warn_return(status, "ufx_lite_reset error reading 0x3008");
233 
234 	return (value == 0) ? 0 : -EIO;
235 }
236 
237 /* If display is unblanked, then blank it */
ufx_blank(struct ufx_data * dev,bool wait)238 static int ufx_blank(struct ufx_data *dev, bool wait)
239 {
240 	u32 dc_ctrl, dc_sts;
241 	int i;
242 
243 	int status = ufx_reg_read(dev, 0x2004, &dc_sts);
244 	check_warn_return(status, "ufx_blank error reading 0x2004");
245 
246 	status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
247 	check_warn_return(status, "ufx_blank error reading 0x2000");
248 
249 	/* return success if display is already blanked */
250 	if ((dc_sts & 0x00000100) || (dc_ctrl & 0x00000100))
251 		return 0;
252 
253 	/* request the DC to blank the display */
254 	dc_ctrl |= 0x00000100;
255 	status = ufx_reg_write(dev, 0x2000, dc_ctrl);
256 	check_warn_return(status, "ufx_blank error writing 0x2000");
257 
258 	/* return success immediately if we don't have to wait */
259 	if (!wait)
260 		return 0;
261 
262 	for (i = 0; i < 250; i++) {
263 		status = ufx_reg_read(dev, 0x2004, &dc_sts);
264 		check_warn_return(status, "ufx_blank error reading 0x2004");
265 
266 		if (dc_sts & 0x00000100)
267 			return 0;
268 	}
269 
270 	/* timed out waiting for display to blank */
271 	return -EIO;
272 }
273 
274 /* If display is blanked, then unblank it */
ufx_unblank(struct ufx_data * dev,bool wait)275 static int ufx_unblank(struct ufx_data *dev, bool wait)
276 {
277 	u32 dc_ctrl, dc_sts;
278 	int i;
279 
280 	int status = ufx_reg_read(dev, 0x2004, &dc_sts);
281 	check_warn_return(status, "ufx_unblank error reading 0x2004");
282 
283 	status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
284 	check_warn_return(status, "ufx_unblank error reading 0x2000");
285 
286 	/* return success if display is already unblanked */
287 	if (((dc_sts & 0x00000100) == 0) || ((dc_ctrl & 0x00000100) == 0))
288 		return 0;
289 
290 	/* request the DC to unblank the display */
291 	dc_ctrl &= ~0x00000100;
292 	status = ufx_reg_write(dev, 0x2000, dc_ctrl);
293 	check_warn_return(status, "ufx_unblank error writing 0x2000");
294 
295 	/* return success immediately if we don't have to wait */
296 	if (!wait)
297 		return 0;
298 
299 	for (i = 0; i < 250; i++) {
300 		status = ufx_reg_read(dev, 0x2004, &dc_sts);
301 		check_warn_return(status, "ufx_unblank error reading 0x2004");
302 
303 		if ((dc_sts & 0x00000100) == 0)
304 			return 0;
305 	}
306 
307 	/* timed out waiting for display to unblank */
308 	return -EIO;
309 }
310 
311 /* If display is enabled, then disable it */
ufx_disable(struct ufx_data * dev,bool wait)312 static int ufx_disable(struct ufx_data *dev, bool wait)
313 {
314 	u32 dc_ctrl, dc_sts;
315 	int i;
316 
317 	int status = ufx_reg_read(dev, 0x2004, &dc_sts);
318 	check_warn_return(status, "ufx_disable error reading 0x2004");
319 
320 	status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
321 	check_warn_return(status, "ufx_disable error reading 0x2000");
322 
323 	/* return success if display is already disabled */
324 	if (((dc_sts & 0x00000001) == 0) || ((dc_ctrl & 0x00000001) == 0))
325 		return 0;
326 
327 	/* request the DC to disable the display */
328 	dc_ctrl &= ~(0x00000001);
329 	status = ufx_reg_write(dev, 0x2000, dc_ctrl);
330 	check_warn_return(status, "ufx_disable error writing 0x2000");
331 
332 	/* return success immediately if we don't have to wait */
333 	if (!wait)
334 		return 0;
335 
336 	for (i = 0; i < 250; i++) {
337 		status = ufx_reg_read(dev, 0x2004, &dc_sts);
338 		check_warn_return(status, "ufx_disable error reading 0x2004");
339 
340 		if ((dc_sts & 0x00000001) == 0)
341 			return 0;
342 	}
343 
344 	/* timed out waiting for display to disable */
345 	return -EIO;
346 }
347 
348 /* If display is disabled, then enable it */
ufx_enable(struct ufx_data * dev,bool wait)349 static int ufx_enable(struct ufx_data *dev, bool wait)
350 {
351 	u32 dc_ctrl, dc_sts;
352 	int i;
353 
354 	int status = ufx_reg_read(dev, 0x2004, &dc_sts);
355 	check_warn_return(status, "ufx_enable error reading 0x2004");
356 
357 	status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
358 	check_warn_return(status, "ufx_enable error reading 0x2000");
359 
360 	/* return success if display is already enabled */
361 	if ((dc_sts & 0x00000001) || (dc_ctrl & 0x00000001))
362 		return 0;
363 
364 	/* request the DC to enable the display */
365 	dc_ctrl |= 0x00000001;
366 	status = ufx_reg_write(dev, 0x2000, dc_ctrl);
367 	check_warn_return(status, "ufx_enable error writing 0x2000");
368 
369 	/* return success immediately if we don't have to wait */
370 	if (!wait)
371 		return 0;
372 
373 	for (i = 0; i < 250; i++) {
374 		status = ufx_reg_read(dev, 0x2004, &dc_sts);
375 		check_warn_return(status, "ufx_enable error reading 0x2004");
376 
377 		if (dc_sts & 0x00000001)
378 			return 0;
379 	}
380 
381 	/* timed out waiting for display to enable */
382 	return -EIO;
383 }
384 
ufx_config_sys_clk(struct ufx_data * dev)385 static int ufx_config_sys_clk(struct ufx_data *dev)
386 {
387 	int status = ufx_reg_write(dev, 0x700C, 0x8000000F);
388 	check_warn_return(status, "error writing 0x700C");
389 
390 	status = ufx_reg_write(dev, 0x7014, 0x0010024F);
391 	check_warn_return(status, "error writing 0x7014");
392 
393 	status = ufx_reg_write(dev, 0x7010, 0x00000000);
394 	check_warn_return(status, "error writing 0x7010");
395 
396 	status = ufx_reg_clear_bits(dev, 0x700C, 0x0000000A);
397 	check_warn_return(status, "error clearing PLL1 bypass in 0x700C");
398 	msleep(1);
399 
400 	status = ufx_reg_clear_bits(dev, 0x700C, 0x80000000);
401 	check_warn_return(status, "error clearing output gate in 0x700C");
402 
403 	return 0;
404 }
405 
ufx_config_ddr2(struct ufx_data * dev)406 static int ufx_config_ddr2(struct ufx_data *dev)
407 {
408 	int status, i = 0;
409 	u32 tmp;
410 
411 	status = ufx_reg_write(dev, 0x0004, 0x001F0F77);
412 	check_warn_return(status, "error writing 0x0004");
413 
414 	status = ufx_reg_write(dev, 0x0008, 0xFFF00000);
415 	check_warn_return(status, "error writing 0x0008");
416 
417 	status = ufx_reg_write(dev, 0x000C, 0x0FFF2222);
418 	check_warn_return(status, "error writing 0x000C");
419 
420 	status = ufx_reg_write(dev, 0x0010, 0x00030814);
421 	check_warn_return(status, "error writing 0x0010");
422 
423 	status = ufx_reg_write(dev, 0x0014, 0x00500019);
424 	check_warn_return(status, "error writing 0x0014");
425 
426 	status = ufx_reg_write(dev, 0x0018, 0x020D0F15);
427 	check_warn_return(status, "error writing 0x0018");
428 
429 	status = ufx_reg_write(dev, 0x001C, 0x02532305);
430 	check_warn_return(status, "error writing 0x001C");
431 
432 	status = ufx_reg_write(dev, 0x0020, 0x0B030905);
433 	check_warn_return(status, "error writing 0x0020");
434 
435 	status = ufx_reg_write(dev, 0x0024, 0x00000827);
436 	check_warn_return(status, "error writing 0x0024");
437 
438 	status = ufx_reg_write(dev, 0x0028, 0x00000000);
439 	check_warn_return(status, "error writing 0x0028");
440 
441 	status = ufx_reg_write(dev, 0x002C, 0x00000042);
442 	check_warn_return(status, "error writing 0x002C");
443 
444 	status = ufx_reg_write(dev, 0x0030, 0x09520000);
445 	check_warn_return(status, "error writing 0x0030");
446 
447 	status = ufx_reg_write(dev, 0x0034, 0x02223314);
448 	check_warn_return(status, "error writing 0x0034");
449 
450 	status = ufx_reg_write(dev, 0x0038, 0x00430043);
451 	check_warn_return(status, "error writing 0x0038");
452 
453 	status = ufx_reg_write(dev, 0x003C, 0xF00F000F);
454 	check_warn_return(status, "error writing 0x003C");
455 
456 	status = ufx_reg_write(dev, 0x0040, 0xF380F00F);
457 	check_warn_return(status, "error writing 0x0040");
458 
459 	status = ufx_reg_write(dev, 0x0044, 0xF00F0496);
460 	check_warn_return(status, "error writing 0x0044");
461 
462 	status = ufx_reg_write(dev, 0x0048, 0x03080406);
463 	check_warn_return(status, "error writing 0x0048");
464 
465 	status = ufx_reg_write(dev, 0x004C, 0x00001000);
466 	check_warn_return(status, "error writing 0x004C");
467 
468 	status = ufx_reg_write(dev, 0x005C, 0x00000007);
469 	check_warn_return(status, "error writing 0x005C");
470 
471 	status = ufx_reg_write(dev, 0x0100, 0x54F00012);
472 	check_warn_return(status, "error writing 0x0100");
473 
474 	status = ufx_reg_write(dev, 0x0104, 0x00004012);
475 	check_warn_return(status, "error writing 0x0104");
476 
477 	status = ufx_reg_write(dev, 0x0118, 0x40404040);
478 	check_warn_return(status, "error writing 0x0118");
479 
480 	status = ufx_reg_write(dev, 0x0000, 0x00000001);
481 	check_warn_return(status, "error writing 0x0000");
482 
483 	while (i++ < 500) {
484 		status = ufx_reg_read(dev, 0x0000, &tmp);
485 		check_warn_return(status, "error reading 0x0000");
486 
487 		if (all_bits_set(tmp, 0xC0000000))
488 			return 0;
489 	}
490 
491 	pr_err("DDR2 initialisation timed out, reg 0x0000=0x%08x", tmp);
492 	return -ETIMEDOUT;
493 }
494 
495 struct pll_values {
496 	u32 div_r0;
497 	u32 div_f0;
498 	u32 div_q0;
499 	u32 range0;
500 	u32 div_r1;
501 	u32 div_f1;
502 	u32 div_q1;
503 	u32 range1;
504 };
505 
ufx_calc_range(u32 ref_freq)506 static u32 ufx_calc_range(u32 ref_freq)
507 {
508 	if (ref_freq >= 88000000)
509 		return 7;
510 
511 	if (ref_freq >= 54000000)
512 		return 6;
513 
514 	if (ref_freq >= 34000000)
515 		return 5;
516 
517 	if (ref_freq >= 21000000)
518 		return 4;
519 
520 	if (ref_freq >= 13000000)
521 		return 3;
522 
523 	if (ref_freq >= 8000000)
524 		return 2;
525 
526 	return 1;
527 }
528 
529 /* calculates PLL divider settings for a desired target frequency */
ufx_calc_pll_values(const u32 clk_pixel_pll,struct pll_values * asic_pll)530 static void ufx_calc_pll_values(const u32 clk_pixel_pll, struct pll_values *asic_pll)
531 {
532 	const u32 ref_clk = 25000000;
533 	u32 div_r0, div_f0, div_q0, div_r1, div_f1, div_q1;
534 	u32 min_error = clk_pixel_pll;
535 
536 	for (div_r0 = 1; div_r0 <= 32; div_r0++) {
537 		u32 ref_freq0 = ref_clk / div_r0;
538 		if (ref_freq0 < 5000000)
539 			break;
540 
541 		if (ref_freq0 > 200000000)
542 			continue;
543 
544 		for (div_f0 = 1; div_f0 <= 256; div_f0++) {
545 			u32 vco_freq0 = ref_freq0 * div_f0;
546 
547 			if (vco_freq0 < 350000000)
548 				continue;
549 
550 			if (vco_freq0 > 700000000)
551 				break;
552 
553 			for (div_q0 = 0; div_q0 < 7; div_q0++) {
554 				u32 pllout_freq0 = vco_freq0 / (1 << div_q0);
555 
556 				if (pllout_freq0 < 5000000)
557 					break;
558 
559 				if (pllout_freq0 > 200000000)
560 					continue;
561 
562 				for (div_r1 = 1; div_r1 <= 32; div_r1++) {
563 					u32 ref_freq1 = pllout_freq0 / div_r1;
564 
565 					if (ref_freq1 < 5000000)
566 						break;
567 
568 					for (div_f1 = 1; div_f1 <= 256; div_f1++) {
569 						u32 vco_freq1 = ref_freq1 * div_f1;
570 
571 						if (vco_freq1 < 350000000)
572 							continue;
573 
574 						if (vco_freq1 > 700000000)
575 							break;
576 
577 						for (div_q1 = 0; div_q1 < 7; div_q1++) {
578 							u32 pllout_freq1 = vco_freq1 / (1 << div_q1);
579 							int error = abs(pllout_freq1 - clk_pixel_pll);
580 
581 							if (pllout_freq1 < 5000000)
582 								break;
583 
584 							if (pllout_freq1 > 700000000)
585 								continue;
586 
587 							if (error < min_error) {
588 								min_error = error;
589 
590 								/* final returned value is equal to calculated value - 1
591 								 * because a value of 0 = divide by 1 */
592 								asic_pll->div_r0 = div_r0 - 1;
593 								asic_pll->div_f0 = div_f0 - 1;
594 								asic_pll->div_q0 = div_q0;
595 								asic_pll->div_r1 = div_r1 - 1;
596 								asic_pll->div_f1 = div_f1 - 1;
597 								asic_pll->div_q1 = div_q1;
598 
599 								asic_pll->range0 = ufx_calc_range(ref_freq0);
600 								asic_pll->range1 = ufx_calc_range(ref_freq1);
601 
602 								if (min_error == 0)
603 									return;
604 							}
605 						}
606 					}
607 				}
608 			}
609 		}
610 	}
611 }
612 
613 /* sets analog bit PLL configuration values */
ufx_config_pix_clk(struct ufx_data * dev,u32 pixclock)614 static int ufx_config_pix_clk(struct ufx_data *dev, u32 pixclock)
615 {
616 	struct pll_values asic_pll = {0};
617 	u32 value, clk_pixel, clk_pixel_pll;
618 	int status;
619 
620 	/* convert pixclock (in ps) to frequency (in Hz) */
621 	clk_pixel = PICOS2KHZ(pixclock) * 1000;
622 	pr_debug("pixclock %d ps = clk_pixel %d Hz", pixclock, clk_pixel);
623 
624 	/* clk_pixel = 1/2 clk_pixel_pll */
625 	clk_pixel_pll = clk_pixel * 2;
626 
627 	ufx_calc_pll_values(clk_pixel_pll, &asic_pll);
628 
629 	/* Keep BYPASS and RESET signals asserted until configured */
630 	status = ufx_reg_write(dev, 0x7000, 0x8000000F);
631 	check_warn_return(status, "error writing 0x7000");
632 
633 	value = (asic_pll.div_f1 | (asic_pll.div_r1 << 8) |
634 		(asic_pll.div_q1 << 16) | (asic_pll.range1 << 20));
635 	status = ufx_reg_write(dev, 0x7008, value);
636 	check_warn_return(status, "error writing 0x7008");
637 
638 	value = (asic_pll.div_f0 | (asic_pll.div_r0 << 8) |
639 		(asic_pll.div_q0 << 16) | (asic_pll.range0 << 20));
640 	status = ufx_reg_write(dev, 0x7004, value);
641 	check_warn_return(status, "error writing 0x7004");
642 
643 	status = ufx_reg_clear_bits(dev, 0x7000, 0x00000005);
644 	check_warn_return(status,
645 		"error clearing PLL0 bypass bits in 0x7000");
646 	msleep(1);
647 
648 	status = ufx_reg_clear_bits(dev, 0x7000, 0x0000000A);
649 	check_warn_return(status,
650 		"error clearing PLL1 bypass bits in 0x7000");
651 	msleep(1);
652 
653 	status = ufx_reg_clear_bits(dev, 0x7000, 0x80000000);
654 	check_warn_return(status, "error clearing gate bits in 0x7000");
655 
656 	return 0;
657 }
658 
ufx_set_vid_mode(struct ufx_data * dev,struct fb_var_screeninfo * var)659 static int ufx_set_vid_mode(struct ufx_data *dev, struct fb_var_screeninfo *var)
660 {
661 	u32 temp;
662 	u16 h_total, h_active, h_blank_start, h_blank_end, h_sync_start, h_sync_end;
663 	u16 v_total, v_active, v_blank_start, v_blank_end, v_sync_start, v_sync_end;
664 
665 	int status = ufx_reg_write(dev, 0x8028, 0);
666 	check_warn_return(status, "ufx_set_vid_mode error disabling RGB pad");
667 
668 	status = ufx_reg_write(dev, 0x8024, 0);
669 	check_warn_return(status, "ufx_set_vid_mode error disabling VDAC");
670 
671 	/* shut everything down before changing timing */
672 	status = ufx_blank(dev, true);
673 	check_warn_return(status, "ufx_set_vid_mode error blanking display");
674 
675 	status = ufx_disable(dev, true);
676 	check_warn_return(status, "ufx_set_vid_mode error disabling display");
677 
678 	status = ufx_config_pix_clk(dev, var->pixclock);
679 	check_warn_return(status, "ufx_set_vid_mode error configuring pixclock");
680 
681 	status = ufx_reg_write(dev, 0x2000, 0x00000104);
682 	check_warn_return(status, "ufx_set_vid_mode error writing 0x2000");
683 
684 	/* set horizontal timings */
685 	h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
686 	h_active = var->xres;
687 	h_blank_start = var->xres + var->right_margin;
688 	h_blank_end = var->xres + var->right_margin + var->hsync_len;
689 	h_sync_start = var->xres + var->right_margin;
690 	h_sync_end = var->xres + var->right_margin + var->hsync_len;
691 
692 	temp = ((h_total - 1) << 16) | (h_active - 1);
693 	status = ufx_reg_write(dev, 0x2008, temp);
694 	check_warn_return(status, "ufx_set_vid_mode error writing 0x2008");
695 
696 	temp = ((h_blank_start - 1) << 16) | (h_blank_end - 1);
697 	status = ufx_reg_write(dev, 0x200C, temp);
698 	check_warn_return(status, "ufx_set_vid_mode error writing 0x200C");
699 
700 	temp = ((h_sync_start - 1) << 16) | (h_sync_end - 1);
701 	status = ufx_reg_write(dev, 0x2010, temp);
702 	check_warn_return(status, "ufx_set_vid_mode error writing 0x2010");
703 
704 	/* set vertical timings */
705 	v_total = var->upper_margin + var->yres + var->lower_margin + var->vsync_len;
706 	v_active = var->yres;
707 	v_blank_start = var->yres + var->lower_margin;
708 	v_blank_end = var->yres + var->lower_margin + var->vsync_len;
709 	v_sync_start = var->yres + var->lower_margin;
710 	v_sync_end = var->yres + var->lower_margin + var->vsync_len;
711 
712 	temp = ((v_total - 1) << 16) | (v_active - 1);
713 	status = ufx_reg_write(dev, 0x2014, temp);
714 	check_warn_return(status, "ufx_set_vid_mode error writing 0x2014");
715 
716 	temp = ((v_blank_start - 1) << 16) | (v_blank_end - 1);
717 	status = ufx_reg_write(dev, 0x2018, temp);
718 	check_warn_return(status, "ufx_set_vid_mode error writing 0x2018");
719 
720 	temp = ((v_sync_start - 1) << 16) | (v_sync_end - 1);
721 	status = ufx_reg_write(dev, 0x201C, temp);
722 	check_warn_return(status, "ufx_set_vid_mode error writing 0x201C");
723 
724 	status = ufx_reg_write(dev, 0x2020, 0x00000000);
725 	check_warn_return(status, "ufx_set_vid_mode error writing 0x2020");
726 
727 	status = ufx_reg_write(dev, 0x2024, 0x00000000);
728 	check_warn_return(status, "ufx_set_vid_mode error writing 0x2024");
729 
730 	/* Set the frame length register (#pix * 2 bytes/pixel) */
731 	temp = var->xres * var->yres * 2;
732 	temp = (temp + 7) & (~0x7);
733 	status = ufx_reg_write(dev, 0x2028, temp);
734 	check_warn_return(status, "ufx_set_vid_mode error writing 0x2028");
735 
736 	/* enable desired output interface & disable others */
737 	status = ufx_reg_write(dev, 0x2040, 0);
738 	check_warn_return(status, "ufx_set_vid_mode error writing 0x2040");
739 
740 	status = ufx_reg_write(dev, 0x2044, 0);
741 	check_warn_return(status, "ufx_set_vid_mode error writing 0x2044");
742 
743 	status = ufx_reg_write(dev, 0x2048, 0);
744 	check_warn_return(status, "ufx_set_vid_mode error writing 0x2048");
745 
746 	/* set the sync polarities & enable bit */
747 	temp = 0x00000001;
748 	if (var->sync & FB_SYNC_HOR_HIGH_ACT)
749 		temp |= 0x00000010;
750 
751 	if (var->sync & FB_SYNC_VERT_HIGH_ACT)
752 		temp |= 0x00000008;
753 
754 	status = ufx_reg_write(dev, 0x2040, temp);
755 	check_warn_return(status, "ufx_set_vid_mode error writing 0x2040");
756 
757 	/* start everything back up */
758 	status = ufx_enable(dev, true);
759 	check_warn_return(status, "ufx_set_vid_mode error enabling display");
760 
761 	/* Unblank the display */
762 	status = ufx_unblank(dev, true);
763 	check_warn_return(status, "ufx_set_vid_mode error unblanking display");
764 
765 	/* enable RGB pad */
766 	status = ufx_reg_write(dev, 0x8028, 0x00000003);
767 	check_warn_return(status, "ufx_set_vid_mode error enabling RGB pad");
768 
769 	/* enable VDAC */
770 	status = ufx_reg_write(dev, 0x8024, 0x00000007);
771 	check_warn_return(status, "ufx_set_vid_mode error enabling VDAC");
772 
773 	return 0;
774 }
775 
ufx_ops_mmap(struct fb_info * info,struct vm_area_struct * vma)776 static int ufx_ops_mmap(struct fb_info *info, struct vm_area_struct *vma)
777 {
778 	unsigned long start = vma->vm_start;
779 	unsigned long size = vma->vm_end - vma->vm_start;
780 	unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
781 	unsigned long page, pos;
782 
783 	if (info->fbdefio)
784 		return fb_deferred_io_mmap(info, vma);
785 
786 	if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
787 		return -EINVAL;
788 	if (size > info->fix.smem_len)
789 		return -EINVAL;
790 	if (offset > info->fix.smem_len - size)
791 		return -EINVAL;
792 
793 	pos = (unsigned long)info->fix.smem_start + offset;
794 
795 	pr_debug("mmap() framebuffer addr:%lu size:%lu\n",
796 		  pos, size);
797 
798 	while (size > 0) {
799 		page = vmalloc_to_pfn((void *)pos);
800 		if (remap_pfn_range(vma, start, page, PAGE_SIZE, PAGE_SHARED))
801 			return -EAGAIN;
802 
803 		start += PAGE_SIZE;
804 		pos += PAGE_SIZE;
805 		if (size > PAGE_SIZE)
806 			size -= PAGE_SIZE;
807 		else
808 			size = 0;
809 	}
810 
811 	return 0;
812 }
813 
ufx_raw_rect(struct ufx_data * dev,u16 * cmd,int x,int y,int width,int height)814 static void ufx_raw_rect(struct ufx_data *dev, u16 *cmd, int x, int y,
815 	int width, int height)
816 {
817 	size_t packed_line_len = ALIGN((width * 2), 4);
818 	size_t packed_rect_len = packed_line_len * height;
819 	int line;
820 
821 	BUG_ON(!dev);
822 	BUG_ON(!dev->info);
823 
824 	/* command word */
825 	*((u32 *)&cmd[0]) = cpu_to_le32(0x01);
826 
827 	/* length word */
828 	*((u32 *)&cmd[2]) = cpu_to_le32(packed_rect_len + 16);
829 
830 	cmd[4] = cpu_to_le16(x);
831 	cmd[5] = cpu_to_le16(y);
832 	cmd[6] = cpu_to_le16(width);
833 	cmd[7] = cpu_to_le16(height);
834 
835 	/* frame base address */
836 	*((u32 *)&cmd[8]) = cpu_to_le32(0);
837 
838 	/* color mode and horizontal resolution */
839 	cmd[10] = cpu_to_le16(0x4000 | dev->info->var.xres);
840 
841 	/* vertical resolution */
842 	cmd[11] = cpu_to_le16(dev->info->var.yres);
843 
844 	/* packed data */
845 	for (line = 0; line < height; line++) {
846 		const int line_offset = dev->info->fix.line_length * (y + line);
847 		const int byte_offset = line_offset + (x * BPP);
848 		memcpy(&cmd[(24 + (packed_line_len * line)) / 2],
849 			(char *)dev->info->fix.smem_start + byte_offset, width * BPP);
850 	}
851 }
852 
ufx_handle_damage(struct ufx_data * dev,int x,int y,int width,int height)853 static int ufx_handle_damage(struct ufx_data *dev, int x, int y,
854 	int width, int height)
855 {
856 	size_t packed_line_len = ALIGN((width * 2), 4);
857 	int len, status, urb_lines, start_line = 0;
858 
859 	if ((width <= 0) || (height <= 0) ||
860 	    (x + width > dev->info->var.xres) ||
861 	    (y + height > dev->info->var.yres))
862 		return -EINVAL;
863 
864 	if (!atomic_read(&dev->usb_active))
865 		return 0;
866 
867 	while (start_line < height) {
868 		struct urb *urb = ufx_get_urb(dev);
869 		if (!urb) {
870 			pr_warn("ufx_handle_damage unable to get urb");
871 			return 0;
872 		}
873 
874 		/* assume we have enough space to transfer at least one line */
875 		BUG_ON(urb->transfer_buffer_length < (24 + (width * 2)));
876 
877 		/* calculate the maximum number of lines we could fit in */
878 		urb_lines = (urb->transfer_buffer_length - 24) / packed_line_len;
879 
880 		/* but we might not need this many */
881 		urb_lines = min(urb_lines, (height - start_line));
882 
883 		memset(urb->transfer_buffer, 0, urb->transfer_buffer_length);
884 
885 		ufx_raw_rect(dev, urb->transfer_buffer, x, (y + start_line), width, urb_lines);
886 		len = 24 + (packed_line_len * urb_lines);
887 
888 		status = ufx_submit_urb(dev, urb, len);
889 		check_warn_return(status, "Error submitting URB");
890 
891 		start_line += urb_lines;
892 	}
893 
894 	return 0;
895 }
896 
897 /* Path triggered by usermode clients who write to filesystem
898  * e.g. cat filename > /dev/fb1
899  * Not used by X Windows or text-mode console. But useful for testing.
900  * Slow because of extra copy and we must assume all pixels dirty. */
ufx_ops_write(struct fb_info * info,const char __user * buf,size_t count,loff_t * ppos)901 static ssize_t ufx_ops_write(struct fb_info *info, const char __user *buf,
902 			  size_t count, loff_t *ppos)
903 {
904 	ssize_t result;
905 	struct ufx_data *dev = info->par;
906 	u32 offset = (u32) *ppos;
907 
908 	result = fb_sys_write(info, buf, count, ppos);
909 
910 	if (result > 0) {
911 		int start = max((int)(offset / info->fix.line_length), 0);
912 		int lines = min((u32)((result / info->fix.line_length) + 1),
913 				(u32)info->var.yres);
914 
915 		ufx_handle_damage(dev, 0, start, info->var.xres, lines);
916 	}
917 
918 	return result;
919 }
920 
ufx_ops_copyarea(struct fb_info * info,const struct fb_copyarea * area)921 static void ufx_ops_copyarea(struct fb_info *info,
922 				const struct fb_copyarea *area)
923 {
924 
925 	struct ufx_data *dev = info->par;
926 
927 	sys_copyarea(info, area);
928 
929 	ufx_handle_damage(dev, area->dx, area->dy,
930 			area->width, area->height);
931 }
932 
ufx_ops_imageblit(struct fb_info * info,const struct fb_image * image)933 static void ufx_ops_imageblit(struct fb_info *info,
934 				const struct fb_image *image)
935 {
936 	struct ufx_data *dev = info->par;
937 
938 	sys_imageblit(info, image);
939 
940 	ufx_handle_damage(dev, image->dx, image->dy,
941 			image->width, image->height);
942 }
943 
ufx_ops_fillrect(struct fb_info * info,const struct fb_fillrect * rect)944 static void ufx_ops_fillrect(struct fb_info *info,
945 			  const struct fb_fillrect *rect)
946 {
947 	struct ufx_data *dev = info->par;
948 
949 	sys_fillrect(info, rect);
950 
951 	ufx_handle_damage(dev, rect->dx, rect->dy, rect->width,
952 			      rect->height);
953 }
954 
955 /* NOTE: fb_defio.c is holding info->fbdefio.mutex
956  *   Touching ANY framebuffer memory that triggers a page fault
957  *   in fb_defio will cause a deadlock, when it also tries to
958  *   grab the same mutex. */
ufx_dpy_deferred_io(struct fb_info * info,struct list_head * pagereflist)959 static void ufx_dpy_deferred_io(struct fb_info *info, struct list_head *pagereflist)
960 {
961 	struct ufx_data *dev = info->par;
962 	struct fb_deferred_io_pageref *pageref;
963 
964 	if (!fb_defio)
965 		return;
966 
967 	if (!atomic_read(&dev->usb_active))
968 		return;
969 
970 	/* walk the written page list and render each to device */
971 	list_for_each_entry(pageref, pagereflist, list) {
972 		/* create a rectangle of full screen width that encloses the
973 		 * entire dirty framebuffer page */
974 		const int x = 0;
975 		const int width = dev->info->var.xres;
976 		const int y = pageref->offset / (width * 2);
977 		int height = (PAGE_SIZE / (width * 2)) + 1;
978 		height = min(height, (int)(dev->info->var.yres - y));
979 
980 		BUG_ON(y >= dev->info->var.yres);
981 		BUG_ON((y + height) > dev->info->var.yres);
982 
983 		ufx_handle_damage(dev, x, y, width, height);
984 	}
985 }
986 
ufx_ops_ioctl(struct fb_info * info,unsigned int cmd,unsigned long arg)987 static int ufx_ops_ioctl(struct fb_info *info, unsigned int cmd,
988 			 unsigned long arg)
989 {
990 	struct ufx_data *dev = info->par;
991 	struct dloarea *area = NULL;
992 
993 	if (!atomic_read(&dev->usb_active))
994 		return 0;
995 
996 	/* TODO: Update X server to get this from sysfs instead */
997 	if (cmd == UFX_IOCTL_RETURN_EDID) {
998 		u8 __user *edid = (u8 __user *)arg;
999 		if (copy_to_user(edid, dev->edid, dev->edid_size))
1000 			return -EFAULT;
1001 		return 0;
1002 	}
1003 
1004 	/* TODO: Help propose a standard fb.h ioctl to report mmap damage */
1005 	if (cmd == UFX_IOCTL_REPORT_DAMAGE) {
1006 		/* If we have a damage-aware client, turn fb_defio "off"
1007 		 * To avoid perf imact of unnecessary page fault handling.
1008 		 * Done by resetting the delay for this fb_info to a very
1009 		 * long period. Pages will become writable and stay that way.
1010 		 * Reset to normal value when all clients have closed this fb.
1011 		 */
1012 		if (info->fbdefio)
1013 			info->fbdefio->delay = UFX_DEFIO_WRITE_DISABLE;
1014 
1015 		area = (struct dloarea *)arg;
1016 
1017 		if (area->x < 0)
1018 			area->x = 0;
1019 
1020 		if (area->x > info->var.xres)
1021 			area->x = info->var.xres;
1022 
1023 		if (area->y < 0)
1024 			area->y = 0;
1025 
1026 		if (area->y > info->var.yres)
1027 			area->y = info->var.yres;
1028 
1029 		ufx_handle_damage(dev, area->x, area->y, area->w, area->h);
1030 	}
1031 
1032 	return 0;
1033 }
1034 
1035 /* taken from vesafb */
1036 static int
ufx_ops_setcolreg(unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp,struct fb_info * info)1037 ufx_ops_setcolreg(unsigned regno, unsigned red, unsigned green,
1038 	       unsigned blue, unsigned transp, struct fb_info *info)
1039 {
1040 	int err = 0;
1041 
1042 	if (regno >= info->cmap.len)
1043 		return 1;
1044 
1045 	if (regno < 16) {
1046 		if (info->var.red.offset == 10) {
1047 			/* 1:5:5:5 */
1048 			((u32 *) (info->pseudo_palette))[regno] =
1049 			    ((red & 0xf800) >> 1) |
1050 			    ((green & 0xf800) >> 6) | ((blue & 0xf800) >> 11);
1051 		} else {
1052 			/* 0:5:6:5 */
1053 			((u32 *) (info->pseudo_palette))[regno] =
1054 			    ((red & 0xf800)) |
1055 			    ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11);
1056 		}
1057 	}
1058 
1059 	return err;
1060 }
1061 
1062 /* It's common for several clients to have framebuffer open simultaneously.
1063  * e.g. both fbcon and X. Makes things interesting.
1064  * Assumes caller is holding info->lock (for open and release at least) */
ufx_ops_open(struct fb_info * info,int user)1065 static int ufx_ops_open(struct fb_info *info, int user)
1066 {
1067 	struct ufx_data *dev = info->par;
1068 
1069 	/* fbcon aggressively connects to first framebuffer it finds,
1070 	 * preventing other clients (X) from working properly. Usually
1071 	 * not what the user wants. Fail by default with option to enable. */
1072 	if (user == 0 && !console)
1073 		return -EBUSY;
1074 
1075 	mutex_lock(&disconnect_mutex);
1076 
1077 	/* If the USB device is gone, we don't accept new opens */
1078 	if (dev->virtualized) {
1079 		mutex_unlock(&disconnect_mutex);
1080 		return -ENODEV;
1081 	}
1082 
1083 	dev->fb_count++;
1084 
1085 	kref_get(&dev->kref);
1086 
1087 	if (fb_defio && (info->fbdefio == NULL)) {
1088 		/* enable defio at last moment if not disabled by client */
1089 
1090 		struct fb_deferred_io *fbdefio;
1091 
1092 		fbdefio = kzalloc(sizeof(*fbdefio), GFP_KERNEL);
1093 		if (fbdefio) {
1094 			fbdefio->delay = UFX_DEFIO_WRITE_DELAY;
1095 			fbdefio->deferred_io = ufx_dpy_deferred_io;
1096 		}
1097 
1098 		info->fbdefio = fbdefio;
1099 		fb_deferred_io_init(info);
1100 	}
1101 
1102 	pr_debug("open /dev/fb%d user=%d fb_info=%p count=%d",
1103 		info->node, user, info, dev->fb_count);
1104 
1105 	mutex_unlock(&disconnect_mutex);
1106 
1107 	return 0;
1108 }
1109 
1110 /*
1111  * Called when all client interfaces to start transactions have been disabled,
1112  * and all references to our device instance (ufx_data) are released.
1113  * Every transaction must have a reference, so we know are fully spun down
1114  */
ufx_free(struct kref * kref)1115 static void ufx_free(struct kref *kref)
1116 {
1117 	struct ufx_data *dev = container_of(kref, struct ufx_data, kref);
1118 
1119 	kfree(dev);
1120 }
1121 
ufx_ops_destory(struct fb_info * info)1122 static void ufx_ops_destory(struct fb_info *info)
1123 {
1124 	struct ufx_data *dev = info->par;
1125 	int node = info->node;
1126 
1127 	/* Assume info structure is freed after this point */
1128 	framebuffer_release(info);
1129 
1130 	pr_debug("fb_info for /dev/fb%d has been freed", node);
1131 
1132 	/* release reference taken by kref_init in probe() */
1133 	kref_put(&dev->kref, ufx_free);
1134 }
1135 
1136 
ufx_release_urb_work(struct work_struct * work)1137 static void ufx_release_urb_work(struct work_struct *work)
1138 {
1139 	struct urb_node *unode = container_of(work, struct urb_node,
1140 					      release_urb_work.work);
1141 
1142 	up(&unode->dev->urbs.limit_sem);
1143 }
1144 
ufx_free_framebuffer(struct ufx_data * dev)1145 static void ufx_free_framebuffer(struct ufx_data *dev)
1146 {
1147 	struct fb_info *info = dev->info;
1148 
1149 	if (info->cmap.len != 0)
1150 		fb_dealloc_cmap(&info->cmap);
1151 	if (info->monspecs.modedb)
1152 		fb_destroy_modedb(info->monspecs.modedb);
1153 	vfree(info->screen_base);
1154 
1155 	fb_destroy_modelist(&info->modelist);
1156 
1157 	dev->info = NULL;
1158 
1159 	/* ref taken in probe() as part of registering framebfufer */
1160 	kref_put(&dev->kref, ufx_free);
1161 }
1162 
1163 /*
1164  * Assumes caller is holding info->lock mutex (for open and release at least)
1165  */
ufx_ops_release(struct fb_info * info,int user)1166 static int ufx_ops_release(struct fb_info *info, int user)
1167 {
1168 	struct ufx_data *dev = info->par;
1169 
1170 	mutex_lock(&disconnect_mutex);
1171 
1172 	dev->fb_count--;
1173 
1174 	/* We can't free fb_info here - fbmem will touch it when we return */
1175 	if (dev->virtualized && (dev->fb_count == 0))
1176 		ufx_free_framebuffer(dev);
1177 
1178 	if ((dev->fb_count == 0) && (info->fbdefio)) {
1179 		fb_deferred_io_cleanup(info);
1180 		kfree(info->fbdefio);
1181 		info->fbdefio = NULL;
1182 	}
1183 
1184 	pr_debug("released /dev/fb%d user=%d count=%d",
1185 		  info->node, user, dev->fb_count);
1186 
1187 	kref_put(&dev->kref, ufx_free);
1188 
1189 	mutex_unlock(&disconnect_mutex);
1190 
1191 	return 0;
1192 }
1193 
1194 /* Check whether a video mode is supported by the chip
1195  * We start from monitor's modes, so don't need to filter that here */
ufx_is_valid_mode(struct fb_videomode * mode,struct fb_info * info)1196 static int ufx_is_valid_mode(struct fb_videomode *mode,
1197 		struct fb_info *info)
1198 {
1199 	if ((mode->xres * mode->yres) > (2048 * 1152)) {
1200 		pr_debug("%dx%d too many pixels",
1201 		       mode->xres, mode->yres);
1202 		return 0;
1203 	}
1204 
1205 	if (mode->pixclock < 5000) {
1206 		pr_debug("%dx%d %dps pixel clock too fast",
1207 		       mode->xres, mode->yres, mode->pixclock);
1208 		return 0;
1209 	}
1210 
1211 	pr_debug("%dx%d (pixclk %dps %dMHz) valid mode", mode->xres, mode->yres,
1212 		mode->pixclock, (1000000 / mode->pixclock));
1213 	return 1;
1214 }
1215 
ufx_var_color_format(struct fb_var_screeninfo * var)1216 static void ufx_var_color_format(struct fb_var_screeninfo *var)
1217 {
1218 	const struct fb_bitfield red = { 11, 5, 0 };
1219 	const struct fb_bitfield green = { 5, 6, 0 };
1220 	const struct fb_bitfield blue = { 0, 5, 0 };
1221 
1222 	var->bits_per_pixel = 16;
1223 	var->red = red;
1224 	var->green = green;
1225 	var->blue = blue;
1226 }
1227 
ufx_ops_check_var(struct fb_var_screeninfo * var,struct fb_info * info)1228 static int ufx_ops_check_var(struct fb_var_screeninfo *var,
1229 				struct fb_info *info)
1230 {
1231 	struct fb_videomode mode;
1232 
1233 	/* TODO: support dynamically changing framebuffer size */
1234 	if ((var->xres * var->yres * 2) > info->fix.smem_len)
1235 		return -EINVAL;
1236 
1237 	/* set device-specific elements of var unrelated to mode */
1238 	ufx_var_color_format(var);
1239 
1240 	fb_var_to_videomode(&mode, var);
1241 
1242 	if (!ufx_is_valid_mode(&mode, info))
1243 		return -EINVAL;
1244 
1245 	return 0;
1246 }
1247 
ufx_ops_set_par(struct fb_info * info)1248 static int ufx_ops_set_par(struct fb_info *info)
1249 {
1250 	struct ufx_data *dev = info->par;
1251 	int result;
1252 	u16 *pix_framebuffer;
1253 	int i;
1254 
1255 	pr_debug("set_par mode %dx%d", info->var.xres, info->var.yres);
1256 	result = ufx_set_vid_mode(dev, &info->var);
1257 
1258 	if ((result == 0) && (dev->fb_count == 0)) {
1259 		/* paint greenscreen */
1260 		pix_framebuffer = (u16 *) info->screen_base;
1261 		for (i = 0; i < info->fix.smem_len / 2; i++)
1262 			pix_framebuffer[i] = 0x37e6;
1263 
1264 		ufx_handle_damage(dev, 0, 0, info->var.xres, info->var.yres);
1265 	}
1266 
1267 	/* re-enable defio if previously disabled by damage tracking */
1268 	if (info->fbdefio)
1269 		info->fbdefio->delay = UFX_DEFIO_WRITE_DELAY;
1270 
1271 	return result;
1272 }
1273 
1274 /* In order to come back from full DPMS off, we need to set the mode again */
ufx_ops_blank(int blank_mode,struct fb_info * info)1275 static int ufx_ops_blank(int blank_mode, struct fb_info *info)
1276 {
1277 	struct ufx_data *dev = info->par;
1278 	ufx_set_vid_mode(dev, &info->var);
1279 	return 0;
1280 }
1281 
1282 static const struct fb_ops ufx_ops = {
1283 	.owner = THIS_MODULE,
1284 	.fb_read = fb_sys_read,
1285 	.fb_write = ufx_ops_write,
1286 	.fb_setcolreg = ufx_ops_setcolreg,
1287 	.fb_fillrect = ufx_ops_fillrect,
1288 	.fb_copyarea = ufx_ops_copyarea,
1289 	.fb_imageblit = ufx_ops_imageblit,
1290 	.fb_mmap = ufx_ops_mmap,
1291 	.fb_ioctl = ufx_ops_ioctl,
1292 	.fb_open = ufx_ops_open,
1293 	.fb_release = ufx_ops_release,
1294 	.fb_blank = ufx_ops_blank,
1295 	.fb_check_var = ufx_ops_check_var,
1296 	.fb_set_par = ufx_ops_set_par,
1297 	.fb_destroy = ufx_ops_destory,
1298 };
1299 
1300 /* Assumes &info->lock held by caller
1301  * Assumes no active clients have framebuffer open */
ufx_realloc_framebuffer(struct ufx_data * dev,struct fb_info * info)1302 static int ufx_realloc_framebuffer(struct ufx_data *dev, struct fb_info *info)
1303 {
1304 	int old_len = info->fix.smem_len;
1305 	int new_len;
1306 	unsigned char *old_fb = info->screen_base;
1307 	unsigned char *new_fb;
1308 
1309 	pr_debug("Reallocating framebuffer. Addresses will change!");
1310 
1311 	new_len = info->fix.line_length * info->var.yres;
1312 
1313 	if (PAGE_ALIGN(new_len) > old_len) {
1314 		/*
1315 		 * Alloc system memory for virtual framebuffer
1316 		 */
1317 		new_fb = vmalloc(new_len);
1318 		if (!new_fb)
1319 			return -ENOMEM;
1320 
1321 		if (info->screen_base) {
1322 			memcpy(new_fb, old_fb, old_len);
1323 			vfree(info->screen_base);
1324 		}
1325 
1326 		info->screen_base = new_fb;
1327 		info->fix.smem_len = PAGE_ALIGN(new_len);
1328 		info->fix.smem_start = (unsigned long) new_fb;
1329 		info->flags = smscufx_info_flags;
1330 	}
1331 	return 0;
1332 }
1333 
1334 /* sets up I2C Controller for 100 Kbps, std. speed, 7-bit addr, master,
1335  * restart enabled, but no start byte, enable controller */
ufx_i2c_init(struct ufx_data * dev)1336 static int ufx_i2c_init(struct ufx_data *dev)
1337 {
1338 	u32 tmp;
1339 
1340 	/* disable the controller before it can be reprogrammed */
1341 	int status = ufx_reg_write(dev, 0x106C, 0x00);
1342 	check_warn_return(status, "failed to disable I2C");
1343 
1344 	/* Setup the clock count registers
1345 	 * (12+1) = 13 clks @ 2.5 MHz = 5.2 uS */
1346 	status = ufx_reg_write(dev, 0x1018, 12);
1347 	check_warn_return(status, "error writing 0x1018");
1348 
1349 	/* (6+8) = 14 clks @ 2.5 MHz = 5.6 uS */
1350 	status = ufx_reg_write(dev, 0x1014, 6);
1351 	check_warn_return(status, "error writing 0x1014");
1352 
1353 	status = ufx_reg_read(dev, 0x1000, &tmp);
1354 	check_warn_return(status, "error reading 0x1000");
1355 
1356 	/* set speed to std mode */
1357 	tmp &= ~(0x06);
1358 	tmp |= 0x02;
1359 
1360 	/* 7-bit (not 10-bit) addressing */
1361 	tmp &= ~(0x10);
1362 
1363 	/* enable restart conditions and master mode */
1364 	tmp |= 0x21;
1365 
1366 	status = ufx_reg_write(dev, 0x1000, tmp);
1367 	check_warn_return(status, "error writing 0x1000");
1368 
1369 	/* Set normal tx using target address 0 */
1370 	status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0xC00, 0x000);
1371 	check_warn_return(status, "error setting TX mode bits in 0x1004");
1372 
1373 	/* Enable the controller */
1374 	status = ufx_reg_write(dev, 0x106C, 0x01);
1375 	check_warn_return(status, "failed to enable I2C");
1376 
1377 	return 0;
1378 }
1379 
1380 /* sets the I2C port mux and target address */
ufx_i2c_configure(struct ufx_data * dev)1381 static int ufx_i2c_configure(struct ufx_data *dev)
1382 {
1383 	int status = ufx_reg_write(dev, 0x106C, 0x00);
1384 	check_warn_return(status, "failed to disable I2C");
1385 
1386 	status = ufx_reg_write(dev, 0x3010, 0x00000000);
1387 	check_warn_return(status, "failed to write 0x3010");
1388 
1389 	/* A0h is std for any EDID, right shifted by one */
1390 	status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0x3FF,	(0xA0 >> 1));
1391 	check_warn_return(status, "failed to set TAR bits in 0x1004");
1392 
1393 	status = ufx_reg_write(dev, 0x106C, 0x01);
1394 	check_warn_return(status, "failed to enable I2C");
1395 
1396 	return 0;
1397 }
1398 
1399 /* wait for BUSY to clear, with a timeout of 50ms with 10ms sleeps. if no
1400  * monitor is connected, there is no error except for timeout */
ufx_i2c_wait_busy(struct ufx_data * dev)1401 static int ufx_i2c_wait_busy(struct ufx_data *dev)
1402 {
1403 	u32 tmp;
1404 	int i, status;
1405 
1406 	for (i = 0; i < 15; i++) {
1407 		status = ufx_reg_read(dev, 0x1100, &tmp);
1408 		check_warn_return(status, "0x1100 read failed");
1409 
1410 		/* if BUSY is clear, check for error */
1411 		if ((tmp & 0x80000000) == 0) {
1412 			if (tmp & 0x20000000) {
1413 				pr_warn("I2C read failed, 0x1100=0x%08x", tmp);
1414 				return -EIO;
1415 			}
1416 
1417 			return 0;
1418 		}
1419 
1420 		/* perform the first 10 retries without delay */
1421 		if (i >= 10)
1422 			msleep(10);
1423 	}
1424 
1425 	pr_warn("I2C access timed out, resetting I2C hardware");
1426 	status =  ufx_reg_write(dev, 0x1100, 0x40000000);
1427 	check_warn_return(status, "0x1100 write failed");
1428 
1429 	return -ETIMEDOUT;
1430 }
1431 
1432 /* reads a 128-byte EDID block from the currently selected port and TAR */
ufx_read_edid(struct ufx_data * dev,u8 * edid,int edid_len)1433 static int ufx_read_edid(struct ufx_data *dev, u8 *edid, int edid_len)
1434 {
1435 	int i, j, status;
1436 	u32 *edid_u32 = (u32 *)edid;
1437 
1438 	BUG_ON(edid_len != EDID_LENGTH);
1439 
1440 	status = ufx_i2c_configure(dev);
1441 	if (status < 0) {
1442 		pr_err("ufx_i2c_configure failed");
1443 		return status;
1444 	}
1445 
1446 	memset(edid, 0xff, EDID_LENGTH);
1447 
1448 	/* Read the 128-byte EDID as 2 bursts of 64 bytes */
1449 	for (i = 0; i < 2; i++) {
1450 		u32 temp = 0x28070000 | (63 << 20) | (((u32)(i * 64)) << 8);
1451 		status = ufx_reg_write(dev, 0x1100, temp);
1452 		check_warn_return(status, "Failed to write 0x1100");
1453 
1454 		temp |= 0x80000000;
1455 		status = ufx_reg_write(dev, 0x1100, temp);
1456 		check_warn_return(status, "Failed to write 0x1100");
1457 
1458 		status = ufx_i2c_wait_busy(dev);
1459 		check_warn_return(status, "Timeout waiting for I2C BUSY to clear");
1460 
1461 		for (j = 0; j < 16; j++) {
1462 			u32 data_reg_addr = 0x1110 + (j * 4);
1463 			status = ufx_reg_read(dev, data_reg_addr, edid_u32++);
1464 			check_warn_return(status, "Error reading i2c data");
1465 		}
1466 	}
1467 
1468 	/* all FF's in the first 16 bytes indicates nothing is connected */
1469 	for (i = 0; i < 16; i++) {
1470 		if (edid[i] != 0xFF) {
1471 			pr_debug("edid data read successfully");
1472 			return EDID_LENGTH;
1473 		}
1474 	}
1475 
1476 	pr_warn("edid data contains all 0xff");
1477 	return -ETIMEDOUT;
1478 }
1479 
1480 /* 1) use sw default
1481  * 2) Parse into various fb_info structs
1482  * 3) Allocate virtual framebuffer memory to back highest res mode
1483  *
1484  * Parses EDID into three places used by various parts of fbdev:
1485  * fb_var_screeninfo contains the timing of the monitor's preferred mode
1486  * fb_info.monspecs is full parsed EDID info, including monspecs.modedb
1487  * fb_info.modelist is a linked list of all monitor & VESA modes which work
1488  *
1489  * If EDID is not readable/valid, then modelist is all VESA modes,
1490  * monspecs is NULL, and fb_var_screeninfo is set to safe VESA mode
1491  * Returns 0 if successful */
ufx_setup_modes(struct ufx_data * dev,struct fb_info * info,char * default_edid,size_t default_edid_size)1492 static int ufx_setup_modes(struct ufx_data *dev, struct fb_info *info,
1493 	char *default_edid, size_t default_edid_size)
1494 {
1495 	const struct fb_videomode *default_vmode = NULL;
1496 	u8 *edid;
1497 	int i, result = 0, tries = 3;
1498 
1499 	if (info->dev) /* only use mutex if info has been registered */
1500 		mutex_lock(&info->lock);
1501 
1502 	edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
1503 	if (!edid) {
1504 		result = -ENOMEM;
1505 		goto error;
1506 	}
1507 
1508 	fb_destroy_modelist(&info->modelist);
1509 	memset(&info->monspecs, 0, sizeof(info->monspecs));
1510 
1511 	/* Try to (re)read EDID from hardware first
1512 	 * EDID data may return, but not parse as valid
1513 	 * Try again a few times, in case of e.g. analog cable noise */
1514 	while (tries--) {
1515 		i = ufx_read_edid(dev, edid, EDID_LENGTH);
1516 
1517 		if (i >= EDID_LENGTH)
1518 			fb_edid_to_monspecs(edid, &info->monspecs);
1519 
1520 		if (info->monspecs.modedb_len > 0) {
1521 			dev->edid = edid;
1522 			dev->edid_size = i;
1523 			break;
1524 		}
1525 	}
1526 
1527 	/* If that fails, use a previously returned EDID if available */
1528 	if (info->monspecs.modedb_len == 0) {
1529 		pr_err("Unable to get valid EDID from device/display\n");
1530 
1531 		if (dev->edid) {
1532 			fb_edid_to_monspecs(dev->edid, &info->monspecs);
1533 			if (info->monspecs.modedb_len > 0)
1534 				pr_err("Using previously queried EDID\n");
1535 		}
1536 	}
1537 
1538 	/* If that fails, use the default EDID we were handed */
1539 	if (info->monspecs.modedb_len == 0) {
1540 		if (default_edid_size >= EDID_LENGTH) {
1541 			fb_edid_to_monspecs(default_edid, &info->monspecs);
1542 			if (info->monspecs.modedb_len > 0) {
1543 				memcpy(edid, default_edid, default_edid_size);
1544 				dev->edid = edid;
1545 				dev->edid_size = default_edid_size;
1546 				pr_err("Using default/backup EDID\n");
1547 			}
1548 		}
1549 	}
1550 
1551 	/* If we've got modes, let's pick a best default mode */
1552 	if (info->monspecs.modedb_len > 0) {
1553 
1554 		for (i = 0; i < info->monspecs.modedb_len; i++) {
1555 			if (ufx_is_valid_mode(&info->monspecs.modedb[i], info))
1556 				fb_add_videomode(&info->monspecs.modedb[i],
1557 					&info->modelist);
1558 			else /* if we've removed top/best mode */
1559 				info->monspecs.misc &= ~FB_MISC_1ST_DETAIL;
1560 		}
1561 
1562 		default_vmode = fb_find_best_display(&info->monspecs,
1563 						     &info->modelist);
1564 	}
1565 
1566 	/* If everything else has failed, fall back to safe default mode */
1567 	if (default_vmode == NULL) {
1568 
1569 		struct fb_videomode fb_vmode = {0};
1570 
1571 		/* Add the standard VESA modes to our modelist
1572 		 * Since we don't have EDID, there may be modes that
1573 		 * overspec monitor and/or are incorrect aspect ratio, etc.
1574 		 * But at least the user has a chance to choose
1575 		 */
1576 		for (i = 0; i < VESA_MODEDB_SIZE; i++) {
1577 			if (ufx_is_valid_mode((struct fb_videomode *)
1578 						&vesa_modes[i], info))
1579 				fb_add_videomode(&vesa_modes[i],
1580 						 &info->modelist);
1581 		}
1582 
1583 		/* default to resolution safe for projectors
1584 		 * (since they are most common case without EDID)
1585 		 */
1586 		fb_vmode.xres = 800;
1587 		fb_vmode.yres = 600;
1588 		fb_vmode.refresh = 60;
1589 		default_vmode = fb_find_nearest_mode(&fb_vmode,
1590 						     &info->modelist);
1591 	}
1592 
1593 	/* If we have good mode and no active clients */
1594 	if ((default_vmode != NULL) && (dev->fb_count == 0)) {
1595 
1596 		fb_videomode_to_var(&info->var, default_vmode);
1597 		ufx_var_color_format(&info->var);
1598 
1599 		/* with mode size info, we can now alloc our framebuffer */
1600 		memcpy(&info->fix, &ufx_fix, sizeof(ufx_fix));
1601 		info->fix.line_length = info->var.xres *
1602 			(info->var.bits_per_pixel / 8);
1603 
1604 		result = ufx_realloc_framebuffer(dev, info);
1605 
1606 	} else
1607 		result = -EINVAL;
1608 
1609 error:
1610 	if (edid && (dev->edid != edid))
1611 		kfree(edid);
1612 
1613 	if (info->dev)
1614 		mutex_unlock(&info->lock);
1615 
1616 	return result;
1617 }
1618 
ufx_usb_probe(struct usb_interface * interface,const struct usb_device_id * id)1619 static int ufx_usb_probe(struct usb_interface *interface,
1620 			const struct usb_device_id *id)
1621 {
1622 	struct usb_device *usbdev;
1623 	struct ufx_data *dev;
1624 	struct fb_info *info;
1625 	int retval;
1626 	u32 id_rev, fpga_rev;
1627 
1628 	/* usb initialization */
1629 	usbdev = interface_to_usbdev(interface);
1630 	BUG_ON(!usbdev);
1631 
1632 	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1633 	if (dev == NULL) {
1634 		dev_err(&usbdev->dev, "ufx_usb_probe: failed alloc of dev struct\n");
1635 		return -ENOMEM;
1636 	}
1637 
1638 	/* we need to wait for both usb and fbdev to spin down on disconnect */
1639 	kref_init(&dev->kref); /* matching kref_put in usb .disconnect fn */
1640 	kref_get(&dev->kref); /* matching kref_put in free_framebuffer_work */
1641 
1642 	dev->udev = usbdev;
1643 	dev->gdev = &usbdev->dev; /* our generic struct device * */
1644 	usb_set_intfdata(interface, dev);
1645 
1646 	dev_dbg(dev->gdev, "%s %s - serial #%s\n",
1647 		usbdev->manufacturer, usbdev->product, usbdev->serial);
1648 	dev_dbg(dev->gdev, "vid_%04x&pid_%04x&rev_%04x driver's ufx_data struct at %p\n",
1649 		le16_to_cpu(usbdev->descriptor.idVendor),
1650 		le16_to_cpu(usbdev->descriptor.idProduct),
1651 		le16_to_cpu(usbdev->descriptor.bcdDevice), dev);
1652 	dev_dbg(dev->gdev, "console enable=%d\n", console);
1653 	dev_dbg(dev->gdev, "fb_defio enable=%d\n", fb_defio);
1654 
1655 	if (!ufx_alloc_urb_list(dev, WRITES_IN_FLIGHT, MAX_TRANSFER)) {
1656 		dev_err(dev->gdev, "ufx_alloc_urb_list failed\n");
1657 		goto e_nomem;
1658 	}
1659 
1660 	/* We don't register a new USB class. Our client interface is fbdev */
1661 
1662 	/* allocates framebuffer driver structure, not framebuffer memory */
1663 	info = framebuffer_alloc(0, &usbdev->dev);
1664 	if (!info)
1665 		goto e_nomem;
1666 
1667 	dev->info = info;
1668 	info->par = dev;
1669 	info->pseudo_palette = dev->pseudo_palette;
1670 	info->fbops = &ufx_ops;
1671 	INIT_LIST_HEAD(&info->modelist);
1672 
1673 	retval = fb_alloc_cmap(&info->cmap, 256, 0);
1674 	if (retval < 0) {
1675 		dev_err(dev->gdev, "fb_alloc_cmap failed %x\n", retval);
1676 		goto destroy_modedb;
1677 	}
1678 
1679 	retval = ufx_reg_read(dev, 0x3000, &id_rev);
1680 	check_warn_goto_error(retval, "error %d reading 0x3000 register from device", retval);
1681 	dev_dbg(dev->gdev, "ID_REV register value 0x%08x", id_rev);
1682 
1683 	retval = ufx_reg_read(dev, 0x3004, &fpga_rev);
1684 	check_warn_goto_error(retval, "error %d reading 0x3004 register from device", retval);
1685 	dev_dbg(dev->gdev, "FPGA_REV register value 0x%08x", fpga_rev);
1686 
1687 	dev_dbg(dev->gdev, "resetting device");
1688 	retval = ufx_lite_reset(dev);
1689 	check_warn_goto_error(retval, "error %d resetting device", retval);
1690 
1691 	dev_dbg(dev->gdev, "configuring system clock");
1692 	retval = ufx_config_sys_clk(dev);
1693 	check_warn_goto_error(retval, "error %d configuring system clock", retval);
1694 
1695 	dev_dbg(dev->gdev, "configuring DDR2 controller");
1696 	retval = ufx_config_ddr2(dev);
1697 	check_warn_goto_error(retval, "error %d initialising DDR2 controller", retval);
1698 
1699 	dev_dbg(dev->gdev, "configuring I2C controller");
1700 	retval = ufx_i2c_init(dev);
1701 	check_warn_goto_error(retval, "error %d initialising I2C controller", retval);
1702 
1703 	dev_dbg(dev->gdev, "selecting display mode");
1704 	retval = ufx_setup_modes(dev, info, NULL, 0);
1705 	check_warn_goto_error(retval, "unable to find common mode for display and adapter");
1706 
1707 	retval = ufx_reg_set_bits(dev, 0x4000, 0x00000001);
1708 	check_warn_goto_error(retval, "error %d enabling graphics engine", retval);
1709 
1710 	/* ready to begin using device */
1711 	atomic_set(&dev->usb_active, 1);
1712 
1713 	dev_dbg(dev->gdev, "checking var");
1714 	retval = ufx_ops_check_var(&info->var, info);
1715 	check_warn_goto_error(retval, "error %d ufx_ops_check_var", retval);
1716 
1717 	dev_dbg(dev->gdev, "setting par");
1718 	retval = ufx_ops_set_par(info);
1719 	check_warn_goto_error(retval, "error %d ufx_ops_set_par", retval);
1720 
1721 	dev_dbg(dev->gdev, "registering framebuffer");
1722 	retval = register_framebuffer(info);
1723 	check_warn_goto_error(retval, "error %d register_framebuffer", retval);
1724 
1725 	dev_info(dev->gdev, "SMSC UDX USB device /dev/fb%d attached. %dx%d resolution."
1726 		" Using %dK framebuffer memory\n", info->node,
1727 		info->var.xres, info->var.yres, info->fix.smem_len >> 10);
1728 
1729 	return 0;
1730 
1731 error:
1732 	fb_dealloc_cmap(&info->cmap);
1733 destroy_modedb:
1734 	fb_destroy_modedb(info->monspecs.modedb);
1735 	vfree(info->screen_base);
1736 	fb_destroy_modelist(&info->modelist);
1737 	framebuffer_release(info);
1738 put_ref:
1739 	kref_put(&dev->kref, ufx_free); /* ref for framebuffer */
1740 	kref_put(&dev->kref, ufx_free); /* last ref from kref_init */
1741 	return retval;
1742 
1743 e_nomem:
1744 	retval = -ENOMEM;
1745 	goto put_ref;
1746 }
1747 
ufx_usb_disconnect(struct usb_interface * interface)1748 static void ufx_usb_disconnect(struct usb_interface *interface)
1749 {
1750 	struct ufx_data *dev;
1751 	struct fb_info *info;
1752 
1753 	mutex_lock(&disconnect_mutex);
1754 
1755 	dev = usb_get_intfdata(interface);
1756 	info = dev->info;
1757 
1758 	pr_debug("USB disconnect starting\n");
1759 
1760 	/* we virtualize until all fb clients release. Then we free */
1761 	dev->virtualized = true;
1762 
1763 	/* When non-active we'll update virtual framebuffer, but no new urbs */
1764 	atomic_set(&dev->usb_active, 0);
1765 
1766 	usb_set_intfdata(interface, NULL);
1767 
1768 	/* if clients still have us open, will be freed on last close */
1769 	if (dev->fb_count == 0)
1770 		ufx_free_framebuffer(dev);
1771 
1772 	/* this function will wait for all in-flight urbs to complete */
1773 	if (dev->urbs.count > 0)
1774 		ufx_free_urb_list(dev);
1775 
1776 	pr_debug("freeing ufx_data %p", dev);
1777 
1778 	unregister_framebuffer(info);
1779 
1780 	mutex_unlock(&disconnect_mutex);
1781 }
1782 
1783 static struct usb_driver ufx_driver = {
1784 	.name = "smscufx",
1785 	.probe = ufx_usb_probe,
1786 	.disconnect = ufx_usb_disconnect,
1787 	.id_table = id_table,
1788 };
1789 
1790 module_usb_driver(ufx_driver);
1791 
ufx_urb_completion(struct urb * urb)1792 static void ufx_urb_completion(struct urb *urb)
1793 {
1794 	struct urb_node *unode = urb->context;
1795 	struct ufx_data *dev = unode->dev;
1796 	unsigned long flags;
1797 
1798 	/* sync/async unlink faults aren't errors */
1799 	if (urb->status) {
1800 		if (!(urb->status == -ENOENT ||
1801 		    urb->status == -ECONNRESET ||
1802 		    urb->status == -ESHUTDOWN)) {
1803 			pr_err("%s - nonzero write bulk status received: %d\n",
1804 				__func__, urb->status);
1805 			atomic_set(&dev->lost_pixels, 1);
1806 		}
1807 	}
1808 
1809 	urb->transfer_buffer_length = dev->urbs.size; /* reset to actual */
1810 
1811 	spin_lock_irqsave(&dev->urbs.lock, flags);
1812 	list_add_tail(&unode->entry, &dev->urbs.list);
1813 	dev->urbs.available++;
1814 	spin_unlock_irqrestore(&dev->urbs.lock, flags);
1815 
1816 	/* When using fb_defio, we deadlock if up() is called
1817 	 * while another is waiting. So queue to another process */
1818 	if (fb_defio)
1819 		schedule_delayed_work(&unode->release_urb_work, 0);
1820 	else
1821 		up(&dev->urbs.limit_sem);
1822 }
1823 
ufx_free_urb_list(struct ufx_data * dev)1824 static void ufx_free_urb_list(struct ufx_data *dev)
1825 {
1826 	int count = dev->urbs.count;
1827 	struct list_head *node;
1828 	struct urb_node *unode;
1829 	struct urb *urb;
1830 	int ret;
1831 	unsigned long flags;
1832 
1833 	pr_debug("Waiting for completes and freeing all render urbs\n");
1834 
1835 	/* keep waiting and freeing, until we've got 'em all */
1836 	while (count--) {
1837 		/* Getting interrupted means a leak, but ok at shutdown*/
1838 		ret = down_interruptible(&dev->urbs.limit_sem);
1839 		if (ret)
1840 			break;
1841 
1842 		spin_lock_irqsave(&dev->urbs.lock, flags);
1843 
1844 		node = dev->urbs.list.next; /* have reserved one with sem */
1845 		list_del_init(node);
1846 
1847 		spin_unlock_irqrestore(&dev->urbs.lock, flags);
1848 
1849 		unode = list_entry(node, struct urb_node, entry);
1850 		urb = unode->urb;
1851 
1852 		/* Free each separately allocated piece */
1853 		usb_free_coherent(urb->dev, dev->urbs.size,
1854 				  urb->transfer_buffer, urb->transfer_dma);
1855 		usb_free_urb(urb);
1856 		kfree(node);
1857 	}
1858 }
1859 
ufx_alloc_urb_list(struct ufx_data * dev,int count,size_t size)1860 static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size)
1861 {
1862 	int i = 0;
1863 	struct urb *urb;
1864 	struct urb_node *unode;
1865 	char *buf;
1866 
1867 	spin_lock_init(&dev->urbs.lock);
1868 
1869 	dev->urbs.size = size;
1870 	INIT_LIST_HEAD(&dev->urbs.list);
1871 
1872 	while (i < count) {
1873 		unode = kzalloc(sizeof(*unode), GFP_KERNEL);
1874 		if (!unode)
1875 			break;
1876 		unode->dev = dev;
1877 
1878 		INIT_DELAYED_WORK(&unode->release_urb_work,
1879 			  ufx_release_urb_work);
1880 
1881 		urb = usb_alloc_urb(0, GFP_KERNEL);
1882 		if (!urb) {
1883 			kfree(unode);
1884 			break;
1885 		}
1886 		unode->urb = urb;
1887 
1888 		buf = usb_alloc_coherent(dev->udev, size, GFP_KERNEL,
1889 					 &urb->transfer_dma);
1890 		if (!buf) {
1891 			kfree(unode);
1892 			usb_free_urb(urb);
1893 			break;
1894 		}
1895 
1896 		/* urb->transfer_buffer_length set to actual before submit */
1897 		usb_fill_bulk_urb(urb, dev->udev, usb_sndbulkpipe(dev->udev, 1),
1898 			buf, size, ufx_urb_completion, unode);
1899 		urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
1900 
1901 		list_add_tail(&unode->entry, &dev->urbs.list);
1902 
1903 		i++;
1904 	}
1905 
1906 	sema_init(&dev->urbs.limit_sem, i);
1907 	dev->urbs.count = i;
1908 	dev->urbs.available = i;
1909 
1910 	pr_debug("allocated %d %d byte urbs\n", i, (int) size);
1911 
1912 	return i;
1913 }
1914 
ufx_get_urb(struct ufx_data * dev)1915 static struct urb *ufx_get_urb(struct ufx_data *dev)
1916 {
1917 	int ret = 0;
1918 	struct list_head *entry;
1919 	struct urb_node *unode;
1920 	struct urb *urb = NULL;
1921 	unsigned long flags;
1922 
1923 	/* Wait for an in-flight buffer to complete and get re-queued */
1924 	ret = down_timeout(&dev->urbs.limit_sem, GET_URB_TIMEOUT);
1925 	if (ret) {
1926 		atomic_set(&dev->lost_pixels, 1);
1927 		pr_warn("wait for urb interrupted: %x available: %d\n",
1928 		       ret, dev->urbs.available);
1929 		goto error;
1930 	}
1931 
1932 	spin_lock_irqsave(&dev->urbs.lock, flags);
1933 
1934 	BUG_ON(list_empty(&dev->urbs.list)); /* reserved one with limit_sem */
1935 	entry = dev->urbs.list.next;
1936 	list_del_init(entry);
1937 	dev->urbs.available--;
1938 
1939 	spin_unlock_irqrestore(&dev->urbs.lock, flags);
1940 
1941 	unode = list_entry(entry, struct urb_node, entry);
1942 	urb = unode->urb;
1943 
1944 error:
1945 	return urb;
1946 }
1947 
ufx_submit_urb(struct ufx_data * dev,struct urb * urb,size_t len)1948 static int ufx_submit_urb(struct ufx_data *dev, struct urb *urb, size_t len)
1949 {
1950 	int ret;
1951 
1952 	BUG_ON(len > dev->urbs.size);
1953 
1954 	urb->transfer_buffer_length = len; /* set to actual payload len */
1955 	ret = usb_submit_urb(urb, GFP_KERNEL);
1956 	if (ret) {
1957 		ufx_urb_completion(urb); /* because no one else will */
1958 		atomic_set(&dev->lost_pixels, 1);
1959 		pr_err("usb_submit_urb error %x\n", ret);
1960 	}
1961 	return ret;
1962 }
1963 
1964 module_param(console, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP);
1965 MODULE_PARM_DESC(console, "Allow fbcon to be used on this display");
1966 
1967 module_param(fb_defio, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP);
1968 MODULE_PARM_DESC(fb_defio, "Enable fb_defio mmap support");
1969 
1970 MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
1971 MODULE_DESCRIPTION("SMSC UFX kernel framebuffer driver");
1972 MODULE_LICENSE("GPL");
1973