1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek xHCI Host Controller Driver
4 *
5 * Copyright (c) 2015 MediaTek Inc.
6 * Author:
7 * Chunfeng Yun <chunfeng.yun@mediatek.com>
8 */
9
10 #include <linux/dma-mapping.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/pm_wakeirq.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/reset.h>
22
23 #include "xhci.h"
24 #include "xhci-mtk.h"
25
26 /* ip_pw_ctrl0 register */
27 #define CTRL0_IP_SW_RST BIT(0)
28
29 /* ip_pw_ctrl1 register */
30 #define CTRL1_IP_HOST_PDN BIT(0)
31
32 /* ip_pw_ctrl2 register */
33 #define CTRL2_IP_DEV_PDN BIT(0)
34
35 /* ip_pw_sts1 register */
36 #define STS1_IP_SLEEP_STS BIT(30)
37 #define STS1_U3_MAC_RST BIT(16)
38 #define STS1_XHCI_RST BIT(11)
39 #define STS1_SYS125_RST BIT(10)
40 #define STS1_REF_RST BIT(8)
41 #define STS1_SYSPLL_STABLE BIT(0)
42
43 /* ip_xhci_cap register */
44 #define CAP_U3_PORT_NUM(p) ((p) & 0xff)
45 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
46
47 /* u3_ctrl_p register */
48 #define CTRL_U3_PORT_HOST_SEL BIT(2)
49 #define CTRL_U3_PORT_PDN BIT(1)
50 #define CTRL_U3_PORT_DIS BIT(0)
51
52 /* u2_ctrl_p register */
53 #define CTRL_U2_PORT_HOST_SEL BIT(2)
54 #define CTRL_U2_PORT_PDN BIT(1)
55 #define CTRL_U2_PORT_DIS BIT(0)
56
57 /* u2_phy_pll register */
58 #define CTRL_U2_FORCE_PLL_STB BIT(28)
59
60 /* xHCI CSR */
61 #define LS_EOF_CFG 0x930
62 #define LSEOF_OFFSET 0x89
63
64 #define FS_EOF_CFG 0x934
65 #define FSEOF_OFFSET 0x2e
66
67 #define SS_GEN1_EOF_CFG 0x93c
68 #define SSG1EOF_OFFSET 0x78
69
70 #define HFCNTR_CFG 0x944
71 #define ITP_DELTA_CLK (0xa << 1)
72 #define ITP_DELTA_CLK_MASK GENMASK(5, 1)
73 #define FRMCNT_LEV1_RANG (0x12b << 8)
74 #define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8)
75
76 #define SS_GEN2_EOF_CFG 0x990
77 #define SSG2EOF_OFFSET 0x3c
78
79 #define XSEOF_OFFSET_MASK GENMASK(11, 0)
80
81 /* usb remote wakeup registers in syscon */
82
83 /* mt8173 etc */
84 #define PERI_WK_CTRL1 0x4
85 #define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
86 #define WC1_IS_EN BIT(25)
87 #define WC1_IS_P BIT(6) /* polarity for ip sleep */
88
89 /* mt8183 */
90 #define PERI_WK_CTRL0 0x0
91 #define WC0_IS_C(x) ((u32)(((x) & 0xf) << 28)) /* cycle debounce */
92 #define WC0_IS_P BIT(12) /* polarity */
93 #define WC0_IS_EN BIT(6)
94
95 /* mt8192 */
96 #define WC0_SSUSB0_CDEN BIT(6)
97 #define WC0_IS_SPM_EN BIT(1)
98
99 /* mt8195 */
100 #define PERI_WK_CTRL0_8195 0x04
101 #define WC0_IS_P_95 BIT(30) /* polarity */
102 #define WC0_IS_C_95(x) ((u32)(((x) & 0x7) << 27))
103 #define WC0_IS_EN_P3_95 BIT(26)
104 #define WC0_IS_EN_P2_95 BIT(25)
105 #define WC0_IS_EN_P1_95 BIT(24)
106
107 #define PERI_WK_CTRL1_8195 0x20
108 #define WC1_IS_C_95(x) ((u32)(((x) & 0xf) << 28))
109 #define WC1_IS_P_95 BIT(12)
110 #define WC1_IS_EN_P0_95 BIT(6)
111
112 /* mt2712 etc */
113 #define PERI_SSUSB_SPM_CTRL 0x0
114 #define SSC_IP_SLEEP_EN BIT(4)
115 #define SSC_SPM_INT_EN BIT(1)
116
117 enum ssusb_uwk_vers {
118 SSUSB_UWK_V1 = 1,
119 SSUSB_UWK_V2,
120 SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */
121 SSUSB_UWK_V1_2, /* specific revision 1.2 */
122 SSUSB_UWK_V1_3, /* mt8195 IP0 */
123 SSUSB_UWK_V1_4, /* mt8195 IP1 */
124 SSUSB_UWK_V1_5, /* mt8195 IP2 */
125 SSUSB_UWK_V1_6, /* mt8195 IP3 */
126 };
127
128 /*
129 * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
130 * is calculated from the frame counter clock 24M, but in fact, the clock
131 * is 48M, add workaround for it.
132 */
xhci_mtk_set_frame_interval(struct xhci_hcd_mtk * mtk)133 static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk)
134 {
135 struct device *dev = mtk->dev;
136 struct usb_hcd *hcd = mtk->hcd;
137 u32 value;
138
139 if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci"))
140 return;
141
142 value = readl(hcd->regs + HFCNTR_CFG);
143 value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK);
144 value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
145 writel(value, hcd->regs + HFCNTR_CFG);
146
147 value = readl(hcd->regs + LS_EOF_CFG);
148 value &= ~XSEOF_OFFSET_MASK;
149 value |= LSEOF_OFFSET;
150 writel(value, hcd->regs + LS_EOF_CFG);
151
152 value = readl(hcd->regs + FS_EOF_CFG);
153 value &= ~XSEOF_OFFSET_MASK;
154 value |= FSEOF_OFFSET;
155 writel(value, hcd->regs + FS_EOF_CFG);
156
157 value = readl(hcd->regs + SS_GEN1_EOF_CFG);
158 value &= ~XSEOF_OFFSET_MASK;
159 value |= SSG1EOF_OFFSET;
160 writel(value, hcd->regs + SS_GEN1_EOF_CFG);
161
162 value = readl(hcd->regs + SS_GEN2_EOF_CFG);
163 value &= ~XSEOF_OFFSET_MASK;
164 value |= SSG2EOF_OFFSET;
165 writel(value, hcd->regs + SS_GEN2_EOF_CFG);
166 }
167
xhci_mtk_host_enable(struct xhci_hcd_mtk * mtk)168 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
169 {
170 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
171 u32 value, check_val;
172 int u3_ports_disabled = 0;
173 int ret;
174 int i;
175
176 if (!mtk->has_ippc)
177 return 0;
178
179 /* power on host ip */
180 value = readl(&ippc->ip_pw_ctr1);
181 value &= ~CTRL1_IP_HOST_PDN;
182 writel(value, &ippc->ip_pw_ctr1);
183
184 /* power on and enable u3 ports except skipped ones */
185 for (i = 0; i < mtk->num_u3_ports; i++) {
186 if ((0x1 << i) & mtk->u3p_dis_msk) {
187 u3_ports_disabled++;
188 continue;
189 }
190
191 value = readl(&ippc->u3_ctrl_p[i]);
192 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
193 value |= CTRL_U3_PORT_HOST_SEL;
194 writel(value, &ippc->u3_ctrl_p[i]);
195 }
196
197 /* power on and enable all u2 ports except skipped ones */
198 for (i = 0; i < mtk->num_u2_ports; i++) {
199 if (BIT(i) & mtk->u2p_dis_msk)
200 continue;
201
202 value = readl(&ippc->u2_ctrl_p[i]);
203 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
204 value |= CTRL_U2_PORT_HOST_SEL;
205 writel(value, &ippc->u2_ctrl_p[i]);
206 }
207
208 /*
209 * wait for clocks to be stable, and clock domains reset to
210 * be inactive after power on and enable ports
211 */
212 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
213 STS1_SYS125_RST | STS1_XHCI_RST;
214
215 if (mtk->num_u3_ports > u3_ports_disabled)
216 check_val |= STS1_U3_MAC_RST;
217
218 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
219 (check_val == (value & check_val)), 100, 20000);
220 if (ret) {
221 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
222 return ret;
223 }
224
225 return 0;
226 }
227
xhci_mtk_host_disable(struct xhci_hcd_mtk * mtk)228 static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
229 {
230 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
231 u32 value;
232 int ret;
233 int i;
234
235 if (!mtk->has_ippc)
236 return 0;
237
238 /* power down u3 ports except skipped ones */
239 for (i = 0; i < mtk->num_u3_ports; i++) {
240 if ((0x1 << i) & mtk->u3p_dis_msk)
241 continue;
242
243 value = readl(&ippc->u3_ctrl_p[i]);
244 value |= CTRL_U3_PORT_PDN;
245 writel(value, &ippc->u3_ctrl_p[i]);
246 }
247
248 /* power down all u2 ports except skipped ones */
249 for (i = 0; i < mtk->num_u2_ports; i++) {
250 if (BIT(i) & mtk->u2p_dis_msk)
251 continue;
252
253 value = readl(&ippc->u2_ctrl_p[i]);
254 value |= CTRL_U2_PORT_PDN;
255 writel(value, &ippc->u2_ctrl_p[i]);
256 }
257
258 /* power down host ip */
259 value = readl(&ippc->ip_pw_ctr1);
260 value |= CTRL1_IP_HOST_PDN;
261 writel(value, &ippc->ip_pw_ctr1);
262
263 /* wait for host ip to sleep */
264 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
265 (value & STS1_IP_SLEEP_STS), 100, 100000);
266 if (ret)
267 dev_err(mtk->dev, "ip sleep failed!!!\n");
268 else /* workaound for platforms using low level latch */
269 usleep_range(100, 200);
270
271 return ret;
272 }
273
xhci_mtk_ssusb_config(struct xhci_hcd_mtk * mtk)274 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
275 {
276 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
277 u32 value;
278
279 if (!mtk->has_ippc)
280 return 0;
281
282 /* reset whole ip */
283 value = readl(&ippc->ip_pw_ctr0);
284 value |= CTRL0_IP_SW_RST;
285 writel(value, &ippc->ip_pw_ctr0);
286 udelay(1);
287 value = readl(&ippc->ip_pw_ctr0);
288 value &= ~CTRL0_IP_SW_RST;
289 writel(value, &ippc->ip_pw_ctr0);
290
291 /*
292 * device ip is default power-on in fact
293 * power down device ip, otherwise ip-sleep will fail
294 */
295 value = readl(&ippc->ip_pw_ctr2);
296 value |= CTRL2_IP_DEV_PDN;
297 writel(value, &ippc->ip_pw_ctr2);
298
299 value = readl(&ippc->ip_xhci_cap);
300 mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
301 mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
302 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
303 mtk->num_u2_ports, mtk->num_u3_ports);
304
305 return xhci_mtk_host_enable(mtk);
306 }
307
308 /* only clocks can be turn off for ip-sleep wakeup mode */
usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk * mtk,bool enable)309 static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
310 {
311 u32 reg, msk, val;
312
313 switch (mtk->uwk_vers) {
314 case SSUSB_UWK_V1:
315 reg = mtk->uwk_reg_base + PERI_WK_CTRL1;
316 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
317 val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
318 break;
319 case SSUSB_UWK_V1_1:
320 reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
321 msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
322 val = enable ? (WC0_IS_EN | WC0_IS_C(0x1)) : 0;
323 break;
324 case SSUSB_UWK_V1_2:
325 reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
326 msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
327 val = enable ? msk : 0;
328 break;
329 case SSUSB_UWK_V1_3:
330 reg = mtk->uwk_reg_base + PERI_WK_CTRL1_8195;
331 msk = WC1_IS_EN_P0_95 | WC1_IS_C_95(0xf) | WC1_IS_P_95;
332 val = enable ? (WC1_IS_EN_P0_95 | WC1_IS_C_95(0x1)) : 0;
333 break;
334 case SSUSB_UWK_V1_4:
335 reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
336 msk = WC0_IS_EN_P1_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
337 val = enable ? (WC0_IS_EN_P1_95 | WC0_IS_C_95(0x1)) : 0;
338 break;
339 case SSUSB_UWK_V1_5:
340 reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
341 msk = WC0_IS_EN_P2_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
342 val = enable ? (WC0_IS_EN_P2_95 | WC0_IS_C_95(0x1)) : 0;
343 break;
344 case SSUSB_UWK_V1_6:
345 reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
346 msk = WC0_IS_EN_P3_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
347 val = enable ? (WC0_IS_EN_P3_95 | WC0_IS_C_95(0x1)) : 0;
348 break;
349 case SSUSB_UWK_V2:
350 reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
351 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
352 val = enable ? msk : 0;
353 break;
354 default:
355 return;
356 }
357 regmap_update_bits(mtk->uwk, reg, msk, val);
358 }
359
usb_wakeup_of_property_parse(struct xhci_hcd_mtk * mtk,struct device_node * dn)360 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
361 struct device_node *dn)
362 {
363 struct of_phandle_args args;
364 int ret;
365
366 /* Wakeup function is optional */
367 mtk->uwk_en = of_property_read_bool(dn, "wakeup-source");
368 if (!mtk->uwk_en)
369 return 0;
370
371 ret = of_parse_phandle_with_fixed_args(dn,
372 "mediatek,syscon-wakeup", 2, 0, &args);
373 if (ret)
374 return ret;
375
376 mtk->uwk_reg_base = args.args[0];
377 mtk->uwk_vers = args.args[1];
378 mtk->uwk = syscon_node_to_regmap(args.np);
379 of_node_put(args.np);
380 dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n",
381 mtk->uwk_reg_base, mtk->uwk_vers);
382
383 return PTR_ERR_OR_ZERO(mtk->uwk);
384 }
385
usb_wakeup_set(struct xhci_hcd_mtk * mtk,bool enable)386 static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable)
387 {
388 if (mtk->uwk_en)
389 usb_wakeup_ip_sleep_set(mtk, enable);
390 }
391
xhci_mtk_clks_get(struct xhci_hcd_mtk * mtk)392 static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
393 {
394 struct clk_bulk_data *clks = mtk->clks;
395
396 clks[0].id = "sys_ck";
397 clks[1].id = "xhci_ck";
398 clks[2].id = "ref_ck";
399 clks[3].id = "mcu_ck";
400 clks[4].id = "dma_ck";
401
402 return devm_clk_bulk_get_optional(mtk->dev, BULK_CLKS_NUM, clks);
403 }
404
xhci_mtk_vregs_get(struct xhci_hcd_mtk * mtk)405 static int xhci_mtk_vregs_get(struct xhci_hcd_mtk *mtk)
406 {
407 struct regulator_bulk_data *supplies = mtk->supplies;
408
409 supplies[0].supply = "vbus";
410 supplies[1].supply = "vusb33";
411
412 return devm_regulator_bulk_get(mtk->dev, BULK_VREGS_NUM, supplies);
413 }
414
xhci_mtk_quirks(struct device * dev,struct xhci_hcd * xhci)415 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
416 {
417 struct usb_hcd *hcd = xhci_to_hcd(xhci);
418 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
419
420 /*
421 * As of now platform drivers don't provide MSI support so we ensure
422 * here that the generic code does not try to make a pci_dev from our
423 * dev struct in order to setup MSI
424 */
425 xhci->quirks |= XHCI_PLAT;
426 xhci->quirks |= XHCI_MTK_HOST;
427 /*
428 * MTK host controller gives a spurious successful event after a
429 * short transfer. Ignore it.
430 */
431 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
432 if (mtk->lpm_support)
433 xhci->quirks |= XHCI_LPM_SUPPORT;
434 if (mtk->u2_lpm_disable)
435 xhci->quirks |= XHCI_HW_LPM_DISABLE;
436
437 /*
438 * MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream,
439 * and it's 3 when support it.
440 */
441 if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4)
442 xhci->quirks |= XHCI_BROKEN_STREAMS;
443 }
444
445 /* called during probe() after chip reset completes */
xhci_mtk_setup(struct usb_hcd * hcd)446 static int xhci_mtk_setup(struct usb_hcd *hcd)
447 {
448 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
449 int ret;
450
451 if (usb_hcd_is_primary_hcd(hcd)) {
452 ret = xhci_mtk_ssusb_config(mtk);
453 if (ret)
454 return ret;
455
456 /* workaround only for mt8195 */
457 xhci_mtk_set_frame_interval(mtk);
458 }
459
460 ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
461 if (ret)
462 return ret;
463
464 if (usb_hcd_is_primary_hcd(hcd))
465 ret = xhci_mtk_sch_init(mtk);
466
467 return ret;
468 }
469
470 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
471 .reset = xhci_mtk_setup,
472 .add_endpoint = xhci_mtk_add_ep,
473 .drop_endpoint = xhci_mtk_drop_ep,
474 .check_bandwidth = xhci_mtk_check_bandwidth,
475 .reset_bandwidth = xhci_mtk_reset_bandwidth,
476 };
477
478 static struct hc_driver __read_mostly xhci_mtk_hc_driver;
479
xhci_mtk_probe(struct platform_device * pdev)480 static int xhci_mtk_probe(struct platform_device *pdev)
481 {
482 struct device *dev = &pdev->dev;
483 struct device_node *node = dev->of_node;
484 struct xhci_hcd_mtk *mtk;
485 const struct hc_driver *driver;
486 struct xhci_hcd *xhci;
487 struct resource *res;
488 struct usb_hcd *hcd;
489 int ret = -ENODEV;
490 int wakeup_irq;
491 int irq;
492
493 if (usb_disabled())
494 return -ENODEV;
495
496 driver = &xhci_mtk_hc_driver;
497 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
498 if (!mtk)
499 return -ENOMEM;
500
501 mtk->dev = dev;
502
503 ret = xhci_mtk_vregs_get(mtk);
504 if (ret)
505 return dev_err_probe(dev, ret, "Failed to get regulators\n");
506
507 ret = xhci_mtk_clks_get(mtk);
508 if (ret)
509 return ret;
510
511 irq = platform_get_irq_byname_optional(pdev, "host");
512 if (irq < 0) {
513 if (irq == -EPROBE_DEFER)
514 return irq;
515
516 /* for backward compatibility */
517 irq = platform_get_irq(pdev, 0);
518 if (irq < 0)
519 return irq;
520 }
521
522 wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup");
523 if (wakeup_irq == -EPROBE_DEFER)
524 return wakeup_irq;
525
526 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
527 mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable");
528 /* optional property, ignore the error if it does not exist */
529 of_property_read_u32(node, "mediatek,u3p-dis-msk",
530 &mtk->u3p_dis_msk);
531 of_property_read_u32(node, "mediatek,u2p-dis-msk",
532 &mtk->u2p_dis_msk);
533
534 ret = usb_wakeup_of_property_parse(mtk, node);
535 if (ret) {
536 dev_err(dev, "failed to parse uwk property\n");
537 return ret;
538 }
539
540 pm_runtime_set_active(dev);
541 pm_runtime_use_autosuspend(dev);
542 pm_runtime_set_autosuspend_delay(dev, 4000);
543 pm_runtime_enable(dev);
544 pm_runtime_get_sync(dev);
545
546 ret = regulator_bulk_enable(BULK_VREGS_NUM, mtk->supplies);
547 if (ret)
548 goto disable_pm;
549
550 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
551 if (ret)
552 goto disable_ldos;
553
554 ret = device_reset_optional(dev);
555 if (ret) {
556 dev_err_probe(dev, ret, "failed to reset controller\n");
557 goto disable_clk;
558 }
559
560 hcd = usb_create_hcd(driver, dev, dev_name(dev));
561 if (!hcd) {
562 ret = -ENOMEM;
563 goto disable_clk;
564 }
565
566 /*
567 * USB 2.0 roothub is stored in the platform_device.
568 * Swap it with mtk HCD.
569 */
570 mtk->hcd = platform_get_drvdata(pdev);
571 platform_set_drvdata(pdev, mtk);
572
573 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
574 hcd->regs = devm_ioremap_resource(dev, res);
575 if (IS_ERR(hcd->regs)) {
576 ret = PTR_ERR(hcd->regs);
577 goto put_usb2_hcd;
578 }
579 hcd->rsrc_start = res->start;
580 hcd->rsrc_len = resource_size(res);
581
582 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
583 if (res) { /* ippc register is optional */
584 mtk->ippc_regs = devm_ioremap_resource(dev, res);
585 if (IS_ERR(mtk->ippc_regs)) {
586 ret = PTR_ERR(mtk->ippc_regs);
587 goto put_usb2_hcd;
588 }
589 mtk->has_ippc = true;
590 }
591
592 device_init_wakeup(dev, true);
593
594 xhci = hcd_to_xhci(hcd);
595 xhci->main_hcd = hcd;
596
597 /*
598 * imod_interval is the interrupt moderation value in nanoseconds.
599 * The increment interval is 8 times as much as that defined in
600 * the xHCI spec on MTK's controller.
601 */
602 xhci->imod_interval = 5000;
603 device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval);
604
605 xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
606 dev_name(dev), hcd);
607 if (!xhci->shared_hcd) {
608 ret = -ENOMEM;
609 goto disable_device_wakeup;
610 }
611
612 ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
613 if (ret)
614 goto put_usb3_hcd;
615
616 if (HCC_MAX_PSA(xhci->hcc_params) >= 4 &&
617 !(xhci->quirks & XHCI_BROKEN_STREAMS))
618 xhci->shared_hcd->can_do_streams = 1;
619
620 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
621 if (ret)
622 goto dealloc_usb2_hcd;
623
624 if (wakeup_irq > 0) {
625 ret = dev_pm_set_dedicated_wake_irq_reverse(dev, wakeup_irq);
626 if (ret) {
627 dev_err(dev, "set wakeup irq %d failed\n", wakeup_irq);
628 goto dealloc_usb3_hcd;
629 }
630 dev_info(dev, "wakeup irq %d\n", wakeup_irq);
631 }
632
633 device_enable_async_suspend(dev);
634 pm_runtime_mark_last_busy(dev);
635 pm_runtime_put_autosuspend(dev);
636 pm_runtime_forbid(dev);
637
638 return 0;
639
640 dealloc_usb3_hcd:
641 usb_remove_hcd(xhci->shared_hcd);
642 xhci->shared_hcd = NULL;
643
644 dealloc_usb2_hcd:
645 usb_remove_hcd(hcd);
646
647 put_usb3_hcd:
648 xhci_mtk_sch_exit(mtk);
649 usb_put_hcd(xhci->shared_hcd);
650
651 disable_device_wakeup:
652 device_init_wakeup(dev, false);
653
654 put_usb2_hcd:
655 usb_put_hcd(hcd);
656
657 disable_clk:
658 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
659
660 disable_ldos:
661 regulator_bulk_disable(BULK_VREGS_NUM, mtk->supplies);
662
663 disable_pm:
664 pm_runtime_put_noidle(dev);
665 pm_runtime_disable(dev);
666 return ret;
667 }
668
xhci_mtk_remove(struct platform_device * pdev)669 static int xhci_mtk_remove(struct platform_device *pdev)
670 {
671 struct xhci_hcd_mtk *mtk = platform_get_drvdata(pdev);
672 struct usb_hcd *hcd = mtk->hcd;
673 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
674 struct usb_hcd *shared_hcd = xhci->shared_hcd;
675 struct device *dev = &pdev->dev;
676
677 pm_runtime_get_sync(dev);
678 xhci->xhc_state |= XHCI_STATE_REMOVING;
679 dev_pm_clear_wake_irq(dev);
680 device_init_wakeup(dev, false);
681
682 usb_remove_hcd(shared_hcd);
683 xhci->shared_hcd = NULL;
684 usb_remove_hcd(hcd);
685 usb_put_hcd(shared_hcd);
686 usb_put_hcd(hcd);
687 xhci_mtk_sch_exit(mtk);
688 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
689 regulator_bulk_disable(BULK_VREGS_NUM, mtk->supplies);
690
691 pm_runtime_disable(dev);
692 pm_runtime_put_noidle(dev);
693 pm_runtime_set_suspended(dev);
694
695 return 0;
696 }
697
xhci_mtk_suspend(struct device * dev)698 static int __maybe_unused xhci_mtk_suspend(struct device *dev)
699 {
700 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
701 struct usb_hcd *hcd = mtk->hcd;
702 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
703 int ret;
704
705 xhci_dbg(xhci, "%s: stop port polling\n", __func__);
706 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
707 del_timer_sync(&hcd->rh_timer);
708 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
709 del_timer_sync(&xhci->shared_hcd->rh_timer);
710
711 ret = xhci_mtk_host_disable(mtk);
712 if (ret)
713 goto restart_poll_rh;
714
715 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
716 usb_wakeup_set(mtk, true);
717 return 0;
718
719 restart_poll_rh:
720 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
721 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
722 usb_hcd_poll_rh_status(xhci->shared_hcd);
723 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
724 usb_hcd_poll_rh_status(hcd);
725 return ret;
726 }
727
xhci_mtk_resume(struct device * dev)728 static int __maybe_unused xhci_mtk_resume(struct device *dev)
729 {
730 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
731 struct usb_hcd *hcd = mtk->hcd;
732 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
733 int ret;
734
735 usb_wakeup_set(mtk, false);
736 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
737 if (ret)
738 goto enable_wakeup;
739
740 ret = xhci_mtk_host_enable(mtk);
741 if (ret)
742 goto disable_clks;
743
744 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
745 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
746 usb_hcd_poll_rh_status(xhci->shared_hcd);
747 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
748 usb_hcd_poll_rh_status(hcd);
749 return 0;
750
751 disable_clks:
752 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
753 enable_wakeup:
754 usb_wakeup_set(mtk, true);
755 return ret;
756 }
757
xhci_mtk_runtime_suspend(struct device * dev)758 static int __maybe_unused xhci_mtk_runtime_suspend(struct device *dev)
759 {
760 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
761 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
762 int ret = 0;
763
764 if (xhci->xhc_state)
765 return -ESHUTDOWN;
766
767 if (device_may_wakeup(dev))
768 ret = xhci_mtk_suspend(dev);
769
770 /* -EBUSY: let PM automatically reschedule another autosuspend */
771 return ret ? -EBUSY : 0;
772 }
773
xhci_mtk_runtime_resume(struct device * dev)774 static int __maybe_unused xhci_mtk_runtime_resume(struct device *dev)
775 {
776 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
777 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
778 int ret = 0;
779
780 if (xhci->xhc_state)
781 return -ESHUTDOWN;
782
783 if (device_may_wakeup(dev))
784 ret = xhci_mtk_resume(dev);
785
786 return ret;
787 }
788
789 static const struct dev_pm_ops xhci_mtk_pm_ops = {
790 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
791 SET_RUNTIME_PM_OPS(xhci_mtk_runtime_suspend,
792 xhci_mtk_runtime_resume, NULL)
793 };
794
795 #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL)
796
797 static const struct of_device_id mtk_xhci_of_match[] = {
798 { .compatible = "mediatek,mt8173-xhci"},
799 { .compatible = "mediatek,mt8195-xhci"},
800 { .compatible = "mediatek,mtk-xhci"},
801 { },
802 };
803 MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
804
805 static struct platform_driver mtk_xhci_driver = {
806 .probe = xhci_mtk_probe,
807 .remove = xhci_mtk_remove,
808 .driver = {
809 .name = "xhci-mtk",
810 .pm = DEV_PM_OPS,
811 .of_match_table = mtk_xhci_of_match,
812 },
813 };
814
xhci_mtk_init(void)815 static int __init xhci_mtk_init(void)
816 {
817 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
818 return platform_driver_register(&mtk_xhci_driver);
819 }
820 module_init(xhci_mtk_init);
821
xhci_mtk_exit(void)822 static void __exit xhci_mtk_exit(void)
823 {
824 platform_driver_unregister(&mtk_xhci_driver);
825 }
826 module_exit(xhci_mtk_exit);
827
828 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
829 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
830 MODULE_LICENSE("GPL v2");
831
