1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/io.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/of.h>
26 #include <linux/of_graph.h>
27 #include <linux/acpi.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/reset.h>
30 #include <linux/bitfield.h>
31
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/of.h>
35 #include <linux/usb/otg.h>
36
37 #include "core.h"
38 #include "gadget.h"
39 #include "io.h"
40
41 #include "debug.h"
42
43 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
44
45 /**
46 * dwc3_get_dr_mode - Validates and sets dr_mode
47 * @dwc: pointer to our context structure
48 */
dwc3_get_dr_mode(struct dwc3 * dwc)49 static int dwc3_get_dr_mode(struct dwc3 *dwc)
50 {
51 enum usb_dr_mode mode;
52 struct device *dev = dwc->dev;
53 unsigned int hw_mode;
54
55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
56 dwc->dr_mode = USB_DR_MODE_OTG;
57
58 mode = dwc->dr_mode;
59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
60
61 switch (hw_mode) {
62 case DWC3_GHWPARAMS0_MODE_GADGET:
63 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
64 dev_err(dev,
65 "Controller does not support host mode.\n");
66 return -EINVAL;
67 }
68 mode = USB_DR_MODE_PERIPHERAL;
69 break;
70 case DWC3_GHWPARAMS0_MODE_HOST:
71 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
72 dev_err(dev,
73 "Controller does not support device mode.\n");
74 return -EINVAL;
75 }
76 mode = USB_DR_MODE_HOST;
77 break;
78 default:
79 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
80 mode = USB_DR_MODE_HOST;
81 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
82 mode = USB_DR_MODE_PERIPHERAL;
83
84 /*
85 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
86 * mode. If the controller supports DRD but the dr_mode is not
87 * specified or set to OTG, then set the mode to peripheral.
88 */
89 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
90 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
91 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
92 !DWC3_VER_IS_PRIOR(DWC3, 330A))
93 mode = USB_DR_MODE_PERIPHERAL;
94 }
95
96 if (mode != dwc->dr_mode) {
97 dev_warn(dev,
98 "Configuration mismatch. dr_mode forced to %s\n",
99 mode == USB_DR_MODE_HOST ? "host" : "gadget");
100
101 dwc->dr_mode = mode;
102 }
103
104 return 0;
105 }
106
dwc3_set_prtcap(struct dwc3 * dwc,u32 mode)107 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
108 {
109 u32 reg;
110
111 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
112 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
113 reg |= DWC3_GCTL_PRTCAPDIR(mode);
114 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
115
116 dwc->current_dr_role = mode;
117 }
118
__dwc3_set_mode(struct work_struct * work)119 static void __dwc3_set_mode(struct work_struct *work)
120 {
121 struct dwc3 *dwc = work_to_dwc(work);
122 unsigned long flags;
123 int ret;
124 u32 reg;
125
126 mutex_lock(&dwc->mutex);
127
128 pm_runtime_get_sync(dwc->dev);
129
130 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
131 dwc3_otg_update(dwc, 0);
132
133 if (!dwc->desired_dr_role)
134 goto out;
135
136 if (dwc->desired_dr_role == dwc->current_dr_role)
137 goto out;
138
139 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
140 goto out;
141
142 switch (dwc->current_dr_role) {
143 case DWC3_GCTL_PRTCAP_HOST:
144 dwc3_host_exit(dwc);
145 break;
146 case DWC3_GCTL_PRTCAP_DEVICE:
147 dwc3_gadget_exit(dwc);
148 dwc3_event_buffers_cleanup(dwc);
149 break;
150 case DWC3_GCTL_PRTCAP_OTG:
151 dwc3_otg_exit(dwc);
152 spin_lock_irqsave(&dwc->lock, flags);
153 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
154 spin_unlock_irqrestore(&dwc->lock, flags);
155 dwc3_otg_update(dwc, 1);
156 break;
157 default:
158 break;
159 }
160
161 /*
162 * When current_dr_role is not set, there's no role switching.
163 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
164 */
165 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
166 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
167 dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
168 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
169 reg |= DWC3_GCTL_CORESOFTRESET;
170 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
171
172 /*
173 * Wait for internal clocks to synchronized. DWC_usb31 and
174 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
175 * keep it consistent across different IPs, let's wait up to
176 * 100ms before clearing GCTL.CORESOFTRESET.
177 */
178 msleep(100);
179
180 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
181 reg &= ~DWC3_GCTL_CORESOFTRESET;
182 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
183 }
184
185 spin_lock_irqsave(&dwc->lock, flags);
186
187 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
188
189 spin_unlock_irqrestore(&dwc->lock, flags);
190
191 switch (dwc->desired_dr_role) {
192 case DWC3_GCTL_PRTCAP_HOST:
193 ret = dwc3_host_init(dwc);
194 if (ret) {
195 dev_err(dwc->dev, "failed to initialize host\n");
196 } else {
197 if (dwc->usb2_phy)
198 otg_set_vbus(dwc->usb2_phy->otg, true);
199 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
200 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
201 if (dwc->dis_split_quirk) {
202 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
203 reg |= DWC3_GUCTL3_SPLITDISABLE;
204 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
205 }
206 }
207 break;
208 case DWC3_GCTL_PRTCAP_DEVICE:
209 dwc3_core_soft_reset(dwc);
210
211 dwc3_event_buffers_setup(dwc);
212
213 if (dwc->usb2_phy)
214 otg_set_vbus(dwc->usb2_phy->otg, false);
215 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
216 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
217
218 ret = dwc3_gadget_init(dwc);
219 if (ret)
220 dev_err(dwc->dev, "failed to initialize peripheral\n");
221 break;
222 case DWC3_GCTL_PRTCAP_OTG:
223 dwc3_otg_init(dwc);
224 dwc3_otg_update(dwc, 0);
225 break;
226 default:
227 break;
228 }
229
230 out:
231 pm_runtime_mark_last_busy(dwc->dev);
232 pm_runtime_put_autosuspend(dwc->dev);
233 mutex_unlock(&dwc->mutex);
234 }
235
dwc3_set_mode(struct dwc3 * dwc,u32 mode)236 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
237 {
238 unsigned long flags;
239
240 if (dwc->dr_mode != USB_DR_MODE_OTG)
241 return;
242
243 spin_lock_irqsave(&dwc->lock, flags);
244 dwc->desired_dr_role = mode;
245 spin_unlock_irqrestore(&dwc->lock, flags);
246
247 queue_work(system_freezable_wq, &dwc->drd_work);
248 }
249
dwc3_core_fifo_space(struct dwc3_ep * dep,u8 type)250 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
251 {
252 struct dwc3 *dwc = dep->dwc;
253 u32 reg;
254
255 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
256 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
257 DWC3_GDBGFIFOSPACE_TYPE(type));
258
259 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
260
261 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
262 }
263
264 /**
265 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
266 * @dwc: pointer to our context structure
267 */
dwc3_core_soft_reset(struct dwc3 * dwc)268 int dwc3_core_soft_reset(struct dwc3 *dwc)
269 {
270 u32 reg;
271 int retries = 1000;
272
273 /*
274 * We're resetting only the device side because, if we're in host mode,
275 * XHCI driver will reset the host block. If dwc3 was configured for
276 * host-only mode, then we can return early.
277 */
278 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
279 return 0;
280
281 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
282 reg |= DWC3_DCTL_CSFTRST;
283 reg &= ~DWC3_DCTL_RUN_STOP;
284 dwc3_gadget_dctl_write_safe(dwc, reg);
285
286 /*
287 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
288 * is cleared only after all the clocks are synchronized. This can
289 * take a little more than 50ms. Set the polling rate at 20ms
290 * for 10 times instead.
291 */
292 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
293 retries = 10;
294
295 do {
296 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
297 if (!(reg & DWC3_DCTL_CSFTRST))
298 goto done;
299
300 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
301 msleep(20);
302 else
303 udelay(1);
304 } while (--retries);
305
306 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
307 return -ETIMEDOUT;
308
309 done:
310 /*
311 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
312 * is cleared, we must wait at least 50ms before accessing the PHY
313 * domain (synchronization delay).
314 */
315 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
316 msleep(50);
317
318 return 0;
319 }
320
321 /*
322 * dwc3_frame_length_adjustment - Adjusts frame length if required
323 * @dwc3: Pointer to our controller context structure
324 */
dwc3_frame_length_adjustment(struct dwc3 * dwc)325 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
326 {
327 u32 reg;
328 u32 dft;
329
330 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
331 return;
332
333 if (dwc->fladj == 0)
334 return;
335
336 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
337 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
338 if (dft != dwc->fladj) {
339 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
340 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
341 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
342 }
343 }
344
345 /**
346 * dwc3_ref_clk_period - Reference clock period configuration
347 * Default reference clock period depends on hardware
348 * configuration. For systems with reference clock that differs
349 * from the default, this will set clock period in DWC3_GUCTL
350 * register.
351 * @dwc: Pointer to our controller context structure
352 */
dwc3_ref_clk_period(struct dwc3 * dwc)353 static void dwc3_ref_clk_period(struct dwc3 *dwc)
354 {
355 unsigned long period;
356 unsigned long fladj;
357 unsigned long decr;
358 unsigned long rate;
359 u32 reg;
360
361 if (dwc->ref_clk) {
362 rate = clk_get_rate(dwc->ref_clk);
363 if (!rate)
364 return;
365 period = NSEC_PER_SEC / rate;
366 } else if (dwc->ref_clk_per) {
367 period = dwc->ref_clk_per;
368 rate = NSEC_PER_SEC / period;
369 } else {
370 return;
371 }
372
373 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
374 reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
375 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
376 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
377
378 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
379 return;
380
381 /*
382 * The calculation below is
383 *
384 * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
385 *
386 * but rearranged for fixed-point arithmetic. The division must be
387 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
388 * neither does rate * period).
389 *
390 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
391 * nanoseconds of error caused by the truncation which happened during
392 * the division when calculating rate or period (whichever one was
393 * derived from the other). We first calculate the relative error, then
394 * scale it to units of 8 ppm.
395 */
396 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
397 fladj -= 125000;
398
399 /*
400 * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
401 */
402 decr = 480000000 / rate;
403
404 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
405 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
406 & ~DWC3_GFLADJ_240MHZDECR
407 & ~DWC3_GFLADJ_240MHZDECR_PLS1;
408 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
409 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
410 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
411
412 if (dwc->gfladj_refclk_lpm_sel)
413 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL;
414
415 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
416 }
417
418 /**
419 * dwc3_free_one_event_buffer - Frees one event buffer
420 * @dwc: Pointer to our controller context structure
421 * @evt: Pointer to event buffer to be freed
422 */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)423 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
424 struct dwc3_event_buffer *evt)
425 {
426 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
427 }
428
429 /**
430 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
431 * @dwc: Pointer to our controller context structure
432 * @length: size of the event buffer
433 *
434 * Returns a pointer to the allocated event buffer structure on success
435 * otherwise ERR_PTR(errno).
436 */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned int length)437 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
438 unsigned int length)
439 {
440 struct dwc3_event_buffer *evt;
441
442 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
443 if (!evt)
444 return ERR_PTR(-ENOMEM);
445
446 evt->dwc = dwc;
447 evt->length = length;
448 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
449 if (!evt->cache)
450 return ERR_PTR(-ENOMEM);
451
452 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
453 &evt->dma, GFP_KERNEL);
454 if (!evt->buf)
455 return ERR_PTR(-ENOMEM);
456
457 return evt;
458 }
459
460 /**
461 * dwc3_free_event_buffers - frees all allocated event buffers
462 * @dwc: Pointer to our controller context structure
463 */
dwc3_free_event_buffers(struct dwc3 * dwc)464 static void dwc3_free_event_buffers(struct dwc3 *dwc)
465 {
466 struct dwc3_event_buffer *evt;
467
468 evt = dwc->ev_buf;
469 if (evt)
470 dwc3_free_one_event_buffer(dwc, evt);
471 }
472
473 /**
474 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
475 * @dwc: pointer to our controller context structure
476 * @length: size of event buffer
477 *
478 * Returns 0 on success otherwise negative errno. In the error case, dwc
479 * may contain some buffers allocated but not all which were requested.
480 */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned int length)481 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
482 {
483 struct dwc3_event_buffer *evt;
484
485 evt = dwc3_alloc_one_event_buffer(dwc, length);
486 if (IS_ERR(evt)) {
487 dev_err(dwc->dev, "can't allocate event buffer\n");
488 return PTR_ERR(evt);
489 }
490 dwc->ev_buf = evt;
491
492 return 0;
493 }
494
495 /**
496 * dwc3_event_buffers_setup - setup our allocated event buffers
497 * @dwc: pointer to our controller context structure
498 *
499 * Returns 0 on success otherwise negative errno.
500 */
dwc3_event_buffers_setup(struct dwc3 * dwc)501 int dwc3_event_buffers_setup(struct dwc3 *dwc)
502 {
503 struct dwc3_event_buffer *evt;
504
505 evt = dwc->ev_buf;
506 evt->lpos = 0;
507 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
508 lower_32_bits(evt->dma));
509 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
510 upper_32_bits(evt->dma));
511 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
512 DWC3_GEVNTSIZ_SIZE(evt->length));
513 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
514
515 return 0;
516 }
517
dwc3_event_buffers_cleanup(struct dwc3 * dwc)518 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
519 {
520 struct dwc3_event_buffer *evt;
521
522 evt = dwc->ev_buf;
523
524 evt->lpos = 0;
525
526 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
527 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
528 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
529 | DWC3_GEVNTSIZ_SIZE(0));
530 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
531 }
532
dwc3_alloc_scratch_buffers(struct dwc3 * dwc)533 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
534 {
535 if (!dwc->has_hibernation)
536 return 0;
537
538 if (!dwc->nr_scratch)
539 return 0;
540
541 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
542 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
543 if (!dwc->scratchbuf)
544 return -ENOMEM;
545
546 return 0;
547 }
548
dwc3_setup_scratch_buffers(struct dwc3 * dwc)549 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
550 {
551 dma_addr_t scratch_addr;
552 u32 param;
553 int ret;
554
555 if (!dwc->has_hibernation)
556 return 0;
557
558 if (!dwc->nr_scratch)
559 return 0;
560
561 /* should never fall here */
562 if (!WARN_ON(dwc->scratchbuf))
563 return 0;
564
565 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
566 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
567 DMA_BIDIRECTIONAL);
568 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
569 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
570 ret = -EFAULT;
571 goto err0;
572 }
573
574 dwc->scratch_addr = scratch_addr;
575
576 param = lower_32_bits(scratch_addr);
577
578 ret = dwc3_send_gadget_generic_command(dwc,
579 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
580 if (ret < 0)
581 goto err1;
582
583 param = upper_32_bits(scratch_addr);
584
585 ret = dwc3_send_gadget_generic_command(dwc,
586 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
587 if (ret < 0)
588 goto err1;
589
590 return 0;
591
592 err1:
593 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
594 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
595
596 err0:
597 return ret;
598 }
599
dwc3_free_scratch_buffers(struct dwc3 * dwc)600 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
601 {
602 if (!dwc->has_hibernation)
603 return;
604
605 if (!dwc->nr_scratch)
606 return;
607
608 /* should never fall here */
609 if (!WARN_ON(dwc->scratchbuf))
610 return;
611
612 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
613 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
614 kfree(dwc->scratchbuf);
615 }
616
dwc3_core_num_eps(struct dwc3 * dwc)617 static void dwc3_core_num_eps(struct dwc3 *dwc)
618 {
619 struct dwc3_hwparams *parms = &dwc->hwparams;
620
621 dwc->num_eps = DWC3_NUM_EPS(parms);
622 }
623
dwc3_cache_hwparams(struct dwc3 * dwc)624 static void dwc3_cache_hwparams(struct dwc3 *dwc)
625 {
626 struct dwc3_hwparams *parms = &dwc->hwparams;
627
628 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
629 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
630 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
631 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
632 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
633 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
634 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
635 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
636 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
637
638 if (DWC3_IP_IS(DWC32))
639 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
640 }
641
dwc3_core_ulpi_init(struct dwc3 * dwc)642 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
643 {
644 int intf;
645 int ret = 0;
646
647 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
648
649 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
650 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
651 dwc->hsphy_interface &&
652 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
653 ret = dwc3_ulpi_init(dwc);
654
655 return ret;
656 }
657
658 /**
659 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
660 * @dwc: Pointer to our controller context structure
661 *
662 * Returns 0 on success. The USB PHY interfaces are configured but not
663 * initialized. The PHY interfaces and the PHYs get initialized together with
664 * the core in dwc3_core_init.
665 */
dwc3_phy_setup(struct dwc3 * dwc)666 static int dwc3_phy_setup(struct dwc3 *dwc)
667 {
668 unsigned int hw_mode;
669 u32 reg;
670
671 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
672
673 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
674
675 /*
676 * Make sure UX_EXIT_PX is cleared as that causes issues with some
677 * PHYs. Also, this bit is not supposed to be used in normal operation.
678 */
679 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
680
681 /*
682 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
683 * to '0' during coreConsultant configuration. So default value
684 * will be '0' when the core is reset. Application needs to set it
685 * to '1' after the core initialization is completed.
686 */
687 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
688 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
689
690 /*
691 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
692 * power-on reset, and it can be set after core initialization, which is
693 * after device soft-reset during initialization.
694 */
695 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
696 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
697
698 if (dwc->u2ss_inp3_quirk)
699 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
700
701 if (dwc->dis_rxdet_inp3_quirk)
702 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
703
704 if (dwc->req_p1p2p3_quirk)
705 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
706
707 if (dwc->del_p1p2p3_quirk)
708 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
709
710 if (dwc->del_phy_power_chg_quirk)
711 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
712
713 if (dwc->lfps_filter_quirk)
714 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
715
716 if (dwc->rx_detect_poll_quirk)
717 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
718
719 if (dwc->tx_de_emphasis_quirk)
720 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
721
722 if (dwc->dis_u3_susphy_quirk)
723 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
724
725 if (dwc->dis_del_phy_power_chg_quirk)
726 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
727
728 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
729
730 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
731
732 /* Select the HS PHY interface */
733 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
734 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
735 if (dwc->hsphy_interface &&
736 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
737 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
738 break;
739 } else if (dwc->hsphy_interface &&
740 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
741 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
742 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
743 } else {
744 /* Relying on default value. */
745 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
746 break;
747 }
748 fallthrough;
749 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
750 default:
751 break;
752 }
753
754 switch (dwc->hsphy_mode) {
755 case USBPHY_INTERFACE_MODE_UTMI:
756 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
757 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
758 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
759 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
760 break;
761 case USBPHY_INTERFACE_MODE_UTMIW:
762 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
763 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
764 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
765 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
766 break;
767 default:
768 break;
769 }
770
771 /*
772 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
773 * '0' during coreConsultant configuration. So default value will
774 * be '0' when the core is reset. Application needs to set it to
775 * '1' after the core initialization is completed.
776 */
777 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
778 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
779
780 /*
781 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
782 * power-on reset, and it can be set after core initialization, which is
783 * after device soft-reset during initialization.
784 */
785 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
786 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
787
788 if (dwc->dis_u2_susphy_quirk)
789 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
790
791 if (dwc->dis_enblslpm_quirk)
792 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
793 else
794 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
795
796 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
797 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
798
799 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
800
801 return 0;
802 }
803
dwc3_clk_enable(struct dwc3 * dwc)804 static int dwc3_clk_enable(struct dwc3 *dwc)
805 {
806 int ret;
807
808 ret = clk_prepare_enable(dwc->bus_clk);
809 if (ret)
810 return ret;
811
812 ret = clk_prepare_enable(dwc->ref_clk);
813 if (ret)
814 goto disable_bus_clk;
815
816 ret = clk_prepare_enable(dwc->susp_clk);
817 if (ret)
818 goto disable_ref_clk;
819
820 return 0;
821
822 disable_ref_clk:
823 clk_disable_unprepare(dwc->ref_clk);
824 disable_bus_clk:
825 clk_disable_unprepare(dwc->bus_clk);
826 return ret;
827 }
828
dwc3_clk_disable(struct dwc3 * dwc)829 static void dwc3_clk_disable(struct dwc3 *dwc)
830 {
831 clk_disable_unprepare(dwc->susp_clk);
832 clk_disable_unprepare(dwc->ref_clk);
833 clk_disable_unprepare(dwc->bus_clk);
834 }
835
dwc3_core_exit(struct dwc3 * dwc)836 static void dwc3_core_exit(struct dwc3 *dwc)
837 {
838 dwc3_event_buffers_cleanup(dwc);
839
840 usb_phy_set_suspend(dwc->usb2_phy, 1);
841 usb_phy_set_suspend(dwc->usb3_phy, 1);
842 phy_power_off(dwc->usb2_generic_phy);
843 phy_power_off(dwc->usb3_generic_phy);
844
845 usb_phy_shutdown(dwc->usb2_phy);
846 usb_phy_shutdown(dwc->usb3_phy);
847 phy_exit(dwc->usb2_generic_phy);
848 phy_exit(dwc->usb3_generic_phy);
849
850 dwc3_clk_disable(dwc);
851 reset_control_assert(dwc->reset);
852 }
853
dwc3_core_is_valid(struct dwc3 * dwc)854 static bool dwc3_core_is_valid(struct dwc3 *dwc)
855 {
856 u32 reg;
857
858 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
859 dwc->ip = DWC3_GSNPS_ID(reg);
860
861 /* This should read as U3 followed by revision number */
862 if (DWC3_IP_IS(DWC3)) {
863 dwc->revision = reg;
864 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
865 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
866 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
867 } else {
868 return false;
869 }
870
871 return true;
872 }
873
dwc3_core_setup_global_control(struct dwc3 * dwc)874 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
875 {
876 u32 hwparams4 = dwc->hwparams.hwparams4;
877 u32 reg;
878
879 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
880 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
881
882 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
883 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
884 /**
885 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
886 * issue which would cause xHCI compliance tests to fail.
887 *
888 * Because of that we cannot enable clock gating on such
889 * configurations.
890 *
891 * Refers to:
892 *
893 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
894 * SOF/ITP Mode Used
895 */
896 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
897 dwc->dr_mode == USB_DR_MODE_OTG) &&
898 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
899 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
900 else
901 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
902 break;
903 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
904 /* enable hibernation here */
905 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
906
907 /*
908 * REVISIT Enabling this bit so that host-mode hibernation
909 * will work. Device-mode hibernation is not yet implemented.
910 */
911 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
912 break;
913 default:
914 /* nothing */
915 break;
916 }
917
918 /* check if current dwc3 is on simulation board */
919 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
920 dev_info(dwc->dev, "Running with FPGA optimizations\n");
921 dwc->is_fpga = true;
922 }
923
924 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
925 "disable_scramble cannot be used on non-FPGA builds\n");
926
927 if (dwc->disable_scramble_quirk && dwc->is_fpga)
928 reg |= DWC3_GCTL_DISSCRAMBLE;
929 else
930 reg &= ~DWC3_GCTL_DISSCRAMBLE;
931
932 if (dwc->u2exit_lfps_quirk)
933 reg |= DWC3_GCTL_U2EXIT_LFPS;
934
935 /*
936 * WORKAROUND: DWC3 revisions <1.90a have a bug
937 * where the device can fail to connect at SuperSpeed
938 * and falls back to high-speed mode which causes
939 * the device to enter a Connect/Disconnect loop
940 */
941 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
942 reg |= DWC3_GCTL_U2RSTECN;
943
944 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
945 }
946
947 static int dwc3_core_get_phy(struct dwc3 *dwc);
948 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
949
950 /* set global incr burst type configuration registers */
dwc3_set_incr_burst_type(struct dwc3 * dwc)951 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
952 {
953 struct device *dev = dwc->dev;
954 /* incrx_mode : for INCR burst type. */
955 bool incrx_mode;
956 /* incrx_size : for size of INCRX burst. */
957 u32 incrx_size;
958 u32 *vals;
959 u32 cfg;
960 int ntype;
961 int ret;
962 int i;
963
964 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
965
966 /*
967 * Handle property "snps,incr-burst-type-adjustment".
968 * Get the number of value from this property:
969 * result <= 0, means this property is not supported.
970 * result = 1, means INCRx burst mode supported.
971 * result > 1, means undefined length burst mode supported.
972 */
973 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
974 if (ntype <= 0)
975 return;
976
977 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
978 if (!vals)
979 return;
980
981 /* Get INCR burst type, and parse it */
982 ret = device_property_read_u32_array(dev,
983 "snps,incr-burst-type-adjustment", vals, ntype);
984 if (ret) {
985 kfree(vals);
986 dev_err(dev, "Error to get property\n");
987 return;
988 }
989
990 incrx_size = *vals;
991
992 if (ntype > 1) {
993 /* INCRX (undefined length) burst mode */
994 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
995 for (i = 1; i < ntype; i++) {
996 if (vals[i] > incrx_size)
997 incrx_size = vals[i];
998 }
999 } else {
1000 /* INCRX burst mode */
1001 incrx_mode = INCRX_BURST_MODE;
1002 }
1003
1004 kfree(vals);
1005
1006 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
1007 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
1008 if (incrx_mode)
1009 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1010 switch (incrx_size) {
1011 case 256:
1012 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1013 break;
1014 case 128:
1015 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1016 break;
1017 case 64:
1018 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1019 break;
1020 case 32:
1021 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1022 break;
1023 case 16:
1024 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1025 break;
1026 case 8:
1027 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1028 break;
1029 case 4:
1030 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1031 break;
1032 case 1:
1033 break;
1034 default:
1035 dev_err(dev, "Invalid property\n");
1036 break;
1037 }
1038
1039 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1040 }
1041
dwc3_set_power_down_clk_scale(struct dwc3 * dwc)1042 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1043 {
1044 u32 scale;
1045 u32 reg;
1046
1047 if (!dwc->susp_clk)
1048 return;
1049
1050 /*
1051 * The power down scale field specifies how many suspend_clk
1052 * periods fit into a 16KHz clock period. When performing
1053 * the division, round up the remainder.
1054 *
1055 * The power down scale value is calculated using the fastest
1056 * frequency of the suspend_clk. If it isn't fixed (but within
1057 * the accuracy requirement), the driver may not know the max
1058 * rate of the suspend_clk, so only update the power down scale
1059 * if the default is less than the calculated value from
1060 * clk_get_rate() or if the default is questionably high
1061 * (3x or more) to be within the requirement.
1062 */
1063 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1064 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1065 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1066 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1067 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1068 reg |= DWC3_GCTL_PWRDNSCALE(scale);
1069 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1070 }
1071 }
1072
1073 /**
1074 * dwc3_core_init - Low-level initialization of DWC3 Core
1075 * @dwc: Pointer to our controller context structure
1076 *
1077 * Returns 0 on success otherwise negative errno.
1078 */
dwc3_core_init(struct dwc3 * dwc)1079 static int dwc3_core_init(struct dwc3 *dwc)
1080 {
1081 unsigned int hw_mode;
1082 u32 reg;
1083 int ret;
1084
1085 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1086
1087 /*
1088 * Write Linux Version Code to our GUID register so it's easy to figure
1089 * out which kernel version a bug was found.
1090 */
1091 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1092
1093 ret = dwc3_phy_setup(dwc);
1094 if (ret)
1095 goto err0;
1096
1097 if (!dwc->ulpi_ready) {
1098 ret = dwc3_core_ulpi_init(dwc);
1099 if (ret)
1100 goto err0;
1101 dwc->ulpi_ready = true;
1102 }
1103
1104 if (!dwc->phys_ready) {
1105 ret = dwc3_core_get_phy(dwc);
1106 if (ret)
1107 goto err0a;
1108 dwc->phys_ready = true;
1109 }
1110
1111 usb_phy_init(dwc->usb2_phy);
1112 usb_phy_init(dwc->usb3_phy);
1113 ret = phy_init(dwc->usb2_generic_phy);
1114 if (ret < 0)
1115 goto err0a;
1116
1117 ret = phy_init(dwc->usb3_generic_phy);
1118 if (ret < 0) {
1119 phy_exit(dwc->usb2_generic_phy);
1120 goto err0a;
1121 }
1122
1123 ret = dwc3_core_soft_reset(dwc);
1124 if (ret)
1125 goto err1;
1126
1127 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
1128 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
1129 if (!dwc->dis_u3_susphy_quirk) {
1130 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1131 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1132 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1133 }
1134
1135 if (!dwc->dis_u2_susphy_quirk) {
1136 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1137 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1138 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1139 }
1140 }
1141
1142 dwc3_core_setup_global_control(dwc);
1143 dwc3_core_num_eps(dwc);
1144
1145 ret = dwc3_setup_scratch_buffers(dwc);
1146 if (ret)
1147 goto err1;
1148
1149 /* Set power down scale of suspend_clk */
1150 dwc3_set_power_down_clk_scale(dwc);
1151
1152 /* Adjust Frame Length */
1153 dwc3_frame_length_adjustment(dwc);
1154
1155 /* Adjust Reference Clock Period */
1156 dwc3_ref_clk_period(dwc);
1157
1158 dwc3_set_incr_burst_type(dwc);
1159
1160 usb_phy_set_suspend(dwc->usb2_phy, 0);
1161 usb_phy_set_suspend(dwc->usb3_phy, 0);
1162 ret = phy_power_on(dwc->usb2_generic_phy);
1163 if (ret < 0)
1164 goto err2;
1165
1166 ret = phy_power_on(dwc->usb3_generic_phy);
1167 if (ret < 0)
1168 goto err3;
1169
1170 ret = dwc3_event_buffers_setup(dwc);
1171 if (ret) {
1172 dev_err(dwc->dev, "failed to setup event buffers\n");
1173 goto err4;
1174 }
1175
1176 /*
1177 * ENDXFER polling is available on version 3.10a and later of
1178 * the DWC_usb3 controller. It is NOT available in the
1179 * DWC_usb31 controller.
1180 */
1181 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1182 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1183 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1184 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1185 }
1186
1187 /*
1188 * When configured in HOST mode, after issuing U3/L2 exit controller
1189 * fails to send proper CRC checksum in CRC5 feild. Because of this
1190 * behaviour Transaction Error is generated, resulting in reset and
1191 * re-enumeration of usb device attached. All the termsel, xcvrsel,
1192 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
1193 * will correct this problem. This option is to support certain
1194 * legacy ULPI PHYs.
1195 */
1196 if (dwc->resume_hs_terminations) {
1197 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1198 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
1199 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1200 }
1201
1202 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1203 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1204
1205 /*
1206 * Enable hardware control of sending remote wakeup
1207 * in HS when the device is in the L1 state.
1208 */
1209 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1210 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1211
1212 /*
1213 * Decouple USB 2.0 L1 & L2 events which will allow for
1214 * gadget driver to only receive U3/L2 suspend & wakeup
1215 * events and prevent the more frequent L1 LPM transitions
1216 * from interrupting the driver.
1217 */
1218 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1219 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1220
1221 if (dwc->dis_tx_ipgap_linecheck_quirk)
1222 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1223
1224 if (dwc->parkmode_disable_ss_quirk)
1225 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1226
1227 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1228 (dwc->maximum_speed == USB_SPEED_HIGH ||
1229 dwc->maximum_speed == USB_SPEED_FULL))
1230 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1231
1232 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1233 }
1234
1235 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1236 dwc->dr_mode == USB_DR_MODE_OTG) {
1237 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1238
1239 /*
1240 * Enable Auto retry Feature to make the controller operating in
1241 * Host mode on seeing transaction errors(CRC errors or internal
1242 * overrun scenerios) on IN transfers to reply to the device
1243 * with a non-terminating retry ACK (i.e, an ACK transcation
1244 * packet with Retry=1 & Nump != 0)
1245 */
1246 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1247
1248 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1249 }
1250
1251 /*
1252 * Must config both number of packets and max burst settings to enable
1253 * RX and/or TX threshold.
1254 */
1255 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1256 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1257 u8 rx_maxburst = dwc->rx_max_burst_prd;
1258 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1259 u8 tx_maxburst = dwc->tx_max_burst_prd;
1260
1261 if (rx_thr_num && rx_maxburst) {
1262 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1263 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1264
1265 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1266 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1267
1268 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1269 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1270
1271 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1272 }
1273
1274 if (tx_thr_num && tx_maxburst) {
1275 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1276 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1277
1278 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1279 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1280
1281 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1282 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1283
1284 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1285 }
1286 }
1287
1288 return 0;
1289
1290 err4:
1291 phy_power_off(dwc->usb3_generic_phy);
1292
1293 err3:
1294 phy_power_off(dwc->usb2_generic_phy);
1295
1296 err2:
1297 usb_phy_set_suspend(dwc->usb2_phy, 1);
1298 usb_phy_set_suspend(dwc->usb3_phy, 1);
1299
1300 err1:
1301 usb_phy_shutdown(dwc->usb2_phy);
1302 usb_phy_shutdown(dwc->usb3_phy);
1303 phy_exit(dwc->usb2_generic_phy);
1304 phy_exit(dwc->usb3_generic_phy);
1305
1306 err0a:
1307 dwc3_ulpi_exit(dwc);
1308
1309 err0:
1310 return ret;
1311 }
1312
dwc3_core_get_phy(struct dwc3 * dwc)1313 static int dwc3_core_get_phy(struct dwc3 *dwc)
1314 {
1315 struct device *dev = dwc->dev;
1316 struct device_node *node = dev->of_node;
1317 int ret;
1318
1319 if (node) {
1320 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1321 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1322 } else {
1323 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1324 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1325 }
1326
1327 if (IS_ERR(dwc->usb2_phy)) {
1328 ret = PTR_ERR(dwc->usb2_phy);
1329 if (ret == -ENXIO || ret == -ENODEV)
1330 dwc->usb2_phy = NULL;
1331 else
1332 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1333 }
1334
1335 if (IS_ERR(dwc->usb3_phy)) {
1336 ret = PTR_ERR(dwc->usb3_phy);
1337 if (ret == -ENXIO || ret == -ENODEV)
1338 dwc->usb3_phy = NULL;
1339 else
1340 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1341 }
1342
1343 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1344 if (IS_ERR(dwc->usb2_generic_phy)) {
1345 ret = PTR_ERR(dwc->usb2_generic_phy);
1346 if (ret == -ENOSYS || ret == -ENODEV)
1347 dwc->usb2_generic_phy = NULL;
1348 else
1349 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1350 }
1351
1352 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1353 if (IS_ERR(dwc->usb3_generic_phy)) {
1354 ret = PTR_ERR(dwc->usb3_generic_phy);
1355 if (ret == -ENOSYS || ret == -ENODEV)
1356 dwc->usb3_generic_phy = NULL;
1357 else
1358 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1359 }
1360
1361 return 0;
1362 }
1363
dwc3_core_init_mode(struct dwc3 * dwc)1364 static int dwc3_core_init_mode(struct dwc3 *dwc)
1365 {
1366 struct device *dev = dwc->dev;
1367 int ret;
1368
1369 switch (dwc->dr_mode) {
1370 case USB_DR_MODE_PERIPHERAL:
1371 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1372
1373 if (dwc->usb2_phy)
1374 otg_set_vbus(dwc->usb2_phy->otg, false);
1375 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1376 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1377
1378 ret = dwc3_gadget_init(dwc);
1379 if (ret)
1380 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1381 break;
1382 case USB_DR_MODE_HOST:
1383 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1384
1385 if (dwc->usb2_phy)
1386 otg_set_vbus(dwc->usb2_phy->otg, true);
1387 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1388 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1389
1390 ret = dwc3_host_init(dwc);
1391 if (ret)
1392 return dev_err_probe(dev, ret, "failed to initialize host\n");
1393 break;
1394 case USB_DR_MODE_OTG:
1395 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1396 ret = dwc3_drd_init(dwc);
1397 if (ret)
1398 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1399 break;
1400 default:
1401 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1402 return -EINVAL;
1403 }
1404
1405 return 0;
1406 }
1407
dwc3_core_exit_mode(struct dwc3 * dwc)1408 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1409 {
1410 switch (dwc->dr_mode) {
1411 case USB_DR_MODE_PERIPHERAL:
1412 dwc3_gadget_exit(dwc);
1413 break;
1414 case USB_DR_MODE_HOST:
1415 dwc3_host_exit(dwc);
1416 break;
1417 case USB_DR_MODE_OTG:
1418 dwc3_drd_exit(dwc);
1419 break;
1420 default:
1421 /* do nothing */
1422 break;
1423 }
1424
1425 /* de-assert DRVVBUS for HOST and OTG mode */
1426 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1427 }
1428
dwc3_get_properties(struct dwc3 * dwc)1429 static void dwc3_get_properties(struct dwc3 *dwc)
1430 {
1431 struct device *dev = dwc->dev;
1432 u8 lpm_nyet_threshold;
1433 u8 tx_de_emphasis;
1434 u8 hird_threshold;
1435 u8 rx_thr_num_pkt_prd = 0;
1436 u8 rx_max_burst_prd = 0;
1437 u8 tx_thr_num_pkt_prd = 0;
1438 u8 tx_max_burst_prd = 0;
1439 u8 tx_fifo_resize_max_num;
1440 const char *usb_psy_name;
1441 int ret;
1442
1443 /* default to highest possible threshold */
1444 lpm_nyet_threshold = 0xf;
1445
1446 /* default to -3.5dB de-emphasis */
1447 tx_de_emphasis = 1;
1448
1449 /*
1450 * default to assert utmi_sleep_n and use maximum allowed HIRD
1451 * threshold value of 0b1100
1452 */
1453 hird_threshold = 12;
1454
1455 /*
1456 * default to a TXFIFO size large enough to fit 6 max packets. This
1457 * allows for systems with larger bus latencies to have some headroom
1458 * for endpoints that have a large bMaxBurst value.
1459 */
1460 tx_fifo_resize_max_num = 6;
1461
1462 dwc->maximum_speed = usb_get_maximum_speed(dev);
1463 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1464 dwc->dr_mode = usb_get_dr_mode(dev);
1465 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1466
1467 dwc->sysdev_is_parent = device_property_read_bool(dev,
1468 "linux,sysdev_is_parent");
1469 if (dwc->sysdev_is_parent)
1470 dwc->sysdev = dwc->dev->parent;
1471 else
1472 dwc->sysdev = dwc->dev;
1473
1474 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1475 if (ret >= 0) {
1476 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1477 if (!dwc->usb_psy)
1478 dev_err(dev, "couldn't get usb power supply\n");
1479 }
1480
1481 dwc->has_lpm_erratum = device_property_read_bool(dev,
1482 "snps,has-lpm-erratum");
1483 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1484 &lpm_nyet_threshold);
1485 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1486 "snps,is-utmi-l1-suspend");
1487 device_property_read_u8(dev, "snps,hird-threshold",
1488 &hird_threshold);
1489 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1490 "snps,dis-start-transfer-quirk");
1491 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1492 "snps,usb3_lpm_capable");
1493 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1494 "snps,usb2-lpm-disable");
1495 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1496 "snps,usb2-gadget-lpm-disable");
1497 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1498 &rx_thr_num_pkt_prd);
1499 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1500 &rx_max_burst_prd);
1501 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1502 &tx_thr_num_pkt_prd);
1503 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1504 &tx_max_burst_prd);
1505 dwc->do_fifo_resize = device_property_read_bool(dev,
1506 "tx-fifo-resize");
1507 if (dwc->do_fifo_resize)
1508 device_property_read_u8(dev, "tx-fifo-max-num",
1509 &tx_fifo_resize_max_num);
1510
1511 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1512 "snps,disable_scramble_quirk");
1513 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1514 "snps,u2exit_lfps_quirk");
1515 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1516 "snps,u2ss_inp3_quirk");
1517 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1518 "snps,req_p1p2p3_quirk");
1519 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1520 "snps,del_p1p2p3_quirk");
1521 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1522 "snps,del_phy_power_chg_quirk");
1523 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1524 "snps,lfps_filter_quirk");
1525 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1526 "snps,rx_detect_poll_quirk");
1527 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1528 "snps,dis_u3_susphy_quirk");
1529 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1530 "snps,dis_u2_susphy_quirk");
1531 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1532 "snps,dis_enblslpm_quirk");
1533 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1534 "snps,dis-u1-entry-quirk");
1535 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1536 "snps,dis-u2-entry-quirk");
1537 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1538 "snps,dis_rxdet_inp3_quirk");
1539 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1540 "snps,dis-u2-freeclk-exists-quirk");
1541 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1542 "snps,dis-del-phy-power-chg-quirk");
1543 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1544 "snps,dis-tx-ipgap-linecheck-quirk");
1545 dwc->resume_hs_terminations = device_property_read_bool(dev,
1546 "snps,resume-hs-terminations");
1547 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1548 "snps,parkmode-disable-ss-quirk");
1549 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
1550 "snps,gfladj-refclk-lpm-sel-quirk");
1551
1552 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1553 "snps,tx_de_emphasis_quirk");
1554 device_property_read_u8(dev, "snps,tx_de_emphasis",
1555 &tx_de_emphasis);
1556 device_property_read_string(dev, "snps,hsphy_interface",
1557 &dwc->hsphy_interface);
1558 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1559 &dwc->fladj);
1560 device_property_read_u32(dev, "snps,ref-clock-period-ns",
1561 &dwc->ref_clk_per);
1562
1563 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1564 "snps,dis_metastability_quirk");
1565
1566 dwc->dis_split_quirk = device_property_read_bool(dev,
1567 "snps,dis-split-quirk");
1568
1569 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1570 dwc->tx_de_emphasis = tx_de_emphasis;
1571
1572 dwc->hird_threshold = hird_threshold;
1573
1574 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1575 dwc->rx_max_burst_prd = rx_max_burst_prd;
1576
1577 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1578 dwc->tx_max_burst_prd = tx_max_burst_prd;
1579
1580 dwc->imod_interval = 0;
1581
1582 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1583 }
1584
1585 /* check whether the core supports IMOD */
dwc3_has_imod(struct dwc3 * dwc)1586 bool dwc3_has_imod(struct dwc3 *dwc)
1587 {
1588 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1589 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1590 DWC3_IP_IS(DWC32);
1591 }
1592
dwc3_check_params(struct dwc3 * dwc)1593 static void dwc3_check_params(struct dwc3 *dwc)
1594 {
1595 struct device *dev = dwc->dev;
1596 unsigned int hwparam_gen =
1597 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1598
1599 /* Check for proper value of imod_interval */
1600 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1601 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1602 dwc->imod_interval = 0;
1603 }
1604
1605 /*
1606 * Workaround for STAR 9000961433 which affects only version
1607 * 3.00a of the DWC_usb3 core. This prevents the controller
1608 * interrupt from being masked while handling events. IMOD
1609 * allows us to work around this issue. Enable it for the
1610 * affected version.
1611 */
1612 if (!dwc->imod_interval &&
1613 DWC3_VER_IS(DWC3, 300A))
1614 dwc->imod_interval = 1;
1615
1616 /* Check the maximum_speed parameter */
1617 switch (dwc->maximum_speed) {
1618 case USB_SPEED_FULL:
1619 case USB_SPEED_HIGH:
1620 break;
1621 case USB_SPEED_SUPER:
1622 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1623 dev_warn(dev, "UDC doesn't support Gen 1\n");
1624 break;
1625 case USB_SPEED_SUPER_PLUS:
1626 if ((DWC3_IP_IS(DWC32) &&
1627 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1628 (!DWC3_IP_IS(DWC32) &&
1629 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1630 dev_warn(dev, "UDC doesn't support SSP\n");
1631 break;
1632 default:
1633 dev_err(dev, "invalid maximum_speed parameter %d\n",
1634 dwc->maximum_speed);
1635 fallthrough;
1636 case USB_SPEED_UNKNOWN:
1637 switch (hwparam_gen) {
1638 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1639 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1640 break;
1641 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1642 if (DWC3_IP_IS(DWC32))
1643 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1644 else
1645 dwc->maximum_speed = USB_SPEED_SUPER;
1646 break;
1647 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1648 dwc->maximum_speed = USB_SPEED_HIGH;
1649 break;
1650 default:
1651 dwc->maximum_speed = USB_SPEED_SUPER;
1652 break;
1653 }
1654 break;
1655 }
1656
1657 /*
1658 * Currently the controller does not have visibility into the HW
1659 * parameter to determine the maximum number of lanes the HW supports.
1660 * If the number of lanes is not specified in the device property, then
1661 * set the default to support dual-lane for DWC_usb32 and single-lane
1662 * for DWC_usb31 for super-speed-plus.
1663 */
1664 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1665 switch (dwc->max_ssp_rate) {
1666 case USB_SSP_GEN_2x1:
1667 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1668 dev_warn(dev, "UDC only supports Gen 1\n");
1669 break;
1670 case USB_SSP_GEN_1x2:
1671 case USB_SSP_GEN_2x2:
1672 if (DWC3_IP_IS(DWC31))
1673 dev_warn(dev, "UDC only supports single lane\n");
1674 break;
1675 case USB_SSP_GEN_UNKNOWN:
1676 default:
1677 switch (hwparam_gen) {
1678 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1679 if (DWC3_IP_IS(DWC32))
1680 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1681 else
1682 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1683 break;
1684 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1685 if (DWC3_IP_IS(DWC32))
1686 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1687 break;
1688 }
1689 break;
1690 }
1691 }
1692 }
1693
dwc3_get_extcon(struct dwc3 * dwc)1694 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1695 {
1696 struct device *dev = dwc->dev;
1697 struct device_node *np_phy;
1698 struct extcon_dev *edev = NULL;
1699 const char *name;
1700
1701 if (device_property_read_bool(dev, "extcon"))
1702 return extcon_get_edev_by_phandle(dev, 0);
1703
1704 /*
1705 * Device tree platforms should get extcon via phandle.
1706 * On ACPI platforms, we get the name from a device property.
1707 * This device property is for kernel internal use only and
1708 * is expected to be set by the glue code.
1709 */
1710 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1711 return extcon_get_extcon_dev(name);
1712
1713 /*
1714 * Check explicitly if "usb-role-switch" is used since
1715 * extcon_find_edev_by_node() can not be used to check the absence of
1716 * an extcon device. In the absence of an device it will always return
1717 * EPROBE_DEFER.
1718 */
1719 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) &&
1720 device_property_read_bool(dev, "usb-role-switch"))
1721 return NULL;
1722
1723 /*
1724 * Try to get an extcon device from the USB PHY controller's "port"
1725 * node. Check if it has the "port" node first, to avoid printing the
1726 * error message from underlying code, as it's a valid case: extcon
1727 * device (and "port" node) may be missing in case of "usb-role-switch"
1728 * or OTG mode.
1729 */
1730 np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1731 if (of_graph_is_present(np_phy)) {
1732 struct device_node *np_conn;
1733
1734 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1735 if (np_conn)
1736 edev = extcon_find_edev_by_node(np_conn);
1737 of_node_put(np_conn);
1738 }
1739 of_node_put(np_phy);
1740
1741 return edev;
1742 }
1743
dwc3_probe(struct platform_device * pdev)1744 static int dwc3_probe(struct platform_device *pdev)
1745 {
1746 struct device *dev = &pdev->dev;
1747 struct resource *res, dwc_res;
1748 struct dwc3 *dwc;
1749
1750 int ret;
1751
1752 void __iomem *regs;
1753
1754 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1755 if (!dwc)
1756 return -ENOMEM;
1757
1758 dwc->dev = dev;
1759
1760 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1761 if (!res) {
1762 dev_err(dev, "missing memory resource\n");
1763 return -ENODEV;
1764 }
1765
1766 dwc->xhci_resources[0].start = res->start;
1767 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1768 DWC3_XHCI_REGS_END;
1769 dwc->xhci_resources[0].flags = res->flags;
1770 dwc->xhci_resources[0].name = res->name;
1771
1772 /*
1773 * Request memory region but exclude xHCI regs,
1774 * since it will be requested by the xhci-plat driver.
1775 */
1776 dwc_res = *res;
1777 dwc_res.start += DWC3_GLOBALS_REGS_START;
1778
1779 regs = devm_ioremap_resource(dev, &dwc_res);
1780 if (IS_ERR(regs))
1781 return PTR_ERR(regs);
1782
1783 dwc->regs = regs;
1784 dwc->regs_size = resource_size(&dwc_res);
1785
1786 dwc3_get_properties(dwc);
1787
1788 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1789 if (IS_ERR(dwc->reset)) {
1790 ret = PTR_ERR(dwc->reset);
1791 goto put_usb_psy;
1792 }
1793
1794 if (dev->of_node) {
1795 /*
1796 * Clocks are optional, but new DT platforms should support all
1797 * clocks as required by the DT-binding.
1798 * Some devices have different clock names in legacy device trees,
1799 * check for them to retain backwards compatibility.
1800 */
1801 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1802 if (IS_ERR(dwc->bus_clk)) {
1803 ret = dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1804 "could not get bus clock\n");
1805 goto put_usb_psy;
1806 }
1807
1808 if (dwc->bus_clk == NULL) {
1809 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1810 if (IS_ERR(dwc->bus_clk)) {
1811 ret = dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1812 "could not get bus clock\n");
1813 goto put_usb_psy;
1814 }
1815 }
1816
1817 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1818 if (IS_ERR(dwc->ref_clk)) {
1819 ret = dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1820 "could not get ref clock\n");
1821 goto put_usb_psy;
1822 }
1823
1824 if (dwc->ref_clk == NULL) {
1825 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1826 if (IS_ERR(dwc->ref_clk)) {
1827 ret = dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1828 "could not get ref clock\n");
1829 goto put_usb_psy;
1830 }
1831 }
1832
1833 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1834 if (IS_ERR(dwc->susp_clk)) {
1835 ret = dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1836 "could not get suspend clock\n");
1837 goto put_usb_psy;
1838 }
1839
1840 if (dwc->susp_clk == NULL) {
1841 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1842 if (IS_ERR(dwc->susp_clk)) {
1843 ret = dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1844 "could not get suspend clock\n");
1845 goto put_usb_psy;
1846 }
1847 }
1848 }
1849
1850 ret = reset_control_deassert(dwc->reset);
1851 if (ret)
1852 goto put_usb_psy;
1853
1854 ret = dwc3_clk_enable(dwc);
1855 if (ret)
1856 goto assert_reset;
1857
1858 if (!dwc3_core_is_valid(dwc)) {
1859 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1860 ret = -ENODEV;
1861 goto disable_clks;
1862 }
1863
1864 platform_set_drvdata(pdev, dwc);
1865 dwc3_cache_hwparams(dwc);
1866
1867 if (!dwc->sysdev_is_parent &&
1868 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
1869 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1870 if (ret)
1871 goto disable_clks;
1872 }
1873
1874 spin_lock_init(&dwc->lock);
1875 mutex_init(&dwc->mutex);
1876
1877 pm_runtime_set_active(dev);
1878 pm_runtime_use_autosuspend(dev);
1879 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1880 pm_runtime_enable(dev);
1881 ret = pm_runtime_get_sync(dev);
1882 if (ret < 0)
1883 goto err1;
1884
1885 pm_runtime_forbid(dev);
1886
1887 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1888 if (ret) {
1889 dev_err(dwc->dev, "failed to allocate event buffers\n");
1890 ret = -ENOMEM;
1891 goto err2;
1892 }
1893
1894 dwc->edev = dwc3_get_extcon(dwc);
1895 if (IS_ERR(dwc->edev)) {
1896 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n");
1897 goto err3;
1898 }
1899
1900 ret = dwc3_get_dr_mode(dwc);
1901 if (ret)
1902 goto err3;
1903
1904 ret = dwc3_alloc_scratch_buffers(dwc);
1905 if (ret)
1906 goto err3;
1907
1908 ret = dwc3_core_init(dwc);
1909 if (ret) {
1910 dev_err_probe(dev, ret, "failed to initialize core\n");
1911 goto err4;
1912 }
1913
1914 dwc3_check_params(dwc);
1915 dwc3_debugfs_init(dwc);
1916
1917 ret = dwc3_core_init_mode(dwc);
1918 if (ret)
1919 goto err5;
1920
1921 pm_runtime_put(dev);
1922
1923 return 0;
1924
1925 err5:
1926 dwc3_debugfs_exit(dwc);
1927 dwc3_event_buffers_cleanup(dwc);
1928
1929 usb_phy_set_suspend(dwc->usb2_phy, 1);
1930 usb_phy_set_suspend(dwc->usb3_phy, 1);
1931 phy_power_off(dwc->usb2_generic_phy);
1932 phy_power_off(dwc->usb3_generic_phy);
1933
1934 usb_phy_shutdown(dwc->usb2_phy);
1935 usb_phy_shutdown(dwc->usb3_phy);
1936 phy_exit(dwc->usb2_generic_phy);
1937 phy_exit(dwc->usb3_generic_phy);
1938
1939 dwc3_ulpi_exit(dwc);
1940
1941 err4:
1942 dwc3_free_scratch_buffers(dwc);
1943
1944 err3:
1945 dwc3_free_event_buffers(dwc);
1946
1947 err2:
1948 pm_runtime_allow(&pdev->dev);
1949
1950 err1:
1951 pm_runtime_put_sync(&pdev->dev);
1952 pm_runtime_disable(&pdev->dev);
1953
1954 disable_clks:
1955 dwc3_clk_disable(dwc);
1956 assert_reset:
1957 reset_control_assert(dwc->reset);
1958 put_usb_psy:
1959 if (dwc->usb_psy)
1960 power_supply_put(dwc->usb_psy);
1961
1962 return ret;
1963 }
1964
dwc3_remove(struct platform_device * pdev)1965 static int dwc3_remove(struct platform_device *pdev)
1966 {
1967 struct dwc3 *dwc = platform_get_drvdata(pdev);
1968
1969 pm_runtime_get_sync(&pdev->dev);
1970
1971 dwc3_core_exit_mode(dwc);
1972 dwc3_debugfs_exit(dwc);
1973
1974 dwc3_core_exit(dwc);
1975 dwc3_ulpi_exit(dwc);
1976
1977 pm_runtime_disable(&pdev->dev);
1978 pm_runtime_put_noidle(&pdev->dev);
1979 pm_runtime_set_suspended(&pdev->dev);
1980
1981 dwc3_free_event_buffers(dwc);
1982 dwc3_free_scratch_buffers(dwc);
1983
1984 if (dwc->usb_psy)
1985 power_supply_put(dwc->usb_psy);
1986
1987 return 0;
1988 }
1989
1990 #ifdef CONFIG_PM
dwc3_core_init_for_resume(struct dwc3 * dwc)1991 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1992 {
1993 int ret;
1994
1995 ret = reset_control_deassert(dwc->reset);
1996 if (ret)
1997 return ret;
1998
1999 ret = dwc3_clk_enable(dwc);
2000 if (ret)
2001 goto assert_reset;
2002
2003 ret = dwc3_core_init(dwc);
2004 if (ret)
2005 goto disable_clks;
2006
2007 return 0;
2008
2009 disable_clks:
2010 dwc3_clk_disable(dwc);
2011 assert_reset:
2012 reset_control_assert(dwc->reset);
2013
2014 return ret;
2015 }
2016
dwc3_suspend_common(struct dwc3 * dwc,pm_message_t msg)2017 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
2018 {
2019 unsigned long flags;
2020 u32 reg;
2021
2022 switch (dwc->current_dr_role) {
2023 case DWC3_GCTL_PRTCAP_DEVICE:
2024 if (pm_runtime_suspended(dwc->dev))
2025 break;
2026 dwc3_gadget_suspend(dwc);
2027 synchronize_irq(dwc->irq_gadget);
2028 dwc3_core_exit(dwc);
2029 break;
2030 case DWC3_GCTL_PRTCAP_HOST:
2031 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2032 dwc3_core_exit(dwc);
2033 break;
2034 }
2035
2036 /* Let controller to suspend HSPHY before PHY driver suspends */
2037 if (dwc->dis_u2_susphy_quirk ||
2038 dwc->dis_enblslpm_quirk) {
2039 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2040 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
2041 DWC3_GUSB2PHYCFG_SUSPHY;
2042 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2043
2044 /* Give some time for USB2 PHY to suspend */
2045 usleep_range(5000, 6000);
2046 }
2047
2048 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
2049 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
2050 break;
2051 case DWC3_GCTL_PRTCAP_OTG:
2052 /* do nothing during runtime_suspend */
2053 if (PMSG_IS_AUTO(msg))
2054 break;
2055
2056 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2057 spin_lock_irqsave(&dwc->lock, flags);
2058 dwc3_gadget_suspend(dwc);
2059 spin_unlock_irqrestore(&dwc->lock, flags);
2060 synchronize_irq(dwc->irq_gadget);
2061 }
2062
2063 dwc3_otg_exit(dwc);
2064 dwc3_core_exit(dwc);
2065 break;
2066 default:
2067 /* do nothing */
2068 break;
2069 }
2070
2071 return 0;
2072 }
2073
dwc3_resume_common(struct dwc3 * dwc,pm_message_t msg)2074 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
2075 {
2076 unsigned long flags;
2077 int ret;
2078 u32 reg;
2079
2080 switch (dwc->current_dr_role) {
2081 case DWC3_GCTL_PRTCAP_DEVICE:
2082 ret = dwc3_core_init_for_resume(dwc);
2083 if (ret)
2084 return ret;
2085
2086 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2087 dwc3_gadget_resume(dwc);
2088 break;
2089 case DWC3_GCTL_PRTCAP_HOST:
2090 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2091 ret = dwc3_core_init_for_resume(dwc);
2092 if (ret)
2093 return ret;
2094 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2095 break;
2096 }
2097 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2098 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2099 if (dwc->dis_u2_susphy_quirk)
2100 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2101
2102 if (dwc->dis_enblslpm_quirk)
2103 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2104
2105 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2106
2107 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2108 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
2109 break;
2110 case DWC3_GCTL_PRTCAP_OTG:
2111 /* nothing to do on runtime_resume */
2112 if (PMSG_IS_AUTO(msg))
2113 break;
2114
2115 ret = dwc3_core_init_for_resume(dwc);
2116 if (ret)
2117 return ret;
2118
2119 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2120
2121 dwc3_otg_init(dwc);
2122 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2123 dwc3_otg_host_init(dwc);
2124 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2125 spin_lock_irqsave(&dwc->lock, flags);
2126 dwc3_gadget_resume(dwc);
2127 spin_unlock_irqrestore(&dwc->lock, flags);
2128 }
2129
2130 break;
2131 default:
2132 /* do nothing */
2133 break;
2134 }
2135
2136 return 0;
2137 }
2138
dwc3_runtime_checks(struct dwc3 * dwc)2139 static int dwc3_runtime_checks(struct dwc3 *dwc)
2140 {
2141 switch (dwc->current_dr_role) {
2142 case DWC3_GCTL_PRTCAP_DEVICE:
2143 if (dwc->connected)
2144 return -EBUSY;
2145 break;
2146 case DWC3_GCTL_PRTCAP_HOST:
2147 default:
2148 /* do nothing */
2149 break;
2150 }
2151
2152 return 0;
2153 }
2154
dwc3_runtime_suspend(struct device * dev)2155 static int dwc3_runtime_suspend(struct device *dev)
2156 {
2157 struct dwc3 *dwc = dev_get_drvdata(dev);
2158 int ret;
2159
2160 if (dwc3_runtime_checks(dwc))
2161 return -EBUSY;
2162
2163 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2164 if (ret)
2165 return ret;
2166
2167 return 0;
2168 }
2169
dwc3_runtime_resume(struct device * dev)2170 static int dwc3_runtime_resume(struct device *dev)
2171 {
2172 struct dwc3 *dwc = dev_get_drvdata(dev);
2173 int ret;
2174
2175 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2176 if (ret)
2177 return ret;
2178
2179 switch (dwc->current_dr_role) {
2180 case DWC3_GCTL_PRTCAP_DEVICE:
2181 dwc3_gadget_process_pending_events(dwc);
2182 break;
2183 case DWC3_GCTL_PRTCAP_HOST:
2184 default:
2185 /* do nothing */
2186 break;
2187 }
2188
2189 pm_runtime_mark_last_busy(dev);
2190
2191 return 0;
2192 }
2193
dwc3_runtime_idle(struct device * dev)2194 static int dwc3_runtime_idle(struct device *dev)
2195 {
2196 struct dwc3 *dwc = dev_get_drvdata(dev);
2197
2198 switch (dwc->current_dr_role) {
2199 case DWC3_GCTL_PRTCAP_DEVICE:
2200 if (dwc3_runtime_checks(dwc))
2201 return -EBUSY;
2202 break;
2203 case DWC3_GCTL_PRTCAP_HOST:
2204 default:
2205 /* do nothing */
2206 break;
2207 }
2208
2209 pm_runtime_mark_last_busy(dev);
2210 pm_runtime_autosuspend(dev);
2211
2212 return 0;
2213 }
2214 #endif /* CONFIG_PM */
2215
2216 #ifdef CONFIG_PM_SLEEP
dwc3_suspend(struct device * dev)2217 static int dwc3_suspend(struct device *dev)
2218 {
2219 struct dwc3 *dwc = dev_get_drvdata(dev);
2220 int ret;
2221
2222 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2223 if (ret)
2224 return ret;
2225
2226 pinctrl_pm_select_sleep_state(dev);
2227
2228 return 0;
2229 }
2230
dwc3_resume(struct device * dev)2231 static int dwc3_resume(struct device *dev)
2232 {
2233 struct dwc3 *dwc = dev_get_drvdata(dev);
2234 int ret;
2235
2236 pinctrl_pm_select_default_state(dev);
2237
2238 ret = dwc3_resume_common(dwc, PMSG_RESUME);
2239 if (ret)
2240 return ret;
2241
2242 pm_runtime_disable(dev);
2243 pm_runtime_set_active(dev);
2244 pm_runtime_enable(dev);
2245
2246 return 0;
2247 }
2248
dwc3_complete(struct device * dev)2249 static void dwc3_complete(struct device *dev)
2250 {
2251 struct dwc3 *dwc = dev_get_drvdata(dev);
2252 u32 reg;
2253
2254 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2255 dwc->dis_split_quirk) {
2256 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2257 reg |= DWC3_GUCTL3_SPLITDISABLE;
2258 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2259 }
2260 }
2261 #else
2262 #define dwc3_complete NULL
2263 #endif /* CONFIG_PM_SLEEP */
2264
2265 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2266 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2267 .complete = dwc3_complete,
2268 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2269 dwc3_runtime_idle)
2270 };
2271
2272 #ifdef CONFIG_OF
2273 static const struct of_device_id of_dwc3_match[] = {
2274 {
2275 .compatible = "snps,dwc3"
2276 },
2277 {
2278 .compatible = "synopsys,dwc3"
2279 },
2280 { },
2281 };
2282 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2283 #endif
2284
2285 #ifdef CONFIG_ACPI
2286
2287 #define ACPI_ID_INTEL_BSW "808622B7"
2288
2289 static const struct acpi_device_id dwc3_acpi_match[] = {
2290 { ACPI_ID_INTEL_BSW, 0 },
2291 { },
2292 };
2293 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2294 #endif
2295
2296 static struct platform_driver dwc3_driver = {
2297 .probe = dwc3_probe,
2298 .remove = dwc3_remove,
2299 .driver = {
2300 .name = "dwc3",
2301 .of_match_table = of_match_ptr(of_dwc3_match),
2302 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2303 .pm = &dwc3_dev_pm_ops,
2304 },
2305 };
2306
2307 module_platform_driver(dwc3_driver);
2308
2309 MODULE_ALIAS("platform:dwc3");
2310 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2311 MODULE_LICENSE("GPL v2");
2312 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
2313
