1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R-Car Gen1 RESET/WDT, R-Car Gen2, Gen3, and RZ/G RST Driver
4 *
5 * Copyright (C) 2016 Glider bvba
6 */
7
8 #include <linux/err.h>
9 #include <linux/io.h>
10 #include <linux/of_address.h>
11 #include <linux/soc/renesas/rcar-rst.h>
12
13 #define WDTRSTCR_RESET 0xA55A0002
14 #define WDTRSTCR 0x0054
15
16 #define CR7BAR 0x0070
17 #define CR7BAREN BIT(4)
18 #define CR7BAR_MASK 0xFFFC0000
19
20 static void __iomem *rcar_rst_base;
21 static u32 saved_mode __initdata;
22 static int (*rcar_rst_set_rproc_boot_addr_func)(u64 boot_addr);
23
rcar_rst_enable_wdt_reset(void __iomem * base)24 static int rcar_rst_enable_wdt_reset(void __iomem *base)
25 {
26 iowrite32(WDTRSTCR_RESET, base + WDTRSTCR);
27 return 0;
28 }
29
30 /*
31 * Most of the R-Car Gen3 SoCs have an ARM Realtime Core.
32 * Firmware boot address has to be set in CR7BAR before
33 * starting the realtime core.
34 * Boot address must be aligned on a 256k boundary.
35 */
rcar_rst_set_gen3_rproc_boot_addr(u64 boot_addr)36 static int rcar_rst_set_gen3_rproc_boot_addr(u64 boot_addr)
37 {
38 if (boot_addr & ~(u64)CR7BAR_MASK) {
39 pr_err("Invalid boot address got %llx\n", boot_addr);
40 return -EINVAL;
41 }
42
43 iowrite32(boot_addr, rcar_rst_base + CR7BAR);
44 iowrite32(boot_addr | CR7BAREN, rcar_rst_base + CR7BAR);
45
46 return 0;
47 }
48
49 struct rst_config {
50 unsigned int modemr; /* Mode Monitoring Register Offset */
51 int (*configure)(void __iomem *base); /* Platform specific config */
52 int (*set_rproc_boot_addr)(u64 boot_addr);
53 };
54
55 static const struct rst_config rcar_rst_gen1 __initconst = {
56 .modemr = 0x20,
57 };
58
59 static const struct rst_config rcar_rst_gen2 __initconst = {
60 .modemr = 0x60,
61 .configure = rcar_rst_enable_wdt_reset,
62 };
63
64 static const struct rst_config rcar_rst_gen3 __initconst = {
65 .modemr = 0x60,
66 .set_rproc_boot_addr = rcar_rst_set_gen3_rproc_boot_addr,
67 };
68
69 static const struct rst_config rcar_rst_gen4 __initconst = {
70 .modemr = 0x00, /* MODEMR0 and it has CPG related bits */
71 };
72
73 static const struct of_device_id rcar_rst_matches[] __initconst = {
74 /* RZ/G1 is handled like R-Car Gen2 */
75 { .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
76 { .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
77 { .compatible = "renesas,r8a7744-rst", .data = &rcar_rst_gen2 },
78 { .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
79 { .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
80 /* RZ/G2 is handled like R-Car Gen3 */
81 { .compatible = "renesas,r8a774a1-rst", .data = &rcar_rst_gen3 },
82 { .compatible = "renesas,r8a774b1-rst", .data = &rcar_rst_gen3 },
83 { .compatible = "renesas,r8a774c0-rst", .data = &rcar_rst_gen3 },
84 { .compatible = "renesas,r8a774e1-rst", .data = &rcar_rst_gen3 },
85 /* R-Car Gen1 */
86 { .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },
87 { .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 },
88 /* R-Car Gen2 */
89 { .compatible = "renesas,r8a7790-rst", .data = &rcar_rst_gen2 },
90 { .compatible = "renesas,r8a7791-rst", .data = &rcar_rst_gen2 },
91 { .compatible = "renesas,r8a7792-rst", .data = &rcar_rst_gen2 },
92 { .compatible = "renesas,r8a7793-rst", .data = &rcar_rst_gen2 },
93 { .compatible = "renesas,r8a7794-rst", .data = &rcar_rst_gen2 },
94 /* R-Car Gen3 */
95 { .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen3 },
96 { .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen3 },
97 { .compatible = "renesas,r8a77961-rst", .data = &rcar_rst_gen3 },
98 { .compatible = "renesas,r8a77965-rst", .data = &rcar_rst_gen3 },
99 { .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen3 },
100 { .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen3 },
101 { .compatible = "renesas,r8a77990-rst", .data = &rcar_rst_gen3 },
102 { .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 },
103 /* R-Car Gen4 */
104 { .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_gen4 },
105 { .compatible = "renesas,r8a779f0-rst", .data = &rcar_rst_gen4 },
106 { .compatible = "renesas,r8a779g0-rst", .data = &rcar_rst_gen4 },
107 { /* sentinel */ }
108 };
109
rcar_rst_init(void)110 static int __init rcar_rst_init(void)
111 {
112 const struct of_device_id *match;
113 const struct rst_config *cfg;
114 struct device_node *np;
115 void __iomem *base;
116 int error = 0;
117
118 np = of_find_matching_node_and_match(NULL, rcar_rst_matches, &match);
119 if (!np)
120 return -ENODEV;
121
122 base = of_iomap(np, 0);
123 if (!base) {
124 pr_warn("%pOF: Cannot map regs\n", np);
125 error = -ENOMEM;
126 goto out_put;
127 }
128
129 rcar_rst_base = base;
130 cfg = match->data;
131 rcar_rst_set_rproc_boot_addr_func = cfg->set_rproc_boot_addr;
132
133 saved_mode = ioread32(base + cfg->modemr);
134 if (cfg->configure) {
135 error = cfg->configure(base);
136 if (error) {
137 pr_warn("%pOF: Cannot run SoC specific configuration\n",
138 np);
139 goto out_put;
140 }
141 }
142
143 pr_debug("%pOF: MODE = 0x%08x\n", np, saved_mode);
144
145 out_put:
146 of_node_put(np);
147 return error;
148 }
149
rcar_rst_read_mode_pins(u32 * mode)150 int __init rcar_rst_read_mode_pins(u32 *mode)
151 {
152 int error;
153
154 if (!rcar_rst_base) {
155 error = rcar_rst_init();
156 if (error)
157 return error;
158 }
159
160 *mode = saved_mode;
161 return 0;
162 }
163
rcar_rst_set_rproc_boot_addr(u64 boot_addr)164 int rcar_rst_set_rproc_boot_addr(u64 boot_addr)
165 {
166 if (!rcar_rst_set_rproc_boot_addr_func)
167 return -EIO;
168
169 return rcar_rst_set_rproc_boot_addr_func(boot_addr);
170 }
171 EXPORT_SYMBOL_GPL(rcar_rst_set_rproc_boot_addr);
172
