1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
3 */
4 #include <linux/of.h>
5 #include <linux/module.h>
6 #include <linux/init.h>
7 #include <linux/rtc.h>
8 #include <linux/platform_device.h>
9 #include <linux/pm.h>
10 #include <linux/pm_wakeirq.h>
11 #include <linux/regmap.h>
12 #include <linux/slab.h>
13 #include <linux/spinlock.h>
14
15 /* RTC Register offsets from RTC CTRL REG */
16 #define PM8XXX_ALARM_CTRL_OFFSET 0x01
17 #define PM8XXX_RTC_WRITE_OFFSET 0x02
18 #define PM8XXX_RTC_READ_OFFSET 0x06
19 #define PM8XXX_ALARM_RW_OFFSET 0x0A
20
21 /* RTC_CTRL register bit fields */
22 #define PM8xxx_RTC_ENABLE BIT(7)
23 #define PM8xxx_RTC_ALARM_CLEAR BIT(0)
24 #define PM8xxx_RTC_ALARM_ENABLE BIT(7)
25
26 #define NUM_8_BIT_RTC_REGS 0x4
27
28 /**
29 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
30 * @ctrl: base address of control register
31 * @write: base address of write register
32 * @read: base address of read register
33 * @alarm_ctrl: base address of alarm control register
34 * @alarm_ctrl2: base address of alarm control2 register
35 * @alarm_rw: base address of alarm read-write register
36 * @alarm_en: alarm enable mask
37 */
38 struct pm8xxx_rtc_regs {
39 unsigned int ctrl;
40 unsigned int write;
41 unsigned int read;
42 unsigned int alarm_ctrl;
43 unsigned int alarm_ctrl2;
44 unsigned int alarm_rw;
45 unsigned int alarm_en;
46 };
47
48 /**
49 * struct pm8xxx_rtc - rtc driver internal structure
50 * @rtc: rtc device for this driver.
51 * @regmap: regmap used to access RTC registers
52 * @allow_set_time: indicates whether writing to the RTC is allowed
53 * @rtc_alarm_irq: rtc alarm irq number.
54 * @regs: rtc registers description.
55 * @rtc_dev: device structure.
56 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
57 */
58 struct pm8xxx_rtc {
59 struct rtc_device *rtc;
60 struct regmap *regmap;
61 bool allow_set_time;
62 int rtc_alarm_irq;
63 const struct pm8xxx_rtc_regs *regs;
64 struct device *rtc_dev;
65 spinlock_t ctrl_reg_lock;
66 };
67
68 /*
69 * Steps to write the RTC registers.
70 * 1. Disable alarm if enabled.
71 * 2. Disable rtc if enabled.
72 * 3. Write 0x00 to LSB.
73 * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
74 * 5. Enable rtc if disabled in step 2.
75 * 6. Enable alarm if disabled in step 1.
76 */
pm8xxx_rtc_set_time(struct device * dev,struct rtc_time * tm)77 static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
78 {
79 int rc, i;
80 unsigned long secs, irq_flags;
81 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
82 unsigned int ctrl_reg, rtc_ctrl_reg;
83 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
84 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
85
86 if (!rtc_dd->allow_set_time)
87 return -ENODEV;
88
89 secs = rtc_tm_to_time64(tm);
90
91 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
92
93 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
94 value[i] = secs & 0xFF;
95 secs >>= 8;
96 }
97
98 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
99
100 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
101 if (rc)
102 goto rtc_rw_fail;
103
104 if (ctrl_reg & regs->alarm_en) {
105 alarm_enabled = 1;
106 ctrl_reg &= ~regs->alarm_en;
107 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
108 if (rc) {
109 dev_err(dev, "Write to RTC Alarm control register failed\n");
110 goto rtc_rw_fail;
111 }
112 }
113
114 /* Disable RTC H/w before writing on RTC register */
115 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
116 if (rc)
117 goto rtc_rw_fail;
118
119 if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
120 rtc_disabled = 1;
121 rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
122 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
123 if (rc) {
124 dev_err(dev, "Write to RTC control register failed\n");
125 goto rtc_rw_fail;
126 }
127 }
128
129 /* Write 0 to Byte[0] */
130 rc = regmap_write(rtc_dd->regmap, regs->write, 0);
131 if (rc) {
132 dev_err(dev, "Write to RTC write data register failed\n");
133 goto rtc_rw_fail;
134 }
135
136 /* Write Byte[1], Byte[2], Byte[3] */
137 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
138 &value[1], sizeof(value) - 1);
139 if (rc) {
140 dev_err(dev, "Write to RTC write data register failed\n");
141 goto rtc_rw_fail;
142 }
143
144 /* Write Byte[0] */
145 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
146 if (rc) {
147 dev_err(dev, "Write to RTC write data register failed\n");
148 goto rtc_rw_fail;
149 }
150
151 /* Enable RTC H/w after writing on RTC register */
152 if (rtc_disabled) {
153 rtc_ctrl_reg |= PM8xxx_RTC_ENABLE;
154 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
155 if (rc) {
156 dev_err(dev, "Write to RTC control register failed\n");
157 goto rtc_rw_fail;
158 }
159 }
160
161 if (alarm_enabled) {
162 ctrl_reg |= regs->alarm_en;
163 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
164 if (rc) {
165 dev_err(dev, "Write to RTC Alarm control register failed\n");
166 goto rtc_rw_fail;
167 }
168 }
169
170 rtc_rw_fail:
171 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
172
173 return rc;
174 }
175
pm8xxx_rtc_read_time(struct device * dev,struct rtc_time * tm)176 static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
177 {
178 int rc;
179 u8 value[NUM_8_BIT_RTC_REGS];
180 unsigned long secs;
181 unsigned int reg;
182 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
183 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
184
185 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
186 if (rc) {
187 dev_err(dev, "RTC read data register failed\n");
188 return rc;
189 }
190
191 /*
192 * Read the LSB again and check if there has been a carry over.
193 * If there is, redo the read operation.
194 */
195 rc = regmap_read(rtc_dd->regmap, regs->read, ®);
196 if (rc < 0) {
197 dev_err(dev, "RTC read data register failed\n");
198 return rc;
199 }
200
201 if (unlikely(reg < value[0])) {
202 rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
203 value, sizeof(value));
204 if (rc) {
205 dev_err(dev, "RTC read data register failed\n");
206 return rc;
207 }
208 }
209
210 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
211 ((unsigned long)value[3] << 24);
212
213 rtc_time64_to_tm(secs, tm);
214
215 dev_dbg(dev, "secs = %lu, h:m:s == %ptRt, y-m-d = %ptRdr\n", secs, tm, tm);
216
217 return 0;
218 }
219
pm8xxx_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alarm)220 static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
221 {
222 int rc, i;
223 u8 value[NUM_8_BIT_RTC_REGS];
224 unsigned int ctrl_reg;
225 unsigned long secs, irq_flags;
226 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
227 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
228
229 secs = rtc_tm_to_time64(&alarm->time);
230
231 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
232 value[i] = secs & 0xFF;
233 secs >>= 8;
234 }
235
236 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
237
238 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
239 sizeof(value));
240 if (rc) {
241 dev_err(dev, "Write to RTC ALARM register failed\n");
242 goto rtc_rw_fail;
243 }
244
245 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
246 if (rc)
247 goto rtc_rw_fail;
248
249 if (alarm->enabled)
250 ctrl_reg |= regs->alarm_en;
251 else
252 ctrl_reg &= ~regs->alarm_en;
253
254 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
255 if (rc) {
256 dev_err(dev, "Write to RTC alarm control register failed\n");
257 goto rtc_rw_fail;
258 }
259
260 dev_dbg(dev, "Alarm Set for h:m:s=%ptRt, y-m-d=%ptRdr\n",
261 &alarm->time, &alarm->time);
262 rtc_rw_fail:
263 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
264 return rc;
265 }
266
pm8xxx_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alarm)267 static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
268 {
269 int rc;
270 unsigned int ctrl_reg;
271 u8 value[NUM_8_BIT_RTC_REGS];
272 unsigned long secs;
273 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
274 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
275
276 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
277 sizeof(value));
278 if (rc) {
279 dev_err(dev, "RTC alarm time read failed\n");
280 return rc;
281 }
282
283 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
284 ((unsigned long)value[3] << 24);
285
286 rtc_time64_to_tm(secs, &alarm->time);
287
288 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
289 if (rc) {
290 dev_err(dev, "Read from RTC alarm control register failed\n");
291 return rc;
292 }
293 alarm->enabled = !!(ctrl_reg & PM8xxx_RTC_ALARM_ENABLE);
294
295 dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n",
296 &alarm->time, &alarm->time);
297
298 return 0;
299 }
300
pm8xxx_rtc_alarm_irq_enable(struct device * dev,unsigned int enable)301 static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
302 {
303 int rc;
304 unsigned long irq_flags;
305 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
306 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
307 unsigned int ctrl_reg;
308 u8 value[NUM_8_BIT_RTC_REGS] = {0};
309
310 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
311
312 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
313 if (rc)
314 goto rtc_rw_fail;
315
316 if (enable)
317 ctrl_reg |= regs->alarm_en;
318 else
319 ctrl_reg &= ~regs->alarm_en;
320
321 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
322 if (rc) {
323 dev_err(dev, "Write to RTC control register failed\n");
324 goto rtc_rw_fail;
325 }
326
327 /* Clear Alarm register */
328 if (!enable) {
329 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
330 sizeof(value));
331 if (rc) {
332 dev_err(dev, "Clear RTC ALARM register failed\n");
333 goto rtc_rw_fail;
334 }
335 }
336
337 rtc_rw_fail:
338 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
339 return rc;
340 }
341
342 static const struct rtc_class_ops pm8xxx_rtc_ops = {
343 .read_time = pm8xxx_rtc_read_time,
344 .set_time = pm8xxx_rtc_set_time,
345 .set_alarm = pm8xxx_rtc_set_alarm,
346 .read_alarm = pm8xxx_rtc_read_alarm,
347 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
348 };
349
pm8xxx_alarm_trigger(int irq,void * dev_id)350 static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
351 {
352 struct pm8xxx_rtc *rtc_dd = dev_id;
353 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
354 unsigned int ctrl_reg;
355 int rc;
356
357 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
358
359 spin_lock(&rtc_dd->ctrl_reg_lock);
360
361 /* Clear the alarm enable bit */
362 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
363 if (rc) {
364 spin_unlock(&rtc_dd->ctrl_reg_lock);
365 goto rtc_alarm_handled;
366 }
367
368 ctrl_reg &= ~regs->alarm_en;
369
370 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
371 if (rc) {
372 spin_unlock(&rtc_dd->ctrl_reg_lock);
373 dev_err(rtc_dd->rtc_dev,
374 "Write to alarm control register failed\n");
375 goto rtc_alarm_handled;
376 }
377
378 spin_unlock(&rtc_dd->ctrl_reg_lock);
379
380 /* Clear RTC alarm register */
381 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
382 if (rc) {
383 dev_err(rtc_dd->rtc_dev,
384 "RTC Alarm control2 register read failed\n");
385 goto rtc_alarm_handled;
386 }
387
388 ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
389 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
390 if (rc)
391 dev_err(rtc_dd->rtc_dev,
392 "Write to RTC Alarm control2 register failed\n");
393
394 rtc_alarm_handled:
395 return IRQ_HANDLED;
396 }
397
pm8xxx_rtc_enable(struct pm8xxx_rtc * rtc_dd)398 static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
399 {
400 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
401 unsigned int ctrl_reg;
402 int rc;
403
404 /* Check if the RTC is on, else turn it on */
405 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
406 if (rc)
407 return rc;
408
409 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
410 ctrl_reg |= PM8xxx_RTC_ENABLE;
411 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
412 if (rc)
413 return rc;
414 }
415
416 return 0;
417 }
418
419 static const struct pm8xxx_rtc_regs pm8921_regs = {
420 .ctrl = 0x11d,
421 .write = 0x11f,
422 .read = 0x123,
423 .alarm_rw = 0x127,
424 .alarm_ctrl = 0x11d,
425 .alarm_ctrl2 = 0x11e,
426 .alarm_en = BIT(1),
427 };
428
429 static const struct pm8xxx_rtc_regs pm8058_regs = {
430 .ctrl = 0x1e8,
431 .write = 0x1ea,
432 .read = 0x1ee,
433 .alarm_rw = 0x1f2,
434 .alarm_ctrl = 0x1e8,
435 .alarm_ctrl2 = 0x1e9,
436 .alarm_en = BIT(1),
437 };
438
439 static const struct pm8xxx_rtc_regs pm8941_regs = {
440 .ctrl = 0x6046,
441 .write = 0x6040,
442 .read = 0x6048,
443 .alarm_rw = 0x6140,
444 .alarm_ctrl = 0x6146,
445 .alarm_ctrl2 = 0x6148,
446 .alarm_en = BIT(7),
447 };
448
449 static const struct pm8xxx_rtc_regs pmk8350_regs = {
450 .ctrl = 0x6146,
451 .write = 0x6140,
452 .read = 0x6148,
453 .alarm_rw = 0x6240,
454 .alarm_ctrl = 0x6246,
455 .alarm_ctrl2 = 0x6248,
456 .alarm_en = BIT(7),
457 };
458
459 /*
460 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
461 */
462 static const struct of_device_id pm8xxx_id_table[] = {
463 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
464 { .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs },
465 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
466 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
467 { .compatible = "qcom,pmk8350-rtc", .data = &pmk8350_regs },
468 { },
469 };
470 MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
471
pm8xxx_rtc_probe(struct platform_device * pdev)472 static int pm8xxx_rtc_probe(struct platform_device *pdev)
473 {
474 int rc;
475 struct pm8xxx_rtc *rtc_dd;
476 const struct of_device_id *match;
477
478 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
479 if (!match)
480 return -ENXIO;
481
482 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
483 if (rtc_dd == NULL)
484 return -ENOMEM;
485
486 /* Initialise spinlock to protect RTC control register */
487 spin_lock_init(&rtc_dd->ctrl_reg_lock);
488
489 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
490 if (!rtc_dd->regmap) {
491 dev_err(&pdev->dev, "Parent regmap unavailable.\n");
492 return -ENXIO;
493 }
494
495 rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
496 if (rtc_dd->rtc_alarm_irq < 0)
497 return -ENXIO;
498
499 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
500 "allow-set-time");
501
502 rtc_dd->regs = match->data;
503 rtc_dd->rtc_dev = &pdev->dev;
504
505 rc = pm8xxx_rtc_enable(rtc_dd);
506 if (rc)
507 return rc;
508
509 platform_set_drvdata(pdev, rtc_dd);
510
511 device_init_wakeup(&pdev->dev, 1);
512
513 /* Register the RTC device */
514 rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev);
515 if (IS_ERR(rtc_dd->rtc))
516 return PTR_ERR(rtc_dd->rtc);
517
518 rtc_dd->rtc->ops = &pm8xxx_rtc_ops;
519 rtc_dd->rtc->range_max = U32_MAX;
520
521 /* Request the alarm IRQ */
522 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
523 pm8xxx_alarm_trigger,
524 IRQF_TRIGGER_RISING,
525 "pm8xxx_rtc_alarm", rtc_dd);
526 if (rc < 0) {
527 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
528 return rc;
529 }
530
531 rc = devm_rtc_register_device(rtc_dd->rtc);
532 if (rc)
533 return rc;
534
535 rc = dev_pm_set_wake_irq(&pdev->dev, rtc_dd->rtc_alarm_irq);
536 if (rc)
537 return rc;
538
539 return 0;
540 }
541
pm8xxx_remove(struct platform_device * pdev)542 static int pm8xxx_remove(struct platform_device *pdev)
543 {
544 dev_pm_clear_wake_irq(&pdev->dev);
545 return 0;
546 }
547
548 static struct platform_driver pm8xxx_rtc_driver = {
549 .probe = pm8xxx_rtc_probe,
550 .remove = pm8xxx_remove,
551 .driver = {
552 .name = "rtc-pm8xxx",
553 .of_match_table = pm8xxx_id_table,
554 },
555 };
556
557 module_platform_driver(pm8xxx_rtc_driver);
558
559 MODULE_ALIAS("platform:rtc-pm8xxx");
560 MODULE_DESCRIPTION("PMIC8xxx RTC driver");
561 MODULE_LICENSE("GPL v2");
562 MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
563
