1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
4 *
5 * Copyright (C) 2017 Jacopo Mondi
6 */
7
8 /*
9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
10 * family.
11 * This includes SoCs which are sub- or super- sets of this particular line,
12 * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020).
13 */
14
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 #include <linux/property.h>
28 #include <linux/slab.h>
29
30 #include "../core.h"
31 #include "../devicetree.h"
32 #include "../pinconf.h"
33 #include "../pinmux.h"
34
35 #define DRIVER_NAME "pinctrl-rza1"
36
37 #define RZA1_P_REG 0x0000
38 #define RZA1_PPR_REG 0x0200
39 #define RZA1_PM_REG 0x0300
40 #define RZA1_PMC_REG 0x0400
41 #define RZA1_PFC_REG 0x0500
42 #define RZA1_PFCE_REG 0x0600
43 #define RZA1_PFCEA_REG 0x0a00
44 #define RZA1_PIBC_REG 0x4000
45 #define RZA1_PBDC_REG 0x4100
46 #define RZA1_PIPC_REG 0x4200
47
48 #define RZA1_ADDR(mem, reg, port) ((mem) + (reg) + ((port) * 4))
49
50 #define RZA1_NPORTS 12
51 #define RZA1_PINS_PER_PORT 16
52 #define RZA1_NPINS (RZA1_PINS_PER_PORT * RZA1_NPORTS)
53 #define RZA1_PIN_ID_TO_PORT(id) ((id) / RZA1_PINS_PER_PORT)
54 #define RZA1_PIN_ID_TO_PIN(id) ((id) % RZA1_PINS_PER_PORT)
55
56 /*
57 * Use 16 lower bits [15:0] for pin identifier
58 * Use 16 higher bits [31:16] for pin mux function
59 */
60 #define MUX_PIN_ID_MASK GENMASK(15, 0)
61 #define MUX_FUNC_MASK GENMASK(31, 16)
62
63 #define MUX_FUNC_OFFS 16
64 #define MUX_FUNC(pinconf) \
65 ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
66 #define MUX_FUNC_PFC_MASK BIT(0)
67 #define MUX_FUNC_PFCE_MASK BIT(1)
68 #define MUX_FUNC_PFCEA_MASK BIT(2)
69
70 /* Pin mux flags */
71 #define MUX_FLAGS_BIDIR BIT(0)
72 #define MUX_FLAGS_SWIO_INPUT BIT(1)
73 #define MUX_FLAGS_SWIO_OUTPUT BIT(2)
74
75 /* ----------------------------------------------------------------------------
76 * RZ/A1 pinmux flags
77 */
78
79 /*
80 * rza1_bidir_pin - describe a single pin that needs bidir flag applied.
81 */
82 struct rza1_bidir_pin {
83 u8 pin: 4;
84 u8 func: 4;
85 };
86
87 /*
88 * rza1_bidir_entry - describe a list of pins that needs bidir flag applied.
89 * Each struct rza1_bidir_entry describes a port.
90 */
91 struct rza1_bidir_entry {
92 const unsigned int npins;
93 const struct rza1_bidir_pin *pins;
94 };
95
96 /*
97 * rza1_swio_pin - describe a single pin that needs swio flag applied.
98 */
99 struct rza1_swio_pin {
100 u16 pin: 4;
101 u16 port: 4;
102 u16 func: 4;
103 u16 input: 1;
104 };
105
106 /*
107 * rza1_swio_entry - describe a list of pins that needs swio flag applied
108 */
109 struct rza1_swio_entry {
110 const unsigned int npins;
111 const struct rza1_swio_pin *pins;
112 };
113
114 /*
115 * rza1_pinmux_conf - group together bidir and swio pinmux flag tables
116 */
117 struct rza1_pinmux_conf {
118 const struct rza1_bidir_entry *bidir_entries;
119 const struct rza1_swio_entry *swio_entries;
120 };
121
122 /* ----------------------------------------------------------------------------
123 * RZ/A1H (r7s72100) pinmux flags
124 */
125
126 static const struct rza1_bidir_pin rza1h_bidir_pins_p1[] = {
127 { .pin = 0, .func = 1 },
128 { .pin = 1, .func = 1 },
129 { .pin = 2, .func = 1 },
130 { .pin = 3, .func = 1 },
131 { .pin = 4, .func = 1 },
132 { .pin = 5, .func = 1 },
133 { .pin = 6, .func = 1 },
134 { .pin = 7, .func = 1 },
135 };
136
137 static const struct rza1_bidir_pin rza1h_bidir_pins_p2[] = {
138 { .pin = 0, .func = 1 },
139 { .pin = 1, .func = 1 },
140 { .pin = 2, .func = 1 },
141 { .pin = 3, .func = 1 },
142 { .pin = 4, .func = 1 },
143 { .pin = 0, .func = 4 },
144 { .pin = 1, .func = 4 },
145 { .pin = 2, .func = 4 },
146 { .pin = 3, .func = 4 },
147 { .pin = 5, .func = 1 },
148 { .pin = 6, .func = 1 },
149 { .pin = 7, .func = 1 },
150 { .pin = 8, .func = 1 },
151 { .pin = 9, .func = 1 },
152 { .pin = 10, .func = 1 },
153 { .pin = 11, .func = 1 },
154 { .pin = 12, .func = 1 },
155 { .pin = 13, .func = 1 },
156 { .pin = 14, .func = 1 },
157 { .pin = 15, .func = 1 },
158 { .pin = 12, .func = 4 },
159 { .pin = 13, .func = 4 },
160 { .pin = 14, .func = 4 },
161 { .pin = 15, .func = 4 },
162 };
163
164 static const struct rza1_bidir_pin rza1h_bidir_pins_p3[] = {
165 { .pin = 3, .func = 2 },
166 { .pin = 10, .func = 7 },
167 { .pin = 11, .func = 7 },
168 { .pin = 13, .func = 7 },
169 { .pin = 14, .func = 7 },
170 { .pin = 15, .func = 7 },
171 { .pin = 10, .func = 8 },
172 { .pin = 11, .func = 8 },
173 { .pin = 13, .func = 8 },
174 { .pin = 14, .func = 8 },
175 { .pin = 15, .func = 8 },
176 };
177
178 static const struct rza1_bidir_pin rza1h_bidir_pins_p4[] = {
179 { .pin = 0, .func = 8 },
180 { .pin = 1, .func = 8 },
181 { .pin = 2, .func = 8 },
182 { .pin = 3, .func = 8 },
183 { .pin = 10, .func = 3 },
184 { .pin = 11, .func = 3 },
185 { .pin = 13, .func = 3 },
186 { .pin = 14, .func = 3 },
187 { .pin = 15, .func = 3 },
188 { .pin = 10, .func = 4 },
189 { .pin = 11, .func = 4 },
190 { .pin = 13, .func = 4 },
191 { .pin = 14, .func = 4 },
192 { .pin = 15, .func = 4 },
193 { .pin = 12, .func = 5 },
194 { .pin = 13, .func = 5 },
195 { .pin = 14, .func = 5 },
196 { .pin = 15, .func = 5 },
197 };
198
199 static const struct rza1_bidir_pin rza1h_bidir_pins_p6[] = {
200 { .pin = 0, .func = 1 },
201 { .pin = 1, .func = 1 },
202 { .pin = 2, .func = 1 },
203 { .pin = 3, .func = 1 },
204 { .pin = 4, .func = 1 },
205 { .pin = 5, .func = 1 },
206 { .pin = 6, .func = 1 },
207 { .pin = 7, .func = 1 },
208 { .pin = 8, .func = 1 },
209 { .pin = 9, .func = 1 },
210 { .pin = 10, .func = 1 },
211 { .pin = 11, .func = 1 },
212 { .pin = 12, .func = 1 },
213 { .pin = 13, .func = 1 },
214 { .pin = 14, .func = 1 },
215 { .pin = 15, .func = 1 },
216 };
217
218 static const struct rza1_bidir_pin rza1h_bidir_pins_p7[] = {
219 { .pin = 13, .func = 3 },
220 };
221
222 static const struct rza1_bidir_pin rza1h_bidir_pins_p8[] = {
223 { .pin = 8, .func = 3 },
224 { .pin = 9, .func = 3 },
225 { .pin = 10, .func = 3 },
226 { .pin = 11, .func = 3 },
227 { .pin = 14, .func = 2 },
228 { .pin = 15, .func = 2 },
229 { .pin = 14, .func = 3 },
230 { .pin = 15, .func = 3 },
231 };
232
233 static const struct rza1_bidir_pin rza1h_bidir_pins_p9[] = {
234 { .pin = 0, .func = 2 },
235 { .pin = 1, .func = 2 },
236 { .pin = 4, .func = 2 },
237 { .pin = 5, .func = 2 },
238 { .pin = 6, .func = 2 },
239 { .pin = 7, .func = 2 },
240 };
241
242 static const struct rza1_bidir_pin rza1h_bidir_pins_p11[] = {
243 { .pin = 6, .func = 2 },
244 { .pin = 7, .func = 2 },
245 { .pin = 9, .func = 2 },
246 { .pin = 6, .func = 4 },
247 { .pin = 7, .func = 4 },
248 { .pin = 9, .func = 4 },
249 { .pin = 10, .func = 2 },
250 { .pin = 11, .func = 2 },
251 { .pin = 10, .func = 4 },
252 { .pin = 11, .func = 4 },
253 { .pin = 12, .func = 4 },
254 { .pin = 13, .func = 4 },
255 { .pin = 14, .func = 4 },
256 { .pin = 15, .func = 4 },
257 };
258
259 static const struct rza1_swio_pin rza1h_swio_pins[] = {
260 { .port = 2, .pin = 7, .func = 4, .input = 0 },
261 { .port = 2, .pin = 11, .func = 4, .input = 0 },
262 { .port = 3, .pin = 7, .func = 3, .input = 0 },
263 { .port = 3, .pin = 7, .func = 8, .input = 0 },
264 { .port = 4, .pin = 7, .func = 5, .input = 0 },
265 { .port = 4, .pin = 7, .func = 11, .input = 0 },
266 { .port = 4, .pin = 15, .func = 6, .input = 0 },
267 { .port = 5, .pin = 0, .func = 1, .input = 1 },
268 { .port = 5, .pin = 1, .func = 1, .input = 1 },
269 { .port = 5, .pin = 2, .func = 1, .input = 1 },
270 { .port = 5, .pin = 3, .func = 1, .input = 1 },
271 { .port = 5, .pin = 4, .func = 1, .input = 1 },
272 { .port = 5, .pin = 5, .func = 1, .input = 1 },
273 { .port = 5, .pin = 6, .func = 1, .input = 1 },
274 { .port = 5, .pin = 7, .func = 1, .input = 1 },
275 { .port = 7, .pin = 4, .func = 6, .input = 0 },
276 { .port = 7, .pin = 11, .func = 2, .input = 0 },
277 { .port = 8, .pin = 10, .func = 8, .input = 0 },
278 { .port = 10, .pin = 15, .func = 2, .input = 0 },
279 };
280
281 static const struct rza1_bidir_entry rza1h_bidir_entries[RZA1_NPORTS] = {
282 [1] = { ARRAY_SIZE(rza1h_bidir_pins_p1), rza1h_bidir_pins_p1 },
283 [2] = { ARRAY_SIZE(rza1h_bidir_pins_p2), rza1h_bidir_pins_p2 },
284 [3] = { ARRAY_SIZE(rza1h_bidir_pins_p3), rza1h_bidir_pins_p3 },
285 [4] = { ARRAY_SIZE(rza1h_bidir_pins_p4), rza1h_bidir_pins_p4 },
286 [6] = { ARRAY_SIZE(rza1h_bidir_pins_p6), rza1h_bidir_pins_p6 },
287 [7] = { ARRAY_SIZE(rza1h_bidir_pins_p7), rza1h_bidir_pins_p7 },
288 [8] = { ARRAY_SIZE(rza1h_bidir_pins_p8), rza1h_bidir_pins_p8 },
289 [9] = { ARRAY_SIZE(rza1h_bidir_pins_p9), rza1h_bidir_pins_p9 },
290 [11] = { ARRAY_SIZE(rza1h_bidir_pins_p11), rza1h_bidir_pins_p11 },
291 };
292
293 static const struct rza1_swio_entry rza1h_swio_entries[] = {
294 [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
295 };
296
297 /* RZ/A1H (r7s72100x) pinmux flags table */
298 static const struct rza1_pinmux_conf rza1h_pmx_conf = {
299 .bidir_entries = rza1h_bidir_entries,
300 .swio_entries = rza1h_swio_entries,
301 };
302
303 /* ----------------------------------------------------------------------------
304 * RZ/A1L (r7s72102) pinmux flags
305 */
306
307 static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = {
308 { .pin = 0, .func = 1 },
309 { .pin = 1, .func = 1 },
310 { .pin = 2, .func = 1 },
311 { .pin = 3, .func = 1 },
312 { .pin = 4, .func = 1 },
313 { .pin = 5, .func = 1 },
314 { .pin = 6, .func = 1 },
315 { .pin = 7, .func = 1 },
316 };
317
318 static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = {
319 { .pin = 0, .func = 2 },
320 { .pin = 1, .func = 2 },
321 { .pin = 2, .func = 2 },
322 { .pin = 4, .func = 2 },
323 { .pin = 5, .func = 2 },
324 { .pin = 10, .func = 2 },
325 { .pin = 11, .func = 2 },
326 { .pin = 12, .func = 2 },
327 { .pin = 13, .func = 2 },
328 };
329
330 static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = {
331 { .pin = 1, .func = 4 },
332 { .pin = 2, .func = 2 },
333 { .pin = 3, .func = 2 },
334 { .pin = 6, .func = 2 },
335 { .pin = 7, .func = 2 },
336 };
337
338 static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = {
339 { .pin = 0, .func = 1 },
340 { .pin = 1, .func = 1 },
341 { .pin = 2, .func = 1 },
342 { .pin = 3, .func = 1 },
343 { .pin = 4, .func = 1 },
344 { .pin = 5, .func = 1 },
345 { .pin = 6, .func = 1 },
346 { .pin = 7, .func = 1 },
347 { .pin = 8, .func = 1 },
348 { .pin = 9, .func = 1 },
349 { .pin = 10, .func = 1 },
350 { .pin = 11, .func = 1 },
351 { .pin = 12, .func = 1 },
352 { .pin = 13, .func = 1 },
353 { .pin = 14, .func = 1 },
354 { .pin = 15, .func = 1 },
355 { .pin = 0, .func = 2 },
356 { .pin = 1, .func = 2 },
357 { .pin = 2, .func = 2 },
358 { .pin = 3, .func = 2 },
359 };
360
361 static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = {
362 { .pin = 0, .func = 1 },
363 { .pin = 1, .func = 1 },
364 { .pin = 2, .func = 1 },
365 { .pin = 3, .func = 1 },
366 { .pin = 4, .func = 1 },
367 { .pin = 5, .func = 1 },
368 { .pin = 6, .func = 1 },
369 { .pin = 7, .func = 1 },
370 { .pin = 8, .func = 1 },
371 { .pin = 9, .func = 1 },
372 { .pin = 10, .func = 1 },
373 { .pin = 11, .func = 1 },
374 { .pin = 12, .func = 1 },
375 { .pin = 13, .func = 1 },
376 { .pin = 14, .func = 1 },
377 { .pin = 15, .func = 1 },
378 };
379
380 static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = {
381 { .pin = 2, .func = 2 },
382 { .pin = 3, .func = 2 },
383 { .pin = 5, .func = 2 },
384 { .pin = 6, .func = 2 },
385 { .pin = 7, .func = 2 },
386 { .pin = 2, .func = 3 },
387 { .pin = 3, .func = 3 },
388 { .pin = 5, .func = 3 },
389 { .pin = 6, .func = 3 },
390 { .pin = 7, .func = 3 },
391 };
392
393 static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = {
394 { .pin = 1, .func = 2 },
395 { .pin = 0, .func = 3 },
396 { .pin = 1, .func = 3 },
397 { .pin = 3, .func = 3 },
398 { .pin = 4, .func = 3 },
399 { .pin = 5, .func = 3 },
400 };
401
402 static const struct rza1_swio_pin rza1l_swio_pins[] = {
403 { .port = 2, .pin = 8, .func = 2, .input = 0 },
404 { .port = 5, .pin = 6, .func = 3, .input = 0 },
405 { .port = 6, .pin = 6, .func = 3, .input = 0 },
406 { .port = 6, .pin = 10, .func = 3, .input = 0 },
407 { .port = 7, .pin = 10, .func = 2, .input = 0 },
408 { .port = 8, .pin = 2, .func = 3, .input = 0 },
409 };
410
411 static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = {
412 [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 },
413 [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 },
414 [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 },
415 [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 },
416 [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 },
417 [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 },
418 [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 },
419 };
420
421 static const struct rza1_swio_entry rza1l_swio_entries[] = {
422 [0] = { ARRAY_SIZE(rza1l_swio_pins), rza1l_swio_pins },
423 };
424
425 /* RZ/A1L (r7s72102x) pinmux flags table */
426 static const struct rza1_pinmux_conf rza1l_pmx_conf = {
427 .bidir_entries = rza1l_bidir_entries,
428 .swio_entries = rza1l_swio_entries,
429 };
430
431 /* ----------------------------------------------------------------------------
432 * RZ/A1 types
433 */
434 /**
435 * struct rza1_mux_conf - describes a pin multiplexing operation
436 *
437 * @id: the pin identifier from 0 to RZA1_NPINS
438 * @port: the port where pin sits on
439 * @pin: pin id
440 * @mux_func: alternate function id number
441 * @mux_flags: alternate function flags
442 * @value: output value to set the pin to
443 */
444 struct rza1_mux_conf {
445 u16 id;
446 u8 port;
447 u8 pin;
448 u8 mux_func;
449 u8 mux_flags;
450 u8 value;
451 };
452
453 /**
454 * struct rza1_port - describes a pin port
455 *
456 * This is mostly useful to lock register writes per-bank and not globally.
457 *
458 * @lock: protect access to HW registers
459 * @id: port number
460 * @base: logical address base
461 * @pins: pins sitting on this port
462 */
463 struct rza1_port {
464 spinlock_t lock;
465 unsigned int id;
466 void __iomem *base;
467 struct pinctrl_pin_desc *pins;
468 };
469
470 /**
471 * struct rza1_pinctrl - RZ pincontroller device
472 *
473 * @dev: parent device structure
474 * @mutex: protect [pinctrl|pinmux]_generic functions
475 * @base: logical address base
476 * @nport: number of pin controller ports
477 * @ports: pin controller banks
478 * @pins: pin array for pinctrl core
479 * @desc: pincontroller desc for pinctrl core
480 * @pctl: pinctrl device
481 * @data: device specific data
482 */
483 struct rza1_pinctrl {
484 struct device *dev;
485
486 struct mutex mutex;
487
488 void __iomem *base;
489
490 unsigned int nport;
491 struct rza1_port *ports;
492
493 struct pinctrl_pin_desc *pins;
494 struct pinctrl_desc desc;
495 struct pinctrl_dev *pctl;
496
497 const void *data;
498 };
499
500 /* ----------------------------------------------------------------------------
501 * RZ/A1 pinmux flags
502 */
rza1_pinmux_get_bidir(unsigned int port,unsigned int pin,unsigned int func,const struct rza1_bidir_entry * table)503 static inline bool rza1_pinmux_get_bidir(unsigned int port,
504 unsigned int pin,
505 unsigned int func,
506 const struct rza1_bidir_entry *table)
507 {
508 const struct rza1_bidir_entry *entry = &table[port];
509 const struct rza1_bidir_pin *bidir_pin;
510 unsigned int i;
511
512 for (i = 0; i < entry->npins; ++i) {
513 bidir_pin = &entry->pins[i];
514 if (bidir_pin->pin == pin && bidir_pin->func == func)
515 return true;
516 }
517
518 return false;
519 }
520
rza1_pinmux_get_swio(unsigned int port,unsigned int pin,unsigned int func,const struct rza1_swio_entry * table)521 static inline int rza1_pinmux_get_swio(unsigned int port,
522 unsigned int pin,
523 unsigned int func,
524 const struct rza1_swio_entry *table)
525 {
526 const struct rza1_swio_pin *swio_pin;
527 unsigned int i;
528
529
530 for (i = 0; i < table->npins; ++i) {
531 swio_pin = &table->pins[i];
532 if (swio_pin->port == port && swio_pin->pin == pin &&
533 swio_pin->func == func)
534 return swio_pin->input;
535 }
536
537 return -ENOENT;
538 }
539
540 /*
541 * rza1_pinmux_get_flags() - return pinmux flags associated to a pin
542 */
rza1_pinmux_get_flags(unsigned int port,unsigned int pin,unsigned int func,struct rza1_pinctrl * rza1_pctl)543 static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin,
544 unsigned int func,
545 struct rza1_pinctrl *rza1_pctl)
546
547 {
548 const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data;
549 const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries;
550 const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries;
551 unsigned int pmx_flags = 0;
552 int ret;
553
554 if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries))
555 pmx_flags |= MUX_FLAGS_BIDIR;
556
557 ret = rza1_pinmux_get_swio(port, pin, func, swio_entries);
558 if (ret == 0)
559 pmx_flags |= MUX_FLAGS_SWIO_OUTPUT;
560 else if (ret > 0)
561 pmx_flags |= MUX_FLAGS_SWIO_INPUT;
562
563 return pmx_flags;
564 }
565
566 /* ----------------------------------------------------------------------------
567 * RZ/A1 SoC operations
568 */
569
570 /*
571 * rza1_set_bit() - un-locked set/clear a single bit in pin configuration
572 * registers
573 */
rza1_set_bit(struct rza1_port * port,unsigned int reg,unsigned int bit,bool set)574 static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg,
575 unsigned int bit, bool set)
576 {
577 void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
578 u16 val = ioread16(mem);
579
580 if (set)
581 val |= BIT(bit);
582 else
583 val &= ~BIT(bit);
584
585 iowrite16(val, mem);
586 }
587
rza1_get_bit(struct rza1_port * port,unsigned int reg,unsigned int bit)588 static inline unsigned int rza1_get_bit(struct rza1_port *port,
589 unsigned int reg, unsigned int bit)
590 {
591 void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
592
593 return ioread16(mem) & BIT(bit);
594 }
595
596 /**
597 * rza1_pin_reset() - reset a pin to default initial state
598 *
599 * Reset pin state disabling input buffer and bi-directional control,
600 * and configure it as input port.
601 * Note that pin is now configured with direction as input but with input
602 * buffer disabled. This implies the pin value cannot be read in this state.
603 *
604 * @port: port where pin sits on
605 * @pin: pin offset
606 */
rza1_pin_reset(struct rza1_port * port,unsigned int pin)607 static void rza1_pin_reset(struct rza1_port *port, unsigned int pin)
608 {
609 unsigned long irqflags;
610
611 spin_lock_irqsave(&port->lock, irqflags);
612 rza1_set_bit(port, RZA1_PIBC_REG, pin, 0);
613 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
614
615 rza1_set_bit(port, RZA1_PM_REG, pin, 1);
616 rza1_set_bit(port, RZA1_PMC_REG, pin, 0);
617 rza1_set_bit(port, RZA1_PIPC_REG, pin, 0);
618 spin_unlock_irqrestore(&port->lock, irqflags);
619 }
620
621 /**
622 * rza1_pin_set_direction() - set I/O direction on a pin in port mode
623 *
624 * When running in output port mode keep PBDC enabled to allow reading the
625 * pin value from PPR.
626 *
627 * @port: port where pin sits on
628 * @pin: pin offset
629 * @input: input enable/disable flag
630 */
rza1_pin_set_direction(struct rza1_port * port,unsigned int pin,bool input)631 static inline void rza1_pin_set_direction(struct rza1_port *port,
632 unsigned int pin, bool input)
633 {
634 unsigned long irqflags;
635
636 spin_lock_irqsave(&port->lock, irqflags);
637
638 rza1_set_bit(port, RZA1_PIBC_REG, pin, 1);
639 if (input) {
640 rza1_set_bit(port, RZA1_PM_REG, pin, 1);
641 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
642 } else {
643 rza1_set_bit(port, RZA1_PM_REG, pin, 0);
644 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
645 }
646
647 spin_unlock_irqrestore(&port->lock, irqflags);
648 }
649
rza1_pin_set(struct rza1_port * port,unsigned int pin,unsigned int value)650 static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin,
651 unsigned int value)
652 {
653 unsigned long irqflags;
654
655 spin_lock_irqsave(&port->lock, irqflags);
656 rza1_set_bit(port, RZA1_P_REG, pin, !!value);
657 spin_unlock_irqrestore(&port->lock, irqflags);
658 }
659
rza1_pin_get(struct rza1_port * port,unsigned int pin)660 static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)
661 {
662 return rza1_get_bit(port, RZA1_PPR_REG, pin);
663 }
664
665 /**
666 * rza1_pin_mux_single() - configure pin multiplexing on a single pin
667 *
668 * @rza1_pctl: RZ/A1 pin controller device
669 * @mux_conf: pin multiplexing descriptor
670 */
rza1_pin_mux_single(struct rza1_pinctrl * rza1_pctl,struct rza1_mux_conf * mux_conf)671 static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl,
672 struct rza1_mux_conf *mux_conf)
673 {
674 struct rza1_port *port = &rza1_pctl->ports[mux_conf->port];
675 unsigned int pin = mux_conf->pin;
676 u8 mux_func = mux_conf->mux_func;
677 u8 mux_flags = mux_conf->mux_flags;
678 u8 mux_flags_from_table;
679
680 rza1_pin_reset(port, pin);
681
682 /* SWIO pinmux flags coming from DT are high precedence */
683 mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func,
684 rza1_pctl);
685 if (mux_flags)
686 mux_flags |= (mux_flags_from_table & MUX_FLAGS_BIDIR);
687 else
688 mux_flags = mux_flags_from_table;
689
690 if (mux_flags & MUX_FLAGS_BIDIR)
691 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
692
693 /*
694 * Enable alternate function mode and select it.
695 *
696 * Be careful here: the pin mux sub-nodes in device tree
697 * enumerate alternate functions from 1 to 8;
698 * subtract 1 before using macros to match registers configuration
699 * which expects numbers from 0 to 7 instead.
700 *
701 * ----------------------------------------------------
702 * Alternate mode selection table:
703 *
704 * PMC PFC PFCE PFCAE (mux_func - 1)
705 * 1 0 0 0 0
706 * 1 1 0 0 1
707 * 1 0 1 0 2
708 * 1 1 1 0 3
709 * 1 0 0 1 4
710 * 1 1 0 1 5
711 * 1 0 1 1 6
712 * 1 1 1 1 7
713 * ----------------------------------------------------
714 */
715 mux_func -= 1;
716 rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK);
717 rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK);
718 rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK);
719
720 /*
721 * All alternate functions except a few need PIPCn = 1.
722 * If PIPCn has to stay disabled (SW IO mode), configure PMn according
723 * to I/O direction specified by pin configuration -after- PMC has been
724 * set to one.
725 */
726 if (mux_flags & (MUX_FLAGS_SWIO_INPUT | MUX_FLAGS_SWIO_OUTPUT))
727 rza1_set_bit(port, RZA1_PM_REG, pin,
728 mux_flags & MUX_FLAGS_SWIO_INPUT);
729 else
730 rza1_set_bit(port, RZA1_PIPC_REG, pin, 1);
731
732 rza1_set_bit(port, RZA1_PMC_REG, pin, 1);
733
734 return 0;
735 }
736
737 /* ----------------------------------------------------------------------------
738 * gpio operations
739 */
740
741 /**
742 * rza1_gpio_request() - configure pin in port mode
743 *
744 * Configure a pin as gpio (port mode).
745 * After reset, the pin is in input mode with input buffer disabled.
746 * To use the pin as input or output, set_direction shall be called first
747 *
748 * @chip: gpio chip where the gpio sits on
749 * @gpio: gpio offset
750 */
rza1_gpio_request(struct gpio_chip * chip,unsigned int gpio)751 static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio)
752 {
753 struct rza1_port *port = gpiochip_get_data(chip);
754
755 rza1_pin_reset(port, gpio);
756
757 return 0;
758 }
759
760 /**
761 * rza1_gpio_free() - reset a pin
762 *
763 * Surprisingly, freeing a gpio is equivalent to requesting it.
764 * Reset pin to port mode, with input buffer disabled. This overwrites all
765 * port direction settings applied with set_direction
766 *
767 * @chip: gpio chip where the gpio sits on
768 * @gpio: gpio offset
769 */
rza1_gpio_free(struct gpio_chip * chip,unsigned int gpio)770 static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio)
771 {
772 struct rza1_port *port = gpiochip_get_data(chip);
773
774 rza1_pin_reset(port, gpio);
775 }
776
rza1_gpio_get_direction(struct gpio_chip * chip,unsigned int gpio)777 static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
778 {
779 struct rza1_port *port = gpiochip_get_data(chip);
780
781 if (rza1_get_bit(port, RZA1_PM_REG, gpio))
782 return GPIO_LINE_DIRECTION_IN;
783
784 return GPIO_LINE_DIRECTION_OUT;
785 }
786
rza1_gpio_direction_input(struct gpio_chip * chip,unsigned int gpio)787 static int rza1_gpio_direction_input(struct gpio_chip *chip,
788 unsigned int gpio)
789 {
790 struct rza1_port *port = gpiochip_get_data(chip);
791
792 rza1_pin_set_direction(port, gpio, true);
793
794 return 0;
795 }
796
rza1_gpio_direction_output(struct gpio_chip * chip,unsigned int gpio,int value)797 static int rza1_gpio_direction_output(struct gpio_chip *chip,
798 unsigned int gpio,
799 int value)
800 {
801 struct rza1_port *port = gpiochip_get_data(chip);
802
803 /* Set value before driving pin direction */
804 rza1_pin_set(port, gpio, value);
805 rza1_pin_set_direction(port, gpio, false);
806
807 return 0;
808 }
809
810 /**
811 * rza1_gpio_get() - read a gpio pin value
812 *
813 * Read gpio pin value through PPR register.
814 * Requires bi-directional mode to work when reading the value of a pin
815 * in output mode
816 *
817 * @chip: gpio chip where the gpio sits on
818 * @gpio: gpio offset
819 */
rza1_gpio_get(struct gpio_chip * chip,unsigned int gpio)820 static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio)
821 {
822 struct rza1_port *port = gpiochip_get_data(chip);
823
824 return rza1_pin_get(port, gpio);
825 }
826
rza1_gpio_set(struct gpio_chip * chip,unsigned int gpio,int value)827 static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio,
828 int value)
829 {
830 struct rza1_port *port = gpiochip_get_data(chip);
831
832 rza1_pin_set(port, gpio, value);
833 }
834
835 static const struct gpio_chip rza1_gpiochip_template = {
836 .request = rza1_gpio_request,
837 .free = rza1_gpio_free,
838 .get_direction = rza1_gpio_get_direction,
839 .direction_input = rza1_gpio_direction_input,
840 .direction_output = rza1_gpio_direction_output,
841 .get = rza1_gpio_get,
842 .set = rza1_gpio_set,
843 };
844 /* ----------------------------------------------------------------------------
845 * pinctrl operations
846 */
847
848 /**
849 * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its
850 * children sub-nodes
851 *
852 * @np: device tree node to parse
853 */
rza1_dt_node_pin_count(struct device_node * np)854 static int rza1_dt_node_pin_count(struct device_node *np)
855 {
856 struct device_node *child;
857 struct property *of_pins;
858 unsigned int npins;
859
860 of_pins = of_find_property(np, "pinmux", NULL);
861 if (of_pins)
862 return of_pins->length / sizeof(u32);
863
864 npins = 0;
865 for_each_child_of_node(np, child) {
866 of_pins = of_find_property(child, "pinmux", NULL);
867 if (!of_pins) {
868 of_node_put(child);
869 return -EINVAL;
870 }
871
872 npins += of_pins->length / sizeof(u32);
873 }
874
875 return npins;
876 }
877
878 /**
879 * rza1_parse_pinmux_node() - parse a pin mux sub-node
880 *
881 * @rza1_pctl: RZ/A1 pin controller device
882 * @np: of pmx sub-node
883 * @mux_confs: array of pin mux configurations to fill with parsed info
884 * @grpins: array of pin ids to mux
885 */
rza1_parse_pinmux_node(struct rza1_pinctrl * rza1_pctl,struct device_node * np,struct rza1_mux_conf * mux_confs,unsigned int * grpins)886 static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl,
887 struct device_node *np,
888 struct rza1_mux_conf *mux_confs,
889 unsigned int *grpins)
890 {
891 struct pinctrl_dev *pctldev = rza1_pctl->pctl;
892 char const *prop_name = "pinmux";
893 unsigned long *pin_configs;
894 unsigned int npin_configs;
895 struct property *of_pins;
896 unsigned int npins;
897 u8 pinmux_flags;
898 unsigned int i;
899 int ret;
900
901 of_pins = of_find_property(np, prop_name, NULL);
902 if (!of_pins) {
903 dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name);
904 return -ENOENT;
905 }
906 npins = of_pins->length / sizeof(u32);
907
908 /*
909 * Collect pin configuration properties: they apply to all pins in
910 * this sub-node
911 */
912 ret = pinconf_generic_parse_dt_config(np, pctldev, &pin_configs,
913 &npin_configs);
914 if (ret) {
915 dev_err(rza1_pctl->dev,
916 "Unable to parse pin configuration options for %pOFn\n",
917 np);
918 return ret;
919 }
920
921 /*
922 * Create a mask with pinmux flags from pin configuration;
923 * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction
924 * specified in device tree.
925 */
926 pinmux_flags = 0;
927 for (i = 0; i < npin_configs && pinmux_flags == 0; i++)
928 switch (pinconf_to_config_param(pin_configs[i])) {
929 case PIN_CONFIG_INPUT_ENABLE:
930 pinmux_flags |= MUX_FLAGS_SWIO_INPUT;
931 break;
932 case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */
933 case PIN_CONFIG_OUTPUT_ENABLE:
934 pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
935 break;
936 default:
937 break;
938
939 }
940
941 kfree(pin_configs);
942
943 /* Collect pin positions and their mux settings. */
944 for (i = 0; i < npins; ++i) {
945 u32 of_pinconf;
946 struct rza1_mux_conf *mux_conf = &mux_confs[i];
947
948 ret = of_property_read_u32_index(np, prop_name, i, &of_pinconf);
949 if (ret)
950 return ret;
951
952 mux_conf->id = of_pinconf & MUX_PIN_ID_MASK;
953 mux_conf->port = RZA1_PIN_ID_TO_PORT(mux_conf->id);
954 mux_conf->pin = RZA1_PIN_ID_TO_PIN(mux_conf->id);
955 mux_conf->mux_func = MUX_FUNC(of_pinconf);
956 mux_conf->mux_flags = pinmux_flags;
957
958 if (mux_conf->port >= RZA1_NPORTS ||
959 mux_conf->pin >= RZA1_PINS_PER_PORT) {
960 dev_err(rza1_pctl->dev,
961 "Wrong port %u pin %u for %s property\n",
962 mux_conf->port, mux_conf->pin, prop_name);
963 return -EINVAL;
964 }
965
966 grpins[i] = mux_conf->id;
967 }
968
969 return npins;
970 }
971
972 /**
973 * rza1_dt_node_to_map() - map a pin mux node to a function/group
974 *
975 * Parse and register a pin mux function.
976 *
977 * @pctldev: pin controller device
978 * @np: device tree node to parse
979 * @map: pointer to pin map (output)
980 * @num_maps: number of collected maps (output)
981 */
rza1_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned int * num_maps)982 static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
983 struct device_node *np,
984 struct pinctrl_map **map,
985 unsigned int *num_maps)
986 {
987 struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
988 struct rza1_mux_conf *mux_confs, *mux_conf;
989 unsigned int *grpins, *grpin;
990 struct device_node *child;
991 const char *grpname;
992 const char **fngrps;
993 int ret, npins;
994 int gsel, fsel;
995
996 npins = rza1_dt_node_pin_count(np);
997 if (npins < 0) {
998 dev_err(rza1_pctl->dev, "invalid pinmux node structure\n");
999 return -EINVAL;
1000 }
1001
1002 /*
1003 * Functions are made of 1 group only;
1004 * in fact, functions and groups are identical for this pin controller
1005 * except that functions carry an array of per-pin mux configuration
1006 * settings.
1007 */
1008 mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs),
1009 GFP_KERNEL);
1010 grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins),
1011 GFP_KERNEL);
1012 fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL);
1013
1014 if (!mux_confs || !grpins || !fngrps)
1015 return -ENOMEM;
1016
1017 /*
1018 * Parse the pinmux node.
1019 * If the node does not contain "pinmux" property (-ENOENT)
1020 * that property shall be specified in all its children sub-nodes.
1021 */
1022 mux_conf = &mux_confs[0];
1023 grpin = &grpins[0];
1024
1025 ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin);
1026 if (ret == -ENOENT)
1027 for_each_child_of_node(np, child) {
1028 ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf,
1029 grpin);
1030 if (ret < 0) {
1031 of_node_put(child);
1032 return ret;
1033 }
1034
1035 grpin += ret;
1036 mux_conf += ret;
1037 }
1038 else if (ret < 0)
1039 return ret;
1040
1041 /* Register pin group and function name to pinctrl_generic */
1042 grpname = np->name;
1043 fngrps[0] = grpname;
1044
1045 mutex_lock(&rza1_pctl->mutex);
1046 gsel = pinctrl_generic_add_group(pctldev, grpname, grpins, npins,
1047 NULL);
1048 if (gsel < 0) {
1049 mutex_unlock(&rza1_pctl->mutex);
1050 return gsel;
1051 }
1052
1053 fsel = pinmux_generic_add_function(pctldev, grpname, fngrps, 1,
1054 mux_confs);
1055 if (fsel < 0) {
1056 ret = fsel;
1057 goto remove_group;
1058 }
1059
1060 dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n",
1061 grpname, npins);
1062
1063 /* Create map where to retrieve function and mux settings from */
1064 *num_maps = 0;
1065 *map = kzalloc(sizeof(**map), GFP_KERNEL);
1066 if (!*map) {
1067 ret = -ENOMEM;
1068 goto remove_function;
1069 }
1070
1071 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1072 (*map)->data.mux.group = np->name;
1073 (*map)->data.mux.function = np->name;
1074 *num_maps = 1;
1075 mutex_unlock(&rza1_pctl->mutex);
1076
1077 return 0;
1078
1079 remove_function:
1080 pinmux_generic_remove_function(pctldev, fsel);
1081
1082 remove_group:
1083 pinctrl_generic_remove_group(pctldev, gsel);
1084 mutex_unlock(&rza1_pctl->mutex);
1085
1086 dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n",
1087 grpname);
1088
1089 return ret;
1090 }
1091
rza1_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned int num_maps)1092 static void rza1_dt_free_map(struct pinctrl_dev *pctldev,
1093 struct pinctrl_map *map, unsigned int num_maps)
1094 {
1095 kfree(map);
1096 }
1097
1098 static const struct pinctrl_ops rza1_pinctrl_ops = {
1099 .get_groups_count = pinctrl_generic_get_group_count,
1100 .get_group_name = pinctrl_generic_get_group_name,
1101 .get_group_pins = pinctrl_generic_get_group_pins,
1102 .dt_node_to_map = rza1_dt_node_to_map,
1103 .dt_free_map = rza1_dt_free_map,
1104 };
1105
1106 /* ----------------------------------------------------------------------------
1107 * pinmux operations
1108 */
1109
1110 /**
1111 * rza1_set_mux() - retrieve pins from a group and apply their mux settings
1112 *
1113 * @pctldev: pin controller device
1114 * @selector: function selector
1115 * @group: group selector
1116 */
rza1_set_mux(struct pinctrl_dev * pctldev,unsigned int selector,unsigned int group)1117 static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1118 unsigned int group)
1119 {
1120 struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
1121 struct rza1_mux_conf *mux_confs;
1122 struct function_desc *func;
1123 struct group_desc *grp;
1124 int i;
1125
1126 grp = pinctrl_generic_get_group(pctldev, group);
1127 if (!grp)
1128 return -EINVAL;
1129
1130 func = pinmux_generic_get_function(pctldev, selector);
1131 if (!func)
1132 return -EINVAL;
1133
1134 mux_confs = (struct rza1_mux_conf *)func->data;
1135 for (i = 0; i < grp->num_pins; ++i) {
1136 int ret;
1137
1138 ret = rza1_pin_mux_single(rza1_pctl, &mux_confs[i]);
1139 if (ret)
1140 return ret;
1141 }
1142
1143 return 0;
1144 }
1145
1146 static const struct pinmux_ops rza1_pinmux_ops = {
1147 .get_functions_count = pinmux_generic_get_function_count,
1148 .get_function_name = pinmux_generic_get_function_name,
1149 .get_function_groups = pinmux_generic_get_function_groups,
1150 .set_mux = rza1_set_mux,
1151 .strict = true,
1152 };
1153
1154 /* ----------------------------------------------------------------------------
1155 * RZ/A1 pin controller driver operations
1156 */
1157
1158 /**
1159 * rza1_parse_gpiochip() - parse and register a gpio chip and pin range
1160 *
1161 * The gpio controller subnode shall provide a "gpio-ranges" list property as
1162 * defined by gpio device tree binding documentation.
1163 *
1164 * @rza1_pctl: RZ/A1 pin controller device
1165 * @fwnode: gpio-controller firmware node
1166 * @chip: gpio chip to register to gpiolib
1167 * @range: pin range to register to pinctrl core
1168 */
rza1_parse_gpiochip(struct rza1_pinctrl * rza1_pctl,struct fwnode_handle * fwnode,struct gpio_chip * chip,struct pinctrl_gpio_range * range)1169 static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
1170 struct fwnode_handle *fwnode,
1171 struct gpio_chip *chip,
1172 struct pinctrl_gpio_range *range)
1173 {
1174 const char *list_name = "gpio-ranges";
1175 struct fwnode_reference_args args;
1176 unsigned int gpioport;
1177 u32 pinctrl_base;
1178 int ret;
1179
1180 ret = fwnode_property_get_reference_args(fwnode, list_name, NULL, 3, 0, &args);
1181 if (ret) {
1182 dev_err(rza1_pctl->dev, "Unable to parse %s list property\n",
1183 list_name);
1184 return ret;
1185 }
1186
1187 /*
1188 * Find out on which port this gpio-chip maps to by inspecting the
1189 * second argument of the "gpio-ranges" property.
1190 */
1191 pinctrl_base = args.args[1];
1192 gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base);
1193 if (gpioport >= RZA1_NPORTS) {
1194 dev_err(rza1_pctl->dev,
1195 "Invalid values in property %s\n", list_name);
1196 return -EINVAL;
1197 }
1198
1199 *chip = rza1_gpiochip_template;
1200 chip->base = -1;
1201 chip->ngpio = args.args[2];
1202 chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%pfwP", fwnode);
1203 if (!chip->label)
1204 return -ENOMEM;
1205
1206 chip->fwnode = fwnode;
1207 chip->parent = rza1_pctl->dev;
1208
1209 range->id = gpioport;
1210 range->name = chip->label;
1211 range->pin_base = range->base = pinctrl_base;
1212 range->npins = args.args[2];
1213 range->gc = chip;
1214
1215 ret = devm_gpiochip_add_data(rza1_pctl->dev, chip,
1216 &rza1_pctl->ports[gpioport]);
1217 if (ret)
1218 return ret;
1219
1220 pinctrl_add_gpio_range(rza1_pctl->pctl, range);
1221
1222 dev_dbg(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
1223 chip->label, chip->ngpio);
1224
1225 return 0;
1226 }
1227
1228 /**
1229 * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges
1230 *
1231 * @rza1_pctl: RZ/A1 pin controller device
1232 */
rza1_gpio_register(struct rza1_pinctrl * rza1_pctl)1233 static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl)
1234 {
1235 struct pinctrl_gpio_range *gpio_ranges;
1236 struct gpio_chip *gpio_chips;
1237 struct fwnode_handle *child;
1238 unsigned int ngpiochips;
1239 unsigned int i;
1240 int ret;
1241
1242 ngpiochips = gpiochip_node_count(rza1_pctl->dev);
1243 if (ngpiochips == 0) {
1244 dev_dbg(rza1_pctl->dev, "No gpiochip registered\n");
1245 return 0;
1246 }
1247
1248 gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips,
1249 sizeof(*gpio_chips), GFP_KERNEL);
1250 gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips,
1251 sizeof(*gpio_ranges), GFP_KERNEL);
1252 if (!gpio_chips || !gpio_ranges)
1253 return -ENOMEM;
1254
1255 i = 0;
1256 for_each_gpiochip_node(rza1_pctl->dev, child) {
1257 ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i],
1258 &gpio_ranges[i]);
1259 if (ret) {
1260 fwnode_handle_put(child);
1261 return ret;
1262 }
1263
1264 ++i;
1265 }
1266
1267 dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i);
1268
1269 return 0;
1270 }
1271
1272 /**
1273 * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register
1274 * them to pinctrl and gpio cores.
1275 *
1276 * @rza1_pctl: RZ/A1 pin controller device
1277 */
rza1_pinctrl_register(struct rza1_pinctrl * rza1_pctl)1278 static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl)
1279 {
1280 struct pinctrl_pin_desc *pins;
1281 struct rza1_port *ports;
1282 unsigned int i;
1283 int ret;
1284
1285 pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins),
1286 GFP_KERNEL);
1287 ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports),
1288 GFP_KERNEL);
1289 if (!pins || !ports)
1290 return -ENOMEM;
1291
1292 rza1_pctl->pins = pins;
1293 rza1_pctl->desc.pins = pins;
1294 rza1_pctl->desc.npins = RZA1_NPINS;
1295 rza1_pctl->ports = ports;
1296
1297 for (i = 0; i < RZA1_NPINS; ++i) {
1298 unsigned int pin = RZA1_PIN_ID_TO_PIN(i);
1299 unsigned int port = RZA1_PIN_ID_TO_PORT(i);
1300
1301 pins[i].number = i;
1302 pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL,
1303 "P%u-%u", port, pin);
1304 if (!pins[i].name)
1305 return -ENOMEM;
1306
1307 if (i % RZA1_PINS_PER_PORT == 0) {
1308 /*
1309 * Setup ports;
1310 * they provide per-port lock and logical base address.
1311 */
1312 unsigned int port_id = RZA1_PIN_ID_TO_PORT(i);
1313
1314 ports[port_id].id = port_id;
1315 ports[port_id].base = rza1_pctl->base;
1316 ports[port_id].pins = &pins[i];
1317 spin_lock_init(&ports[port_id].lock);
1318 }
1319 }
1320
1321 ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc,
1322 rza1_pctl, &rza1_pctl->pctl);
1323 if (ret) {
1324 dev_err(rza1_pctl->dev,
1325 "RZ/A1 pin controller registration failed\n");
1326 return ret;
1327 }
1328
1329 ret = pinctrl_enable(rza1_pctl->pctl);
1330 if (ret) {
1331 dev_err(rza1_pctl->dev,
1332 "RZ/A1 pin controller failed to start\n");
1333 return ret;
1334 }
1335
1336 ret = rza1_gpio_register(rza1_pctl);
1337 if (ret) {
1338 dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n");
1339 return ret;
1340 }
1341
1342 return 0;
1343 }
1344
rza1_pinctrl_probe(struct platform_device * pdev)1345 static int rza1_pinctrl_probe(struct platform_device *pdev)
1346 {
1347 struct rza1_pinctrl *rza1_pctl;
1348 int ret;
1349
1350 rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL);
1351 if (!rza1_pctl)
1352 return -ENOMEM;
1353
1354 rza1_pctl->dev = &pdev->dev;
1355
1356 rza1_pctl->base = devm_platform_ioremap_resource(pdev, 0);
1357 if (IS_ERR(rza1_pctl->base))
1358 return PTR_ERR(rza1_pctl->base);
1359
1360 mutex_init(&rza1_pctl->mutex);
1361
1362 platform_set_drvdata(pdev, rza1_pctl);
1363
1364 rza1_pctl->desc.name = DRIVER_NAME;
1365 rza1_pctl->desc.pctlops = &rza1_pinctrl_ops;
1366 rza1_pctl->desc.pmxops = &rza1_pinmux_ops;
1367 rza1_pctl->desc.owner = THIS_MODULE;
1368 rza1_pctl->data = of_device_get_match_data(&pdev->dev);
1369
1370 ret = rza1_pinctrl_register(rza1_pctl);
1371 if (ret)
1372 return ret;
1373
1374 dev_info(&pdev->dev,
1375 "RZ/A1 pin controller and gpio successfully registered\n");
1376
1377 return 0;
1378 }
1379
1380 static const struct of_device_id rza1_pinctrl_of_match[] = {
1381 {
1382 /* RZ/A1H, RZ/A1M */
1383 .compatible = "renesas,r7s72100-ports",
1384 .data = &rza1h_pmx_conf,
1385 },
1386 {
1387 /* RZ/A1L */
1388 .compatible = "renesas,r7s72102-ports",
1389 .data = &rza1l_pmx_conf,
1390 },
1391 { }
1392 };
1393
1394 static struct platform_driver rza1_pinctrl_driver = {
1395 .driver = {
1396 .name = DRIVER_NAME,
1397 .of_match_table = rza1_pinctrl_of_match,
1398 },
1399 .probe = rza1_pinctrl_probe,
1400 };
1401
rza1_pinctrl_init(void)1402 static int __init rza1_pinctrl_init(void)
1403 {
1404 return platform_driver_register(&rza1_pinctrl_driver);
1405 }
1406 core_initcall(rza1_pinctrl_init);
1407
1408 MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org");
1409 MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC");
1410 MODULE_LICENSE("GPL v2");
1411
