1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell ac5 pinctrl driver based on mvebu pinctrl core
4 *
5 * Copyright (C) 2021 Marvell
6 *
7 * Noam Liron <lnoam@marvell.com>
8 */
9
10 #include <linux/err.h>
11 #include <linux/init.h>
12 #include <linux/io.h>
13 #include <linux/platform_device.h>
14 #include <linux/of.h>
15 #include <linux/of_device.h>
16 #include <linux/pinctrl/pinctrl.h>
17
18 #include "pinctrl-mvebu.h"
19
20 static struct mvebu_mpp_mode ac5_mpp_modes[] = {
21 MPP_MODE(0,
22 MPP_FUNCTION(0, "gpio", NULL),
23 MPP_FUNCTION(1, "sdio", "d0"),
24 MPP_FUNCTION(2, "nand", "io4")),
25 MPP_MODE(1,
26 MPP_FUNCTION(0, "gpio", NULL),
27 MPP_FUNCTION(1, "sdio", "d1"),
28 MPP_FUNCTION(2, "nand", "io3")),
29 MPP_MODE(2,
30 MPP_FUNCTION(0, "gpio", NULL),
31 MPP_FUNCTION(1, "sdio", "d2"),
32 MPP_FUNCTION(2, "nand", "io2")),
33 MPP_MODE(3,
34 MPP_FUNCTION(0, "gpio", NULL),
35 MPP_FUNCTION(1, "sdio", "d3"),
36 MPP_FUNCTION(2, "nand", "io7")),
37 MPP_MODE(4,
38 MPP_FUNCTION(0, "gpio", NULL),
39 MPP_FUNCTION(1, "sdio", "d4"),
40 MPP_FUNCTION(2, "nand", "io6"),
41 MPP_FUNCTION(3, "uart3", "txd"),
42 MPP_FUNCTION(4, "uart2", "txd")),
43 MPP_MODE(5,
44 MPP_FUNCTION(0, "gpio", NULL),
45 MPP_FUNCTION(1, "sdio", "d5"),
46 MPP_FUNCTION(2, "nand", "io5"),
47 MPP_FUNCTION(3, "uart3", "rxd"),
48 MPP_FUNCTION(4, "uart2", "rxd")),
49 MPP_MODE(6,
50 MPP_FUNCTION(0, "gpio", NULL),
51 MPP_FUNCTION(1, "sdio", "d6"),
52 MPP_FUNCTION(2, "nand", "io0"),
53 MPP_FUNCTION(3, "i2c1", "sck")),
54 MPP_MODE(7,
55 MPP_FUNCTION(0, "gpio", NULL),
56 MPP_FUNCTION(1, "sdio", "d7"),
57 MPP_FUNCTION(2, "nand", "io1"),
58 MPP_FUNCTION(3, "i2c1", "sda")),
59 MPP_MODE(8,
60 MPP_FUNCTION(0, "gpio", NULL),
61 MPP_FUNCTION(1, "sdio", "clk"),
62 MPP_FUNCTION(2, "nand", "wen")),
63 MPP_MODE(9,
64 MPP_FUNCTION(0, "gpio", NULL),
65 MPP_FUNCTION(1, "sdio", "cmd"),
66 MPP_FUNCTION(2, "nand", "ale")),
67 MPP_MODE(10,
68 MPP_FUNCTION(0, "gpio", NULL),
69 MPP_FUNCTION(1, "sdio", "ds"),
70 MPP_FUNCTION(2, "nand", "cle")),
71 MPP_MODE(11,
72 MPP_FUNCTION(0, "gpio", NULL),
73 MPP_FUNCTION(1, "sdio", "rst"),
74 MPP_FUNCTION(2, "nand", "cen")),
75 MPP_MODE(12,
76 MPP_FUNCTION(0, "gpio", NULL),
77 MPP_FUNCTION(1, "spi0", "clk")),
78 MPP_MODE(13,
79 MPP_FUNCTION(0, "gpio", NULL),
80 MPP_FUNCTION(1, "spi0", "csn")),
81 MPP_MODE(14,
82 MPP_FUNCTION(0, "gpio", NULL),
83 MPP_FUNCTION(1, "spi0", "mosi")),
84 MPP_MODE(15,
85 MPP_FUNCTION(0, "gpio", NULL),
86 MPP_FUNCTION(1, "spi0", "miso")),
87 MPP_MODE(16,
88 MPP_FUNCTION(0, "gpio", NULL),
89 MPP_FUNCTION(1, "spi0", "wpn"),
90 MPP_FUNCTION(2, "nand", "ren"),
91 MPP_FUNCTION(3, "uart1", "txd")),
92 MPP_MODE(17,
93 MPP_FUNCTION(0, "gpio", NULL),
94 MPP_FUNCTION(1, "spi0", "hold"),
95 MPP_FUNCTION(2, "nand", "rb"),
96 MPP_FUNCTION(3, "uart1", "rxd")),
97 MPP_MODE(18,
98 MPP_FUNCTION(0, "gpio", NULL),
99 MPP_FUNCTION(1, "tsen_int", NULL),
100 MPP_FUNCTION(2, "uart2", "rxd"),
101 MPP_FUNCTION(3, "wd_int", NULL)),
102 MPP_MODE(19,
103 MPP_FUNCTION(0, "gpio", NULL),
104 MPP_FUNCTION(1, "dev_init_done", NULL),
105 MPP_FUNCTION(2, "uart2", "txd")),
106 MPP_MODE(20,
107 MPP_FUNCTION(0, "gpio", NULL),
108 MPP_FUNCTION(2, "i2c1", "sck"),
109 MPP_FUNCTION(3, "spi1", "clk"),
110 MPP_FUNCTION(4, "uart3", "txd")),
111 MPP_MODE(21,
112 MPP_FUNCTION(0, "gpio", NULL),
113 MPP_FUNCTION(2, "i2c1", "sda"),
114 MPP_FUNCTION(3, "spi1", "csn"),
115 MPP_FUNCTION(4, "uart3", "rxd")),
116 MPP_MODE(22,
117 MPP_FUNCTION(0, "gpio", NULL),
118 MPP_FUNCTION(3, "spi1", "mosi")),
119 MPP_MODE(23,
120 MPP_FUNCTION(0, "gpio", NULL),
121 MPP_FUNCTION(3, "spi1", "miso")),
122 MPP_MODE(24,
123 MPP_FUNCTION(0, "gpio", NULL),
124 MPP_FUNCTION(1, "wd_int", NULL),
125 MPP_FUNCTION(2, "uart2", "txd"),
126 MPP_FUNCTION(3, "uartsd", "txd")),
127 MPP_MODE(25,
128 MPP_FUNCTION(0, "gpio", NULL),
129 MPP_FUNCTION(1, "int_out", NULL),
130 MPP_FUNCTION(2, "uart2", "rxd"),
131 MPP_FUNCTION(3, "uartsd", "rxd")),
132 MPP_MODE(26,
133 MPP_FUNCTION(0, "gpio", NULL),
134 MPP_FUNCTION(1, "i2c0", "sck"),
135 MPP_FUNCTION(2, "ptp", "clk1"),
136 MPP_FUNCTION(3, "uart3", "txd")),
137 MPP_MODE(27,
138 MPP_FUNCTION(0, "gpio", NULL),
139 MPP_FUNCTION(1, "i2c0", "sda"),
140 MPP_FUNCTION(2, "ptp", "pulse"),
141 MPP_FUNCTION(3, "uart3", "rxd")),
142 MPP_MODE(28,
143 MPP_FUNCTION(0, "gpio", NULL),
144 MPP_FUNCTION(1, "xg", "mdio"),
145 MPP_FUNCTION(2, "ge", "mdio"),
146 MPP_FUNCTION(3, "uart3", "txd")),
147 MPP_MODE(29,
148 MPP_FUNCTION(0, "gpio", NULL),
149 MPP_FUNCTION(1, "xg", "mdio"),
150 MPP_FUNCTION(2, "ge", "mdio"),
151 MPP_FUNCTION(3, "uart3", "rxd")),
152 MPP_MODE(30,
153 MPP_FUNCTION(0, "gpio", NULL),
154 MPP_FUNCTION(1, "xg", "mdio"),
155 MPP_FUNCTION(2, "ge", "mdio"),
156 MPP_FUNCTION(3, "ge", "mdio")),
157 MPP_MODE(31,
158 MPP_FUNCTION(0, "gpio", NULL),
159 MPP_FUNCTION(1, "xg", "mdio"),
160 MPP_FUNCTION(2, "ge", "mdio"),
161 MPP_FUNCTION(3, "ge", "mdio")),
162 MPP_MODE(32,
163 MPP_FUNCTION(0, "gpio", NULL),
164 MPP_FUNCTION(1, "uart0", "txd")),
165 MPP_MODE(33,
166 MPP_FUNCTION(0, "gpio", NULL),
167 MPP_FUNCTION(1, "uart0", "rxd"),
168 MPP_FUNCTION(2, "ptp", "clk1"),
169 MPP_FUNCTION(3, "ptp", "pulse")),
170 MPP_MODE(34,
171 MPP_FUNCTION(0, "gpio", NULL),
172 MPP_FUNCTION(1, "ge", "mdio"),
173 MPP_FUNCTION(2, "uart3", "rxd")),
174 MPP_MODE(35,
175 MPP_FUNCTION(0, "gpio", NULL),
176 MPP_FUNCTION(1, "ge", "mdio"),
177 MPP_FUNCTION(2, "uart3", "txd"),
178 MPP_FUNCTION(3, "pcie", "rstoutn")),
179 MPP_MODE(36,
180 MPP_FUNCTION(0, "gpio", NULL),
181 MPP_FUNCTION(1, "ptp", "clk0_tp"),
182 MPP_FUNCTION(2, "ptp", "clk1_tp")),
183 MPP_MODE(37,
184 MPP_FUNCTION(0, "gpio", NULL),
185 MPP_FUNCTION(1, "ptp", "pulse_tp"),
186 MPP_FUNCTION(2, "wd_int", NULL)),
187 MPP_MODE(38,
188 MPP_FUNCTION(0, "gpio", NULL),
189 MPP_FUNCTION(1, "synce", "clk_out0")),
190 MPP_MODE(39,
191 MPP_FUNCTION(0, "gpio", NULL),
192 MPP_FUNCTION(1, "synce", "clk_out1")),
193 MPP_MODE(40,
194 MPP_FUNCTION(0, "gpio", NULL),
195 MPP_FUNCTION(1, "ptp", "pclk_out0"),
196 MPP_FUNCTION(2, "ptp", "pclk_out1")),
197 MPP_MODE(41,
198 MPP_FUNCTION(0, "gpio", NULL),
199 MPP_FUNCTION(1, "ptp", "ref_clk"),
200 MPP_FUNCTION(2, "ptp", "clk1"),
201 MPP_FUNCTION(3, "ptp", "pulse"),
202 MPP_FUNCTION(4, "uart2", "txd"),
203 MPP_FUNCTION(5, "i2c1", "sck")),
204 MPP_MODE(42,
205 MPP_FUNCTION(0, "gpio", NULL),
206 MPP_FUNCTION(1, "ptp", "clk0"),
207 MPP_FUNCTION(2, "ptp", "clk1"),
208 MPP_FUNCTION(3, "ptp", "pulse"),
209 MPP_FUNCTION(4, "uart2", "rxd"),
210 MPP_FUNCTION(5, "i2c1", "sda")),
211 MPP_MODE(43,
212 MPP_FUNCTION(0, "gpio", NULL),
213 MPP_FUNCTION(1, "led", "clk")),
214 MPP_MODE(44,
215 MPP_FUNCTION(0, "gpio", NULL),
216 MPP_FUNCTION(1, "led", "stb")),
217 MPP_MODE(45,
218 MPP_FUNCTION(0, "gpio", NULL),
219 MPP_FUNCTION(1, "led", "data")),
220 };
221
222 static struct mvebu_pinctrl_soc_info ac5_pinctrl_info;
223
224 static const struct of_device_id ac5_pinctrl_of_match[] = {
225 {
226 .compatible = "marvell,ac5-pinctrl",
227 },
228 { },
229 };
230
231 static const struct mvebu_mpp_ctrl ac5_mpp_controls[] = {
232 MPP_FUNC_CTRL(0, 45, NULL, mvebu_mmio_mpp_ctrl), };
233
234 static struct pinctrl_gpio_range ac5_mpp_gpio_ranges[] = {
235 MPP_GPIO_RANGE(0, 0, 0, 46), };
236
ac5_pinctrl_probe(struct platform_device * pdev)237 static int ac5_pinctrl_probe(struct platform_device *pdev)
238 {
239 struct mvebu_pinctrl_soc_info *soc = &ac5_pinctrl_info;
240
241 soc->variant = 0; /* no variants for ac5 */
242 soc->controls = ac5_mpp_controls;
243 soc->ncontrols = ARRAY_SIZE(ac5_mpp_controls);
244 soc->gpioranges = ac5_mpp_gpio_ranges;
245 soc->ngpioranges = ARRAY_SIZE(ac5_mpp_gpio_ranges);
246 soc->modes = ac5_mpp_modes;
247 soc->nmodes = ac5_mpp_controls[0].npins;
248
249 pdev->dev.platform_data = soc;
250
251 return mvebu_pinctrl_simple_mmio_probe(pdev);
252 }
253
254 static struct platform_driver ac5_pinctrl_driver = {
255 .driver = {
256 .name = "ac5-pinctrl",
257 .of_match_table = of_match_ptr(ac5_pinctrl_of_match),
258 },
259 .probe = ac5_pinctrl_probe,
260 };
261 builtin_platform_driver(ac5_pinctrl_driver);
262
