1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * BRIEF MODULE DESCRIPTION
4 * PCI init for Ralink RT2880 solution
5 *
6 * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
7 *
8 * May 2007 Bruce Chang
9 * Initial Release
10 *
11 * May 2009 Bruce Chang
12 * support RT2880/RT3883 PCIe
13 *
14 * May 2011 Bruce Chang
15 * support RT6855/MT7620 PCIe
16 */
17
18 #include <linux/bitops.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/module.h>
23 #include <linux/of.h>
24 #include <linux/of_address.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/phy/phy.h>
29 #include <linux/platform_device.h>
30 #include <linux/reset.h>
31 #include <linux/sys_soc.h>
32
33 #include "../pci.h"
34
35 /* MediaTek-specific configuration registers */
36 #define PCIE_FTS_NUM 0x70c
37 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
38 #define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
39
40 /* Host-PCI bridge registers */
41 #define RALINK_PCI_PCICFG_ADDR 0x0000
42 #define RALINK_PCI_PCIMSK_ADDR 0x000c
43 #define RALINK_PCI_CONFIG_ADDR 0x0020
44 #define RALINK_PCI_CONFIG_DATA 0x0024
45 #define RALINK_PCI_MEMBASE 0x0028
46 #define RALINK_PCI_IOBASE 0x002c
47
48 /* PCIe RC control registers */
49 #define RALINK_PCI_ID 0x0030
50 #define RALINK_PCI_CLASS 0x0034
51 #define RALINK_PCI_SUBID 0x0038
52 #define RALINK_PCI_STATUS 0x0050
53
54 /* Some definition values */
55 #define PCIE_REVISION_ID BIT(0)
56 #define PCIE_CLASS_CODE (0x60400 << 8)
57 #define PCIE_BAR_MAP_MAX GENMASK(30, 16)
58 #define PCIE_BAR_ENABLE BIT(0)
59 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
60 #define PCIE_PORT_LINKUP BIT(0)
61 #define PCIE_PORT_CNT 3
62
63 #define PERST_DELAY_MS 100
64
65 /**
66 * struct mt7621_pcie_port - PCIe port information
67 * @base: I/O mapped register base
68 * @list: port list
69 * @pcie: pointer to PCIe host info
70 * @clk: pointer to the port clock gate
71 * @phy: pointer to PHY control block
72 * @pcie_rst: pointer to port reset control
73 * @gpio_rst: gpio reset
74 * @slot: port slot
75 * @enabled: indicates if port is enabled
76 */
77 struct mt7621_pcie_port {
78 void __iomem *base;
79 struct list_head list;
80 struct mt7621_pcie *pcie;
81 struct clk *clk;
82 struct phy *phy;
83 struct reset_control *pcie_rst;
84 struct gpio_desc *gpio_rst;
85 u32 slot;
86 bool enabled;
87 };
88
89 /**
90 * struct mt7621_pcie - PCIe host information
91 * @base: IO Mapped Register Base
92 * @dev: Pointer to PCIe device
93 * @ports: pointer to PCIe port information
94 * @resets_inverted: depends on chip revision
95 * reset lines are inverted.
96 */
97 struct mt7621_pcie {
98 struct device *dev;
99 void __iomem *base;
100 struct list_head ports;
101 bool resets_inverted;
102 };
103
pcie_read(struct mt7621_pcie * pcie,u32 reg)104 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
105 {
106 return readl_relaxed(pcie->base + reg);
107 }
108
pcie_write(struct mt7621_pcie * pcie,u32 val,u32 reg)109 static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
110 {
111 writel_relaxed(val, pcie->base + reg);
112 }
113
pcie_port_read(struct mt7621_pcie_port * port,u32 reg)114 static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
115 {
116 return readl_relaxed(port->base + reg);
117 }
118
pcie_port_write(struct mt7621_pcie_port * port,u32 val,u32 reg)119 static inline void pcie_port_write(struct mt7621_pcie_port *port,
120 u32 val, u32 reg)
121 {
122 writel_relaxed(val, port->base + reg);
123 }
124
mt7621_pcie_map_bus(struct pci_bus * bus,unsigned int devfn,int where)125 static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
126 unsigned int devfn, int where)
127 {
128 struct mt7621_pcie *pcie = bus->sysdata;
129 u32 address = PCI_CONF1_EXT_ADDRESS(bus->number, PCI_SLOT(devfn),
130 PCI_FUNC(devfn), where);
131
132 writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
133
134 return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
135 }
136
137 static struct pci_ops mt7621_pcie_ops = {
138 .map_bus = mt7621_pcie_map_bus,
139 .read = pci_generic_config_read,
140 .write = pci_generic_config_write,
141 };
142
read_config(struct mt7621_pcie * pcie,unsigned int dev,u32 reg)143 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
144 {
145 u32 address = PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg);
146
147 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
148 return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
149 }
150
write_config(struct mt7621_pcie * pcie,unsigned int dev,u32 reg,u32 val)151 static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
152 u32 reg, u32 val)
153 {
154 u32 address = PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg);
155
156 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
157 pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
158 }
159
mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port * port)160 static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)
161 {
162 if (port->gpio_rst)
163 gpiod_set_value(port->gpio_rst, 1);
164 }
165
mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port * port)166 static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)
167 {
168 if (port->gpio_rst)
169 gpiod_set_value(port->gpio_rst, 0);
170 }
171
mt7621_pcie_port_is_linkup(struct mt7621_pcie_port * port)172 static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
173 {
174 return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
175 }
176
mt7621_control_assert(struct mt7621_pcie_port * port)177 static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
178 {
179 struct mt7621_pcie *pcie = port->pcie;
180
181 if (pcie->resets_inverted)
182 reset_control_assert(port->pcie_rst);
183 else
184 reset_control_deassert(port->pcie_rst);
185 }
186
mt7621_control_deassert(struct mt7621_pcie_port * port)187 static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
188 {
189 struct mt7621_pcie *pcie = port->pcie;
190
191 if (pcie->resets_inverted)
192 reset_control_deassert(port->pcie_rst);
193 else
194 reset_control_assert(port->pcie_rst);
195 }
196
mt7621_pcie_parse_port(struct mt7621_pcie * pcie,struct device_node * node,int slot)197 static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
198 struct device_node *node,
199 int slot)
200 {
201 struct mt7621_pcie_port *port;
202 struct device *dev = pcie->dev;
203 struct platform_device *pdev = to_platform_device(dev);
204 char name[10];
205 int err;
206
207 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
208 if (!port)
209 return -ENOMEM;
210
211 port->base = devm_platform_ioremap_resource(pdev, slot + 1);
212 if (IS_ERR(port->base))
213 return PTR_ERR(port->base);
214
215 port->clk = devm_get_clk_from_child(dev, node, NULL);
216 if (IS_ERR(port->clk)) {
217 dev_err(dev, "failed to get pcie%d clock\n", slot);
218 return PTR_ERR(port->clk);
219 }
220
221 port->pcie_rst = of_reset_control_get_exclusive(node, NULL);
222 if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
223 dev_err(dev, "failed to get pcie%d reset control\n", slot);
224 return PTR_ERR(port->pcie_rst);
225 }
226
227 snprintf(name, sizeof(name), "pcie-phy%d", slot);
228 port->phy = devm_of_phy_get(dev, node, name);
229 if (IS_ERR(port->phy)) {
230 dev_err(dev, "failed to get pcie-phy%d\n", slot);
231 err = PTR_ERR(port->phy);
232 goto remove_reset;
233 }
234
235 port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
236 GPIOD_OUT_LOW);
237 if (IS_ERR(port->gpio_rst)) {
238 dev_err(dev, "failed to get GPIO for PCIe%d\n", slot);
239 err = PTR_ERR(port->gpio_rst);
240 goto remove_reset;
241 }
242
243 port->slot = slot;
244 port->pcie = pcie;
245
246 INIT_LIST_HEAD(&port->list);
247 list_add_tail(&port->list, &pcie->ports);
248
249 return 0;
250
251 remove_reset:
252 reset_control_put(port->pcie_rst);
253 return err;
254 }
255
mt7621_pcie_parse_dt(struct mt7621_pcie * pcie)256 static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
257 {
258 struct device *dev = pcie->dev;
259 struct platform_device *pdev = to_platform_device(dev);
260 struct device_node *node = dev->of_node, *child;
261 int err;
262
263 pcie->base = devm_platform_ioremap_resource(pdev, 0);
264 if (IS_ERR(pcie->base))
265 return PTR_ERR(pcie->base);
266
267 for_each_available_child_of_node(node, child) {
268 int slot;
269
270 err = of_pci_get_devfn(child);
271 if (err < 0) {
272 of_node_put(child);
273 dev_err(dev, "failed to parse devfn: %d\n", err);
274 return err;
275 }
276
277 slot = PCI_SLOT(err);
278
279 err = mt7621_pcie_parse_port(pcie, child, slot);
280 if (err) {
281 of_node_put(child);
282 return err;
283 }
284 }
285
286 return 0;
287 }
288
mt7621_pcie_init_port(struct mt7621_pcie_port * port)289 static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
290 {
291 struct mt7621_pcie *pcie = port->pcie;
292 struct device *dev = pcie->dev;
293 u32 slot = port->slot;
294 int err;
295
296 err = phy_init(port->phy);
297 if (err) {
298 dev_err(dev, "failed to initialize port%d phy\n", slot);
299 return err;
300 }
301
302 err = phy_power_on(port->phy);
303 if (err) {
304 dev_err(dev, "failed to power on port%d phy\n", slot);
305 phy_exit(port->phy);
306 return err;
307 }
308
309 port->enabled = true;
310
311 return 0;
312 }
313
mt7621_pcie_reset_assert(struct mt7621_pcie * pcie)314 static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)
315 {
316 struct mt7621_pcie_port *port;
317
318 list_for_each_entry(port, &pcie->ports, list) {
319 /* PCIe RC reset assert */
320 mt7621_control_assert(port);
321
322 /* PCIe EP reset assert */
323 mt7621_rst_gpio_pcie_assert(port);
324 }
325
326 msleep(PERST_DELAY_MS);
327 }
328
mt7621_pcie_reset_rc_deassert(struct mt7621_pcie * pcie)329 static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)
330 {
331 struct mt7621_pcie_port *port;
332
333 list_for_each_entry(port, &pcie->ports, list)
334 mt7621_control_deassert(port);
335 }
336
mt7621_pcie_reset_ep_deassert(struct mt7621_pcie * pcie)337 static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)
338 {
339 struct mt7621_pcie_port *port;
340
341 list_for_each_entry(port, &pcie->ports, list)
342 mt7621_rst_gpio_pcie_deassert(port);
343
344 msleep(PERST_DELAY_MS);
345 }
346
mt7621_pcie_init_ports(struct mt7621_pcie * pcie)347 static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
348 {
349 struct device *dev = pcie->dev;
350 struct mt7621_pcie_port *port, *tmp;
351 u8 num_disabled = 0;
352 int err;
353
354 mt7621_pcie_reset_assert(pcie);
355 mt7621_pcie_reset_rc_deassert(pcie);
356
357 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
358 u32 slot = port->slot;
359
360 if (slot == 1) {
361 port->enabled = true;
362 continue;
363 }
364
365 err = mt7621_pcie_init_port(port);
366 if (err) {
367 dev_err(dev, "initializing port %d failed\n", slot);
368 list_del(&port->list);
369 }
370 }
371
372 mt7621_pcie_reset_ep_deassert(pcie);
373
374 tmp = NULL;
375 list_for_each_entry(port, &pcie->ports, list) {
376 u32 slot = port->slot;
377
378 if (!mt7621_pcie_port_is_linkup(port)) {
379 dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
380 slot);
381 mt7621_control_assert(port);
382 port->enabled = false;
383 num_disabled++;
384
385 if (slot == 0) {
386 tmp = port;
387 continue;
388 }
389
390 if (slot == 1 && tmp && !tmp->enabled)
391 phy_power_off(tmp->phy);
392 }
393 }
394
395 return (num_disabled != PCIE_PORT_CNT) ? 0 : -ENODEV;
396 }
397
mt7621_pcie_enable_port(struct mt7621_pcie_port * port)398 static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
399 {
400 struct mt7621_pcie *pcie = port->pcie;
401 u32 slot = port->slot;
402 u32 val;
403
404 /* enable pcie interrupt */
405 val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
406 val |= PCIE_PORT_INT_EN(slot);
407 pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
408
409 /* map 2G DDR region */
410 pcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
411 PCI_BASE_ADDRESS_0);
412
413 /* configure class code and revision ID */
414 pcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID,
415 RALINK_PCI_CLASS);
416
417 /* configure RC FTS number to 250 when it leaves L0s */
418 val = read_config(pcie, slot, PCIE_FTS_NUM);
419 val &= ~PCIE_FTS_NUM_MASK;
420 val |= PCIE_FTS_NUM_L0(0x50);
421 write_config(pcie, slot, PCIE_FTS_NUM, val);
422 }
423
mt7621_pcie_enable_ports(struct pci_host_bridge * host)424 static int mt7621_pcie_enable_ports(struct pci_host_bridge *host)
425 {
426 struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
427 struct device *dev = pcie->dev;
428 struct mt7621_pcie_port *port;
429 struct resource_entry *entry;
430 int err;
431
432 entry = resource_list_first_type(&host->windows, IORESOURCE_IO);
433 if (!entry) {
434 dev_err(dev, "cannot get io resource\n");
435 return -EINVAL;
436 }
437
438 /* Setup MEMWIN and IOWIN */
439 pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
440 pcie_write(pcie, entry->res->start - entry->offset, RALINK_PCI_IOBASE);
441
442 list_for_each_entry(port, &pcie->ports, list) {
443 if (port->enabled) {
444 err = clk_prepare_enable(port->clk);
445 if (err) {
446 dev_err(dev, "enabling clk pcie%d\n",
447 port->slot);
448 return err;
449 }
450
451 mt7621_pcie_enable_port(port);
452 dev_info(dev, "PCIE%d enabled\n", port->slot);
453 }
454 }
455
456 return 0;
457 }
458
mt7621_pcie_register_host(struct pci_host_bridge * host)459 static int mt7621_pcie_register_host(struct pci_host_bridge *host)
460 {
461 struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
462
463 host->ops = &mt7621_pcie_ops;
464 host->sysdata = pcie;
465 return pci_host_probe(host);
466 }
467
468 static const struct soc_device_attribute mt7621_pcie_quirks_match[] = {
469 { .soc_id = "mt7621", .revision = "E2" }
470 };
471
mt7621_pcie_probe(struct platform_device * pdev)472 static int mt7621_pcie_probe(struct platform_device *pdev)
473 {
474 struct device *dev = &pdev->dev;
475 const struct soc_device_attribute *attr;
476 struct mt7621_pcie_port *port;
477 struct mt7621_pcie *pcie;
478 struct pci_host_bridge *bridge;
479 int err;
480
481 if (!dev->of_node)
482 return -ENODEV;
483
484 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
485 if (!bridge)
486 return -ENOMEM;
487
488 pcie = pci_host_bridge_priv(bridge);
489 pcie->dev = dev;
490 platform_set_drvdata(pdev, pcie);
491 INIT_LIST_HEAD(&pcie->ports);
492
493 attr = soc_device_match(mt7621_pcie_quirks_match);
494 if (attr)
495 pcie->resets_inverted = true;
496
497 err = mt7621_pcie_parse_dt(pcie);
498 if (err) {
499 dev_err(dev, "parsing DT failed\n");
500 return err;
501 }
502
503 err = mt7621_pcie_init_ports(pcie);
504 if (err) {
505 dev_err(dev, "nothing connected in virtual bridges\n");
506 return 0;
507 }
508
509 err = mt7621_pcie_enable_ports(bridge);
510 if (err) {
511 dev_err(dev, "error enabling pcie ports\n");
512 goto remove_resets;
513 }
514
515 return mt7621_pcie_register_host(bridge);
516
517 remove_resets:
518 list_for_each_entry(port, &pcie->ports, list)
519 reset_control_put(port->pcie_rst);
520
521 return err;
522 }
523
mt7621_pcie_remove(struct platform_device * pdev)524 static int mt7621_pcie_remove(struct platform_device *pdev)
525 {
526 struct mt7621_pcie *pcie = platform_get_drvdata(pdev);
527 struct mt7621_pcie_port *port;
528
529 list_for_each_entry(port, &pcie->ports, list)
530 reset_control_put(port->pcie_rst);
531
532 return 0;
533 }
534
535 static const struct of_device_id mt7621_pcie_ids[] = {
536 { .compatible = "mediatek,mt7621-pci" },
537 {},
538 };
539 MODULE_DEVICE_TABLE(of, mt7621_pcie_ids);
540
541 static struct platform_driver mt7621_pcie_driver = {
542 .probe = mt7621_pcie_probe,
543 .remove = mt7621_pcie_remove,
544 .driver = {
545 .name = "mt7621-pci",
546 .of_match_table = mt7621_pcie_ids,
547 },
548 };
549 builtin_platform_driver(mt7621_pcie_driver);
550
551 MODULE_LICENSE("GPL v2");
552
