1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * NXP Wireless LAN device driver: PCIE specific handling
4 *
5 * Copyright 2011-2020 NXP
6 */
7
8 #include <linux/iopoll.h>
9 #include <linux/firmware.h>
10
11 #include "decl.h"
12 #include "ioctl.h"
13 #include "util.h"
14 #include "fw.h"
15 #include "main.h"
16 #include "wmm.h"
17 #include "11n.h"
18 #include "pcie.h"
19 #include "pcie_quirks.h"
20
21 #define PCIE_VERSION "1.0"
22 #define DRV_NAME "Marvell mwifiex PCIe"
23
24 static struct mwifiex_if_ops pcie_ops;
25
26 static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
27 .cmd_addr_lo = PCIE_SCRATCH_0_REG,
28 .cmd_addr_hi = PCIE_SCRATCH_1_REG,
29 .cmd_size = PCIE_SCRATCH_2_REG,
30 .fw_status = PCIE_SCRATCH_3_REG,
31 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
32 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
33 .tx_rdptr = PCIE_SCRATCH_6_REG,
34 .tx_wrptr = PCIE_SCRATCH_7_REG,
35 .rx_rdptr = PCIE_SCRATCH_8_REG,
36 .rx_wrptr = PCIE_SCRATCH_9_REG,
37 .evt_rdptr = PCIE_SCRATCH_10_REG,
38 .evt_wrptr = PCIE_SCRATCH_11_REG,
39 .drv_rdy = PCIE_SCRATCH_12_REG,
40 .tx_start_ptr = 0,
41 .tx_mask = MWIFIEX_TXBD_MASK,
42 .tx_wrap_mask = 0,
43 .rx_mask = MWIFIEX_RXBD_MASK,
44 .rx_wrap_mask = 0,
45 .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
46 .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
47 .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
48 .ring_flag_sop = 0,
49 .ring_flag_eop = 0,
50 .ring_flag_xs_sop = 0,
51 .ring_flag_xs_eop = 0,
52 .ring_tx_start_ptr = 0,
53 .pfu_enabled = 0,
54 .sleep_cookie = 1,
55 .msix_support = 0,
56 };
57
58 static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
59 .cmd_addr_lo = PCIE_SCRATCH_0_REG,
60 .cmd_addr_hi = PCIE_SCRATCH_1_REG,
61 .cmd_size = PCIE_SCRATCH_2_REG,
62 .fw_status = PCIE_SCRATCH_3_REG,
63 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
64 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
65 .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
66 .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
67 .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
68 .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
69 .evt_rdptr = PCIE_SCRATCH_10_REG,
70 .evt_wrptr = PCIE_SCRATCH_11_REG,
71 .drv_rdy = PCIE_SCRATCH_12_REG,
72 .tx_start_ptr = 16,
73 .tx_mask = 0x03FF0000,
74 .tx_wrap_mask = 0x07FF0000,
75 .rx_mask = 0x000003FF,
76 .rx_wrap_mask = 0x000007FF,
77 .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
78 .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
79 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
80 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
81 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
82 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
83 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
84 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
85 .pfu_enabled = 1,
86 .sleep_cookie = 0,
87 .fw_dump_ctrl = PCIE_SCRATCH_13_REG,
88 .fw_dump_start = PCIE_SCRATCH_14_REG,
89 .fw_dump_end = 0xcff,
90 .fw_dump_host_ready = 0xee,
91 .fw_dump_read_done = 0xfe,
92 .msix_support = 0,
93 };
94
95 static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
96 .cmd_addr_lo = PCIE_SCRATCH_0_REG,
97 .cmd_addr_hi = PCIE_SCRATCH_1_REG,
98 .cmd_size = PCIE_SCRATCH_2_REG,
99 .fw_status = PCIE_SCRATCH_3_REG,
100 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
101 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
102 .tx_rdptr = 0xC1A4,
103 .tx_wrptr = 0xC174,
104 .rx_rdptr = 0xC174,
105 .rx_wrptr = 0xC1A4,
106 .evt_rdptr = PCIE_SCRATCH_10_REG,
107 .evt_wrptr = PCIE_SCRATCH_11_REG,
108 .drv_rdy = PCIE_SCRATCH_12_REG,
109 .tx_start_ptr = 16,
110 .tx_mask = 0x0FFF0000,
111 .tx_wrap_mask = 0x1FFF0000,
112 .rx_mask = 0x00000FFF,
113 .rx_wrap_mask = 0x00001FFF,
114 .tx_rollover_ind = BIT(28),
115 .rx_rollover_ind = BIT(12),
116 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
117 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
118 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
119 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
120 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
121 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
122 .pfu_enabled = 1,
123 .sleep_cookie = 0,
124 .fw_dump_ctrl = PCIE_SCRATCH_13_REG,
125 .fw_dump_start = PCIE_SCRATCH_14_REG,
126 .fw_dump_end = 0xcff,
127 .fw_dump_host_ready = 0xcc,
128 .fw_dump_read_done = 0xdd,
129 .msix_support = 0,
130 };
131
132 static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {
133 {"ITCM", NULL, 0, 0xF0},
134 {"DTCM", NULL, 0, 0xF1},
135 {"SQRAM", NULL, 0, 0xF2},
136 {"IRAM", NULL, 0, 0xF3},
137 {"APU", NULL, 0, 0xF4},
138 {"CIU", NULL, 0, 0xF5},
139 {"ICU", NULL, 0, 0xF6},
140 {"MAC", NULL, 0, 0xF7},
141 };
142
143 static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {
144 {"DUMP", NULL, 0, 0xDD},
145 };
146
147 static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
148 .reg = &mwifiex_reg_8766,
149 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
150 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
151 .can_dump_fw = false,
152 .can_ext_scan = true,
153 };
154
155 static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
156 .reg = &mwifiex_reg_8897,
157 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
158 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
159 .can_dump_fw = true,
160 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,
161 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),
162 .can_ext_scan = true,
163 };
164
165 static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
166 .reg = &mwifiex_reg_8997,
167 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
168 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
169 .can_dump_fw = true,
170 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,
171 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),
172 .can_ext_scan = true,
173 };
174
175 static const struct of_device_id mwifiex_pcie_of_match_table[] = {
176 { .compatible = "pci11ab,2b42" },
177 { .compatible = "pci1b4b,2b42" },
178 { }
179 };
180
mwifiex_pcie_probe_of(struct device * dev)181 static int mwifiex_pcie_probe_of(struct device *dev)
182 {
183 if (!of_match_node(mwifiex_pcie_of_match_table, dev->of_node)) {
184 dev_err(dev, "required compatible string missing\n");
185 return -EINVAL;
186 }
187
188 return 0;
189 }
190
191 static void mwifiex_pcie_work(struct work_struct *work);
192
193 static int
mwifiex_map_pci_memory(struct mwifiex_adapter * adapter,struct sk_buff * skb,size_t size,int flags)194 mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb,
195 size_t size, int flags)
196 {
197 struct pcie_service_card *card = adapter->card;
198 struct mwifiex_dma_mapping mapping;
199
200 mapping.addr = dma_map_single(&card->dev->dev, skb->data, size, flags);
201 if (dma_mapping_error(&card->dev->dev, mapping.addr)) {
202 mwifiex_dbg(adapter, ERROR, "failed to map pci memory!\n");
203 return -1;
204 }
205 mapping.len = size;
206 mwifiex_store_mapping(skb, &mapping);
207 return 0;
208 }
209
mwifiex_unmap_pci_memory(struct mwifiex_adapter * adapter,struct sk_buff * skb,int flags)210 static void mwifiex_unmap_pci_memory(struct mwifiex_adapter *adapter,
211 struct sk_buff *skb, int flags)
212 {
213 struct pcie_service_card *card = adapter->card;
214 struct mwifiex_dma_mapping mapping;
215
216 mwifiex_get_mapping(skb, &mapping);
217 dma_unmap_single(&card->dev->dev, mapping.addr, mapping.len, flags);
218 }
219
220 /*
221 * This function writes data into PCIE card register.
222 */
mwifiex_write_reg(struct mwifiex_adapter * adapter,int reg,u32 data)223 static int mwifiex_write_reg(struct mwifiex_adapter *adapter, int reg, u32 data)
224 {
225 struct pcie_service_card *card = adapter->card;
226
227 iowrite32(data, card->pci_mmap1 + reg);
228
229 return 0;
230 }
231
232 /* This function reads data from PCIE card register.
233 */
mwifiex_read_reg(struct mwifiex_adapter * adapter,int reg,u32 * data)234 static int mwifiex_read_reg(struct mwifiex_adapter *adapter, int reg, u32 *data)
235 {
236 struct pcie_service_card *card = adapter->card;
237
238 *data = ioread32(card->pci_mmap1 + reg);
239 if (*data == 0xffffffff)
240 return 0xffffffff;
241
242 return 0;
243 }
244
245 /* This function reads u8 data from PCIE card register. */
mwifiex_read_reg_byte(struct mwifiex_adapter * adapter,int reg,u8 * data)246 static int mwifiex_read_reg_byte(struct mwifiex_adapter *adapter,
247 int reg, u8 *data)
248 {
249 struct pcie_service_card *card = adapter->card;
250
251 *data = ioread8(card->pci_mmap1 + reg);
252
253 return 0;
254 }
255
256 /*
257 * This function reads sleep cookie and checks if FW is ready
258 */
mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter * adapter)259 static bool mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter *adapter)
260 {
261 u32 cookie_value;
262 struct pcie_service_card *card = adapter->card;
263 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
264
265 if (!reg->sleep_cookie)
266 return true;
267
268 if (card->sleep_cookie_vbase) {
269 cookie_value = get_unaligned_le32(card->sleep_cookie_vbase);
270 mwifiex_dbg(adapter, INFO,
271 "info: ACCESS_HW: sleep cookie=0x%x\n",
272 cookie_value);
273 if (cookie_value == FW_AWAKE_COOKIE)
274 return true;
275 }
276
277 return false;
278 }
279
280 #ifdef CONFIG_PM_SLEEP
281 /*
282 * Kernel needs to suspend all functions separately. Therefore all
283 * registered functions must have drivers with suspend and resume
284 * methods. Failing that the kernel simply removes the whole card.
285 *
286 * If already not suspended, this function allocates and sends a host
287 * sleep activate request to the firmware and turns off the traffic.
288 */
mwifiex_pcie_suspend(struct device * dev)289 static int mwifiex_pcie_suspend(struct device *dev)
290 {
291 struct mwifiex_adapter *adapter;
292 struct pcie_service_card *card = dev_get_drvdata(dev);
293
294
295 /* Might still be loading firmware */
296 wait_for_completion(&card->fw_done);
297
298 adapter = card->adapter;
299 if (!adapter) {
300 dev_err(dev, "adapter is not valid\n");
301 return 0;
302 }
303
304 mwifiex_enable_wake(adapter);
305
306 /* Enable the Host Sleep */
307 if (!mwifiex_enable_hs(adapter)) {
308 mwifiex_dbg(adapter, ERROR,
309 "cmd: failed to suspend\n");
310 clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags);
311 mwifiex_disable_wake(adapter);
312 return -EFAULT;
313 }
314
315 flush_workqueue(adapter->workqueue);
316
317 /* Indicate device suspended */
318 set_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags);
319 clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags);
320
321 return 0;
322 }
323
324 /*
325 * Kernel needs to suspend all functions separately. Therefore all
326 * registered functions must have drivers with suspend and resume
327 * methods. Failing that the kernel simply removes the whole card.
328 *
329 * If already not resumed, this function turns on the traffic and
330 * sends a host sleep cancel request to the firmware.
331 */
mwifiex_pcie_resume(struct device * dev)332 static int mwifiex_pcie_resume(struct device *dev)
333 {
334 struct mwifiex_adapter *adapter;
335 struct pcie_service_card *card = dev_get_drvdata(dev);
336
337
338 if (!card->adapter) {
339 dev_err(dev, "adapter structure is not valid\n");
340 return 0;
341 }
342
343 adapter = card->adapter;
344
345 if (!test_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags)) {
346 mwifiex_dbg(adapter, WARN,
347 "Device already resumed\n");
348 return 0;
349 }
350
351 clear_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags);
352
353 mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA),
354 MWIFIEX_ASYNC_CMD);
355 mwifiex_disable_wake(adapter);
356
357 return 0;
358 }
359 #endif
360
361 /*
362 * This function probes an mwifiex device and registers it. It allocates
363 * the card structure, enables PCIE function number and initiates the
364 * device registration and initialization procedure by adding a logical
365 * interface.
366 */
mwifiex_pcie_probe(struct pci_dev * pdev,const struct pci_device_id * ent)367 static int mwifiex_pcie_probe(struct pci_dev *pdev,
368 const struct pci_device_id *ent)
369 {
370 struct pcie_service_card *card;
371 int ret;
372
373 pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n",
374 pdev->vendor, pdev->device, pdev->revision);
375
376 card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
377 if (!card)
378 return -ENOMEM;
379
380 init_completion(&card->fw_done);
381
382 card->dev = pdev;
383
384 if (ent->driver_data) {
385 struct mwifiex_pcie_device *data = (void *)ent->driver_data;
386 card->pcie.reg = data->reg;
387 card->pcie.blksz_fw_dl = data->blksz_fw_dl;
388 card->pcie.tx_buf_size = data->tx_buf_size;
389 card->pcie.can_dump_fw = data->can_dump_fw;
390 card->pcie.mem_type_mapping_tbl = data->mem_type_mapping_tbl;
391 card->pcie.num_mem_types = data->num_mem_types;
392 card->pcie.can_ext_scan = data->can_ext_scan;
393 INIT_WORK(&card->work, mwifiex_pcie_work);
394 }
395
396 /* device tree node parsing and platform specific configuration*/
397 if (pdev->dev.of_node) {
398 ret = mwifiex_pcie_probe_of(&pdev->dev);
399 if (ret)
400 return ret;
401 }
402
403 /* check quirks */
404 mwifiex_initialize_quirks(card);
405
406 if (mwifiex_add_card(card, &card->fw_done, &pcie_ops,
407 MWIFIEX_PCIE, &pdev->dev)) {
408 pr_err("%s failed\n", __func__);
409 return -1;
410 }
411
412 return 0;
413 }
414
415 /*
416 * This function removes the interface and frees up the card structure.
417 */
mwifiex_pcie_remove(struct pci_dev * pdev)418 static void mwifiex_pcie_remove(struct pci_dev *pdev)
419 {
420 struct pcie_service_card *card;
421 struct mwifiex_adapter *adapter;
422 struct mwifiex_private *priv;
423 const struct mwifiex_pcie_card_reg *reg;
424 u32 fw_status;
425
426 card = pci_get_drvdata(pdev);
427
428 wait_for_completion(&card->fw_done);
429
430 adapter = card->adapter;
431 if (!adapter || !adapter->priv_num)
432 return;
433
434 reg = card->pcie.reg;
435 if (reg)
436 mwifiex_read_reg(adapter, reg->fw_status, &fw_status);
437 else
438 fw_status = -1;
439
440 if (fw_status == FIRMWARE_READY_PCIE && !adapter->mfg_mode) {
441 mwifiex_deauthenticate_all(adapter);
442
443 priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY);
444
445 mwifiex_disable_auto_ds(priv);
446
447 mwifiex_init_shutdown_fw(priv, MWIFIEX_FUNC_SHUTDOWN);
448 }
449
450 mwifiex_remove_card(adapter);
451 }
452
mwifiex_pcie_shutdown(struct pci_dev * pdev)453 static void mwifiex_pcie_shutdown(struct pci_dev *pdev)
454 {
455 mwifiex_pcie_remove(pdev);
456
457 return;
458 }
459
mwifiex_pcie_coredump(struct device * dev)460 static void mwifiex_pcie_coredump(struct device *dev)
461 {
462 struct pci_dev *pdev;
463 struct pcie_service_card *card;
464
465 pdev = container_of(dev, struct pci_dev, dev);
466 card = pci_get_drvdata(pdev);
467
468 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP,
469 &card->work_flags))
470 schedule_work(&card->work);
471 }
472
473 static const struct pci_device_id mwifiex_ids[] = {
474 {
475 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8766P,
476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
477 .driver_data = (unsigned long)&mwifiex_pcie8766,
478 },
479 {
480 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8897,
481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
482 .driver_data = (unsigned long)&mwifiex_pcie8897,
483 },
484 {
485 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997,
486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
487 .driver_data = (unsigned long)&mwifiex_pcie8997,
488 },
489 {
490 PCIE_VENDOR_ID_V2_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997,
491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
492 .driver_data = (unsigned long)&mwifiex_pcie8997,
493 },
494 {},
495 };
496
497 MODULE_DEVICE_TABLE(pci, mwifiex_ids);
498
499 /*
500 * Cleanup all software without cleaning anything related to PCIe and HW.
501 */
mwifiex_pcie_reset_prepare(struct pci_dev * pdev)502 static void mwifiex_pcie_reset_prepare(struct pci_dev *pdev)
503 {
504 struct pcie_service_card *card = pci_get_drvdata(pdev);
505 struct mwifiex_adapter *adapter = card->adapter;
506
507 if (!adapter) {
508 dev_err(&pdev->dev, "%s: adapter structure is not valid\n",
509 __func__);
510 return;
511 }
512
513 mwifiex_dbg(adapter, INFO,
514 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Pre-FLR\n",
515 __func__, pdev->vendor, pdev->device, pdev->revision);
516
517 mwifiex_shutdown_sw(adapter);
518 clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &card->work_flags);
519 clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags);
520
521 /* On MS Surface gen4+ devices FLR isn't effective to recover from
522 * hangups, so we power-cycle the card instead.
523 */
524 if (card->quirks & QUIRK_FW_RST_D3COLD)
525 mwifiex_pcie_reset_d3cold_quirk(pdev);
526
527 mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__);
528
529 card->pci_reset_ongoing = true;
530 }
531
532 /*
533 * Kernel stores and restores PCIe function context before and after performing
534 * FLR respectively. Reconfigure the software and firmware including firmware
535 * redownload.
536 */
mwifiex_pcie_reset_done(struct pci_dev * pdev)537 static void mwifiex_pcie_reset_done(struct pci_dev *pdev)
538 {
539 struct pcie_service_card *card = pci_get_drvdata(pdev);
540 struct mwifiex_adapter *adapter = card->adapter;
541 int ret;
542
543 if (!adapter) {
544 dev_err(&pdev->dev, "%s: adapter structure is not valid\n",
545 __func__);
546 return;
547 }
548
549 mwifiex_dbg(adapter, INFO,
550 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Post-FLR\n",
551 __func__, pdev->vendor, pdev->device, pdev->revision);
552
553 ret = mwifiex_reinit_sw(adapter);
554 if (ret)
555 dev_err(&pdev->dev, "reinit failed: %d\n", ret);
556 else
557 mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__);
558
559 card->pci_reset_ongoing = false;
560 }
561
562 static const struct pci_error_handlers mwifiex_pcie_err_handler = {
563 .reset_prepare = mwifiex_pcie_reset_prepare,
564 .reset_done = mwifiex_pcie_reset_done,
565 };
566
567 #ifdef CONFIG_PM_SLEEP
568 /* Power Management Hooks */
569 static SIMPLE_DEV_PM_OPS(mwifiex_pcie_pm_ops, mwifiex_pcie_suspend,
570 mwifiex_pcie_resume);
571 #endif
572
573 /* PCI Device Driver */
574 static struct pci_driver mwifiex_pcie = {
575 .name = "mwifiex_pcie",
576 .id_table = mwifiex_ids,
577 .probe = mwifiex_pcie_probe,
578 .remove = mwifiex_pcie_remove,
579 .driver = {
580 .coredump = mwifiex_pcie_coredump,
581 #ifdef CONFIG_PM_SLEEP
582 .pm = &mwifiex_pcie_pm_ops,
583 #endif
584 },
585 .shutdown = mwifiex_pcie_shutdown,
586 .err_handler = &mwifiex_pcie_err_handler,
587 };
588
589 /*
590 * This function adds delay loop to ensure FW is awake before proceeding.
591 */
mwifiex_pcie_dev_wakeup_delay(struct mwifiex_adapter * adapter)592 static void mwifiex_pcie_dev_wakeup_delay(struct mwifiex_adapter *adapter)
593 {
594 int i = 0;
595
596 while (mwifiex_pcie_ok_to_access_hw(adapter)) {
597 i++;
598 usleep_range(10, 20);
599 /* 50ms max wait */
600 if (i == 5000)
601 break;
602 }
603
604 return;
605 }
606
mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter * adapter,u32 max_delay_loop_cnt)607 static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter,
608 u32 max_delay_loop_cnt)
609 {
610 struct pcie_service_card *card = adapter->card;
611 u8 *buffer;
612 u32 sleep_cookie, count;
613 struct sk_buff *cmdrsp = card->cmdrsp_buf;
614
615 for (count = 0; count < max_delay_loop_cnt; count++) {
616 dma_sync_single_for_cpu(&card->dev->dev,
617 MWIFIEX_SKB_DMA_ADDR(cmdrsp),
618 sizeof(sleep_cookie), DMA_FROM_DEVICE);
619 buffer = cmdrsp->data;
620 sleep_cookie = get_unaligned_le32(buffer);
621
622 if (sleep_cookie == MWIFIEX_DEF_SLEEP_COOKIE) {
623 mwifiex_dbg(adapter, INFO,
624 "sleep cookie found at count %d\n", count);
625 break;
626 }
627 dma_sync_single_for_device(&card->dev->dev,
628 MWIFIEX_SKB_DMA_ADDR(cmdrsp),
629 sizeof(sleep_cookie),
630 DMA_FROM_DEVICE);
631 usleep_range(20, 30);
632 }
633
634 if (count >= max_delay_loop_cnt)
635 mwifiex_dbg(adapter, INFO,
636 "max count reached while accessing sleep cookie\n");
637 }
638
639 #define N_WAKEUP_TRIES_SHORT_INTERVAL 15
640 #define N_WAKEUP_TRIES_LONG_INTERVAL 35
641
642 /* This function wakes up the card by reading fw_status register. */
mwifiex_pm_wakeup_card(struct mwifiex_adapter * adapter)643 static int mwifiex_pm_wakeup_card(struct mwifiex_adapter *adapter)
644 {
645 struct pcie_service_card *card = adapter->card;
646 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
647 int retval __maybe_unused;
648
649 mwifiex_dbg(adapter, EVENT,
650 "event: Wakeup device...\n");
651
652 if (reg->sleep_cookie)
653 mwifiex_pcie_dev_wakeup_delay(adapter);
654
655 /* The 88W8897 PCIe+USB firmware (latest version 15.68.19.p21) sometimes
656 * appears to ignore or miss our wakeup request, so we continue trying
657 * until we receive an interrupt from the card.
658 */
659 if (read_poll_timeout(mwifiex_write_reg, retval,
660 READ_ONCE(adapter->int_status) != 0,
661 500, 500 * N_WAKEUP_TRIES_SHORT_INTERVAL,
662 false,
663 adapter, reg->fw_status, FIRMWARE_READY_PCIE)) {
664 if (read_poll_timeout(mwifiex_write_reg, retval,
665 READ_ONCE(adapter->int_status) != 0,
666 10000, 10000 * N_WAKEUP_TRIES_LONG_INTERVAL,
667 false,
668 adapter, reg->fw_status, FIRMWARE_READY_PCIE)) {
669 mwifiex_dbg(adapter, ERROR,
670 "Firmware didn't wake up\n");
671 return -EIO;
672 }
673 }
674
675 if (reg->sleep_cookie) {
676 mwifiex_pcie_dev_wakeup_delay(adapter);
677 mwifiex_dbg(adapter, INFO,
678 "PCIE wakeup: Setting PS_STATE_AWAKE\n");
679 adapter->ps_state = PS_STATE_AWAKE;
680 }
681
682 return 0;
683 }
684
685 /*
686 * This function is called after the card has woken up.
687 *
688 * The card configuration register is reset.
689 */
mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter * adapter)690 static int mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter *adapter)
691 {
692 mwifiex_dbg(adapter, CMD,
693 "cmd: Wakeup device completed\n");
694
695 return 0;
696 }
697
698 /*
699 * This function disables the host interrupt.
700 *
701 * The host interrupt mask is read, the disable bit is reset and
702 * written back to the card host interrupt mask register.
703 */
mwifiex_pcie_disable_host_int(struct mwifiex_adapter * adapter)704 static int mwifiex_pcie_disable_host_int(struct mwifiex_adapter *adapter)
705 {
706 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
707 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK,
708 0x00000000)) {
709 mwifiex_dbg(adapter, ERROR,
710 "Disable host interrupt failed\n");
711 return -1;
712 }
713 }
714
715 atomic_set(&adapter->tx_hw_pending, 0);
716 return 0;
717 }
718
mwifiex_pcie_disable_host_int_noerr(struct mwifiex_adapter * adapter)719 static void mwifiex_pcie_disable_host_int_noerr(struct mwifiex_adapter *adapter)
720 {
721 WARN_ON(mwifiex_pcie_disable_host_int(adapter));
722 }
723
724 /*
725 * This function enables the host interrupt.
726 *
727 * The host interrupt enable mask is written to the card
728 * host interrupt mask register.
729 */
mwifiex_pcie_enable_host_int(struct mwifiex_adapter * adapter)730 static int mwifiex_pcie_enable_host_int(struct mwifiex_adapter *adapter)
731 {
732 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
733 /* Simply write the mask to the register */
734 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK,
735 HOST_INTR_MASK)) {
736 mwifiex_dbg(adapter, ERROR,
737 "Enable host interrupt failed\n");
738 return -1;
739 }
740 }
741
742 return 0;
743 }
744
745 /*
746 * This function initializes TX buffer ring descriptors
747 */
mwifiex_init_txq_ring(struct mwifiex_adapter * adapter)748 static int mwifiex_init_txq_ring(struct mwifiex_adapter *adapter)
749 {
750 struct pcie_service_card *card = adapter->card;
751 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
752 struct mwifiex_pcie_buf_desc *desc;
753 struct mwifiex_pfu_buf_desc *desc2;
754 int i;
755
756 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
757 card->tx_buf_list[i] = NULL;
758 if (reg->pfu_enabled) {
759 card->txbd_ring[i] = (void *)card->txbd_ring_vbase +
760 (sizeof(*desc2) * i);
761 desc2 = card->txbd_ring[i];
762 memset(desc2, 0, sizeof(*desc2));
763 } else {
764 card->txbd_ring[i] = (void *)card->txbd_ring_vbase +
765 (sizeof(*desc) * i);
766 desc = card->txbd_ring[i];
767 memset(desc, 0, sizeof(*desc));
768 }
769 }
770
771 return 0;
772 }
773
774 /* This function initializes RX buffer ring descriptors. Each SKB is allocated
775 * here and after mapping PCI memory, its physical address is assigned to
776 * PCIE Rx buffer descriptor's physical address.
777 */
mwifiex_init_rxq_ring(struct mwifiex_adapter * adapter)778 static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter)
779 {
780 struct pcie_service_card *card = adapter->card;
781 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
782 struct sk_buff *skb;
783 struct mwifiex_pcie_buf_desc *desc;
784 struct mwifiex_pfu_buf_desc *desc2;
785 dma_addr_t buf_pa;
786 int i;
787
788 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
789 /* Allocate skb here so that firmware can DMA data from it */
790 skb = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE,
791 GFP_KERNEL);
792 if (!skb) {
793 mwifiex_dbg(adapter, ERROR,
794 "Unable to allocate skb for RX ring.\n");
795 kfree(card->rxbd_ring_vbase);
796 return -ENOMEM;
797 }
798
799 if (mwifiex_map_pci_memory(adapter, skb,
800 MWIFIEX_RX_DATA_BUF_SIZE,
801 DMA_FROM_DEVICE))
802 return -1;
803
804 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
805
806 mwifiex_dbg(adapter, INFO,
807 "info: RX ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n",
808 skb, skb->len, skb->data, (u32)buf_pa,
809 (u32)((u64)buf_pa >> 32));
810
811 card->rx_buf_list[i] = skb;
812 if (reg->pfu_enabled) {
813 card->rxbd_ring[i] = (void *)card->rxbd_ring_vbase +
814 (sizeof(*desc2) * i);
815 desc2 = card->rxbd_ring[i];
816 desc2->paddr = buf_pa;
817 desc2->len = (u16)skb->len;
818 desc2->frag_len = (u16)skb->len;
819 desc2->flags = reg->ring_flag_eop | reg->ring_flag_sop;
820 desc2->offset = 0;
821 } else {
822 card->rxbd_ring[i] = (void *)(card->rxbd_ring_vbase +
823 (sizeof(*desc) * i));
824 desc = card->rxbd_ring[i];
825 desc->paddr = buf_pa;
826 desc->len = (u16)skb->len;
827 desc->flags = 0;
828 }
829 }
830
831 return 0;
832 }
833
834 /* This function initializes event buffer ring descriptors. Each SKB is
835 * allocated here and after mapping PCI memory, its physical address is assigned
836 * to PCIE Rx buffer descriptor's physical address
837 */
mwifiex_pcie_init_evt_ring(struct mwifiex_adapter * adapter)838 static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter)
839 {
840 struct pcie_service_card *card = adapter->card;
841 struct mwifiex_evt_buf_desc *desc;
842 struct sk_buff *skb;
843 dma_addr_t buf_pa;
844 int i;
845
846 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) {
847 /* Allocate skb here so that firmware can DMA data from it */
848 skb = dev_alloc_skb(MAX_EVENT_SIZE);
849 if (!skb) {
850 mwifiex_dbg(adapter, ERROR,
851 "Unable to allocate skb for EVENT buf.\n");
852 kfree(card->evtbd_ring_vbase);
853 return -ENOMEM;
854 }
855 skb_put(skb, MAX_EVENT_SIZE);
856
857 if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE,
858 DMA_FROM_DEVICE)) {
859 kfree_skb(skb);
860 kfree(card->evtbd_ring_vbase);
861 return -1;
862 }
863
864 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
865
866 mwifiex_dbg(adapter, EVENT,
867 "info: EVT ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n",
868 skb, skb->len, skb->data, (u32)buf_pa,
869 (u32)((u64)buf_pa >> 32));
870
871 card->evt_buf_list[i] = skb;
872 card->evtbd_ring[i] = (void *)(card->evtbd_ring_vbase +
873 (sizeof(*desc) * i));
874 desc = card->evtbd_ring[i];
875 desc->paddr = buf_pa;
876 desc->len = (u16)skb->len;
877 desc->flags = 0;
878 }
879
880 return 0;
881 }
882
883 /* This function cleans up TX buffer rings. If any of the buffer list has valid
884 * SKB address, associated SKB is freed.
885 */
mwifiex_cleanup_txq_ring(struct mwifiex_adapter * adapter)886 static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter)
887 {
888 struct pcie_service_card *card = adapter->card;
889 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
890 struct sk_buff *skb;
891 struct mwifiex_pcie_buf_desc *desc;
892 struct mwifiex_pfu_buf_desc *desc2;
893 int i;
894
895 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
896 if (reg->pfu_enabled) {
897 desc2 = card->txbd_ring[i];
898 if (card->tx_buf_list[i]) {
899 skb = card->tx_buf_list[i];
900 mwifiex_unmap_pci_memory(adapter, skb,
901 DMA_TO_DEVICE);
902 dev_kfree_skb_any(skb);
903 }
904 memset(desc2, 0, sizeof(*desc2));
905 } else {
906 desc = card->txbd_ring[i];
907 if (card->tx_buf_list[i]) {
908 skb = card->tx_buf_list[i];
909 mwifiex_unmap_pci_memory(adapter, skb,
910 DMA_TO_DEVICE);
911 dev_kfree_skb_any(skb);
912 }
913 memset(desc, 0, sizeof(*desc));
914 }
915 card->tx_buf_list[i] = NULL;
916 }
917
918 atomic_set(&adapter->tx_hw_pending, 0);
919 return;
920 }
921
922 /* This function cleans up RX buffer rings. If any of the buffer list has valid
923 * SKB address, associated SKB is freed.
924 */
mwifiex_cleanup_rxq_ring(struct mwifiex_adapter * adapter)925 static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter)
926 {
927 struct pcie_service_card *card = adapter->card;
928 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
929 struct mwifiex_pcie_buf_desc *desc;
930 struct mwifiex_pfu_buf_desc *desc2;
931 struct sk_buff *skb;
932 int i;
933
934 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
935 if (reg->pfu_enabled) {
936 desc2 = card->rxbd_ring[i];
937 if (card->rx_buf_list[i]) {
938 skb = card->rx_buf_list[i];
939 mwifiex_unmap_pci_memory(adapter, skb,
940 DMA_FROM_DEVICE);
941 dev_kfree_skb_any(skb);
942 }
943 memset(desc2, 0, sizeof(*desc2));
944 } else {
945 desc = card->rxbd_ring[i];
946 if (card->rx_buf_list[i]) {
947 skb = card->rx_buf_list[i];
948 mwifiex_unmap_pci_memory(adapter, skb,
949 DMA_FROM_DEVICE);
950 dev_kfree_skb_any(skb);
951 }
952 memset(desc, 0, sizeof(*desc));
953 }
954 card->rx_buf_list[i] = NULL;
955 }
956
957 return;
958 }
959
960 /* This function cleans up event buffer rings. If any of the buffer list has
961 * valid SKB address, associated SKB is freed.
962 */
mwifiex_cleanup_evt_ring(struct mwifiex_adapter * adapter)963 static void mwifiex_cleanup_evt_ring(struct mwifiex_adapter *adapter)
964 {
965 struct pcie_service_card *card = adapter->card;
966 struct mwifiex_evt_buf_desc *desc;
967 struct sk_buff *skb;
968 int i;
969
970 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) {
971 desc = card->evtbd_ring[i];
972 if (card->evt_buf_list[i]) {
973 skb = card->evt_buf_list[i];
974 mwifiex_unmap_pci_memory(adapter, skb,
975 DMA_FROM_DEVICE);
976 dev_kfree_skb_any(skb);
977 }
978 card->evt_buf_list[i] = NULL;
979 memset(desc, 0, sizeof(*desc));
980 }
981
982 return;
983 }
984
985 /* This function creates buffer descriptor ring for TX
986 */
mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter * adapter)987 static int mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter *adapter)
988 {
989 struct pcie_service_card *card = adapter->card;
990 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
991
992 /*
993 * driver maintaines the write pointer and firmware maintaines the read
994 * pointer. The write pointer starts at 0 (zero) while the read pointer
995 * starts at zero with rollover bit set
996 */
997 card->txbd_wrptr = 0;
998
999 if (reg->pfu_enabled)
1000 card->txbd_rdptr = 0;
1001 else
1002 card->txbd_rdptr |= reg->tx_rollover_ind;
1003
1004 /* allocate shared memory for the BD ring and divide the same in to
1005 several descriptors */
1006 if (reg->pfu_enabled)
1007 card->txbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) *
1008 MWIFIEX_MAX_TXRX_BD;
1009 else
1010 card->txbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) *
1011 MWIFIEX_MAX_TXRX_BD;
1012
1013 mwifiex_dbg(adapter, INFO,
1014 "info: txbd_ring: Allocating %d bytes\n",
1015 card->txbd_ring_size);
1016 card->txbd_ring_vbase = dma_alloc_coherent(&card->dev->dev,
1017 card->txbd_ring_size,
1018 &card->txbd_ring_pbase,
1019 GFP_KERNEL);
1020 if (!card->txbd_ring_vbase) {
1021 mwifiex_dbg(adapter, ERROR,
1022 "allocate coherent memory (%d bytes) failed!\n",
1023 card->txbd_ring_size);
1024 return -ENOMEM;
1025 }
1026
1027 mwifiex_dbg(adapter, DATA,
1028 "info: txbd_ring - base: %p, pbase: %#x:%x, len: %#x\n",
1029 card->txbd_ring_vbase, (u32)card->txbd_ring_pbase,
1030 (u32)((u64)card->txbd_ring_pbase >> 32),
1031 card->txbd_ring_size);
1032
1033 return mwifiex_init_txq_ring(adapter);
1034 }
1035
mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter * adapter)1036 static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter)
1037 {
1038 struct pcie_service_card *card = adapter->card;
1039 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1040
1041 mwifiex_cleanup_txq_ring(adapter);
1042
1043 if (card->txbd_ring_vbase)
1044 dma_free_coherent(&card->dev->dev, card->txbd_ring_size,
1045 card->txbd_ring_vbase,
1046 card->txbd_ring_pbase);
1047 card->txbd_ring_size = 0;
1048 card->txbd_wrptr = 0;
1049 card->txbd_rdptr = 0 | reg->tx_rollover_ind;
1050 card->txbd_ring_vbase = NULL;
1051 card->txbd_ring_pbase = 0;
1052
1053 return 0;
1054 }
1055
1056 /*
1057 * This function creates buffer descriptor ring for RX
1058 */
mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter * adapter)1059 static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter)
1060 {
1061 struct pcie_service_card *card = adapter->card;
1062 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1063
1064 /*
1065 * driver maintaines the read pointer and firmware maintaines the write
1066 * pointer. The write pointer starts at 0 (zero) while the read pointer
1067 * starts at zero with rollover bit set
1068 */
1069 card->rxbd_wrptr = 0;
1070 card->rxbd_rdptr = reg->rx_rollover_ind;
1071
1072 if (reg->pfu_enabled)
1073 card->rxbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) *
1074 MWIFIEX_MAX_TXRX_BD;
1075 else
1076 card->rxbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) *
1077 MWIFIEX_MAX_TXRX_BD;
1078
1079 mwifiex_dbg(adapter, INFO,
1080 "info: rxbd_ring: Allocating %d bytes\n",
1081 card->rxbd_ring_size);
1082 card->rxbd_ring_vbase = dma_alloc_coherent(&card->dev->dev,
1083 card->rxbd_ring_size,
1084 &card->rxbd_ring_pbase,
1085 GFP_KERNEL);
1086 if (!card->rxbd_ring_vbase) {
1087 mwifiex_dbg(adapter, ERROR,
1088 "allocate coherent memory (%d bytes) failed!\n",
1089 card->rxbd_ring_size);
1090 return -ENOMEM;
1091 }
1092
1093 mwifiex_dbg(adapter, DATA,
1094 "info: rxbd_ring - base: %p, pbase: %#x:%x, len: %#x\n",
1095 card->rxbd_ring_vbase, (u32)card->rxbd_ring_pbase,
1096 (u32)((u64)card->rxbd_ring_pbase >> 32),
1097 card->rxbd_ring_size);
1098
1099 return mwifiex_init_rxq_ring(adapter);
1100 }
1101
1102 /*
1103 * This function deletes Buffer descriptor ring for RX
1104 */
mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter * adapter)1105 static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter)
1106 {
1107 struct pcie_service_card *card = adapter->card;
1108 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1109
1110 mwifiex_cleanup_rxq_ring(adapter);
1111
1112 if (card->rxbd_ring_vbase)
1113 dma_free_coherent(&card->dev->dev, card->rxbd_ring_size,
1114 card->rxbd_ring_vbase,
1115 card->rxbd_ring_pbase);
1116 card->rxbd_ring_size = 0;
1117 card->rxbd_wrptr = 0;
1118 card->rxbd_rdptr = 0 | reg->rx_rollover_ind;
1119 card->rxbd_ring_vbase = NULL;
1120 card->rxbd_ring_pbase = 0;
1121
1122 return 0;
1123 }
1124
1125 /*
1126 * This function creates buffer descriptor ring for Events
1127 */
mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter * adapter)1128 static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter)
1129 {
1130 struct pcie_service_card *card = adapter->card;
1131 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1132
1133 /*
1134 * driver maintaines the read pointer and firmware maintaines the write
1135 * pointer. The write pointer starts at 0 (zero) while the read pointer
1136 * starts at zero with rollover bit set
1137 */
1138 card->evtbd_wrptr = 0;
1139 card->evtbd_rdptr = reg->evt_rollover_ind;
1140
1141 card->evtbd_ring_size = sizeof(struct mwifiex_evt_buf_desc) *
1142 MWIFIEX_MAX_EVT_BD;
1143
1144 mwifiex_dbg(adapter, INFO,
1145 "info: evtbd_ring: Allocating %d bytes\n",
1146 card->evtbd_ring_size);
1147 card->evtbd_ring_vbase = dma_alloc_coherent(&card->dev->dev,
1148 card->evtbd_ring_size,
1149 &card->evtbd_ring_pbase,
1150 GFP_KERNEL);
1151 if (!card->evtbd_ring_vbase) {
1152 mwifiex_dbg(adapter, ERROR,
1153 "allocate coherent memory (%d bytes) failed!\n",
1154 card->evtbd_ring_size);
1155 return -ENOMEM;
1156 }
1157
1158 mwifiex_dbg(adapter, EVENT,
1159 "info: CMDRSP/EVT bd_ring - base: %p pbase: %#x:%x len: %#x\n",
1160 card->evtbd_ring_vbase, (u32)card->evtbd_ring_pbase,
1161 (u32)((u64)card->evtbd_ring_pbase >> 32),
1162 card->evtbd_ring_size);
1163
1164 return mwifiex_pcie_init_evt_ring(adapter);
1165 }
1166
1167 /*
1168 * This function deletes Buffer descriptor ring for Events
1169 */
mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter * adapter)1170 static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter)
1171 {
1172 struct pcie_service_card *card = adapter->card;
1173 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1174
1175 mwifiex_cleanup_evt_ring(adapter);
1176
1177 if (card->evtbd_ring_vbase)
1178 dma_free_coherent(&card->dev->dev, card->evtbd_ring_size,
1179 card->evtbd_ring_vbase,
1180 card->evtbd_ring_pbase);
1181 card->evtbd_wrptr = 0;
1182 card->evtbd_rdptr = 0 | reg->evt_rollover_ind;
1183 card->evtbd_ring_size = 0;
1184 card->evtbd_ring_vbase = NULL;
1185 card->evtbd_ring_pbase = 0;
1186
1187 return 0;
1188 }
1189
1190 /*
1191 * This function allocates a buffer for CMDRSP
1192 */
mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter * adapter)1193 static int mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter *adapter)
1194 {
1195 struct pcie_service_card *card = adapter->card;
1196 struct sk_buff *skb;
1197
1198 /* Allocate memory for receiving command response data */
1199 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE);
1200 if (!skb) {
1201 mwifiex_dbg(adapter, ERROR,
1202 "Unable to allocate skb for command response data.\n");
1203 return -ENOMEM;
1204 }
1205 skb_put(skb, MWIFIEX_UPLD_SIZE);
1206 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
1207 DMA_FROM_DEVICE)) {
1208 kfree_skb(skb);
1209 return -1;
1210 }
1211
1212 card->cmdrsp_buf = skb;
1213
1214 return 0;
1215 }
1216
1217 /*
1218 * This function deletes a buffer for CMDRSP
1219 */
mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter * adapter)1220 static int mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter *adapter)
1221 {
1222 struct pcie_service_card *card;
1223
1224 if (!adapter)
1225 return 0;
1226
1227 card = adapter->card;
1228
1229 if (card && card->cmdrsp_buf) {
1230 mwifiex_unmap_pci_memory(adapter, card->cmdrsp_buf,
1231 DMA_FROM_DEVICE);
1232 dev_kfree_skb_any(card->cmdrsp_buf);
1233 card->cmdrsp_buf = NULL;
1234 }
1235
1236 if (card && card->cmd_buf) {
1237 mwifiex_unmap_pci_memory(adapter, card->cmd_buf,
1238 DMA_TO_DEVICE);
1239 dev_kfree_skb_any(card->cmd_buf);
1240 card->cmd_buf = NULL;
1241 }
1242 return 0;
1243 }
1244
1245 /*
1246 * This function allocates a buffer for sleep cookie
1247 */
mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter * adapter)1248 static int mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter *adapter)
1249 {
1250 struct pcie_service_card *card = adapter->card;
1251 u32 *cookie;
1252
1253 card->sleep_cookie_vbase = dma_alloc_coherent(&card->dev->dev,
1254 sizeof(u32),
1255 &card->sleep_cookie_pbase,
1256 GFP_KERNEL);
1257 if (!card->sleep_cookie_vbase) {
1258 mwifiex_dbg(adapter, ERROR,
1259 "dma_alloc_coherent failed!\n");
1260 return -ENOMEM;
1261 }
1262 cookie = (u32 *)card->sleep_cookie_vbase;
1263 /* Init val of Sleep Cookie */
1264 *cookie = FW_AWAKE_COOKIE;
1265
1266 mwifiex_dbg(adapter, INFO, "alloc_scook: sleep cookie=0x%x\n", *cookie);
1267
1268 return 0;
1269 }
1270
1271 /*
1272 * This function deletes buffer for sleep cookie
1273 */
mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter * adapter)1274 static int mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter *adapter)
1275 {
1276 struct pcie_service_card *card;
1277
1278 if (!adapter)
1279 return 0;
1280
1281 card = adapter->card;
1282
1283 if (card && card->sleep_cookie_vbase) {
1284 dma_free_coherent(&card->dev->dev, sizeof(u32),
1285 card->sleep_cookie_vbase,
1286 card->sleep_cookie_pbase);
1287 card->sleep_cookie_vbase = NULL;
1288 }
1289
1290 return 0;
1291 }
1292
1293 /* This function flushes the TX buffer descriptor ring
1294 * This function defined as handler is also called while cleaning TXRX
1295 * during disconnect/ bss stop.
1296 */
mwifiex_clean_pcie_ring_buf(struct mwifiex_adapter * adapter)1297 static int mwifiex_clean_pcie_ring_buf(struct mwifiex_adapter *adapter)
1298 {
1299 struct pcie_service_card *card = adapter->card;
1300
1301 if (!mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) {
1302 card->txbd_flush = 1;
1303 /* write pointer already set at last send
1304 * send dnld-rdy intr again, wait for completion.
1305 */
1306 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1307 CPU_INTR_DNLD_RDY)) {
1308 mwifiex_dbg(adapter, ERROR,
1309 "failed to assert dnld-rdy interrupt.\n");
1310 return -1;
1311 }
1312 }
1313 return 0;
1314 }
1315
1316 /*
1317 * This function unmaps and frees downloaded data buffer
1318 */
mwifiex_pcie_send_data_complete(struct mwifiex_adapter * adapter)1319 static int mwifiex_pcie_send_data_complete(struct mwifiex_adapter *adapter)
1320 {
1321 struct sk_buff *skb;
1322 u32 wrdoneidx, rdptr, num_tx_buffs, unmap_count = 0;
1323 struct mwifiex_pcie_buf_desc *desc;
1324 struct mwifiex_pfu_buf_desc *desc2;
1325 struct pcie_service_card *card = adapter->card;
1326 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1327
1328 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1329 mwifiex_pm_wakeup_card(adapter);
1330
1331 /* Read the TX ring read pointer set by firmware */
1332 if (mwifiex_read_reg(adapter, reg->tx_rdptr, &rdptr)) {
1333 mwifiex_dbg(adapter, ERROR,
1334 "SEND COMP: failed to read reg->tx_rdptr\n");
1335 return -1;
1336 }
1337
1338 mwifiex_dbg(adapter, DATA,
1339 "SEND COMP: rdptr_prev=0x%x, rdptr=0x%x\n",
1340 card->txbd_rdptr, rdptr);
1341
1342 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr;
1343 /* free from previous txbd_rdptr to current txbd_rdptr */
1344 while (((card->txbd_rdptr & reg->tx_mask) !=
1345 (rdptr & reg->tx_mask)) ||
1346 ((card->txbd_rdptr & reg->tx_rollover_ind) !=
1347 (rdptr & reg->tx_rollover_ind))) {
1348 wrdoneidx = (card->txbd_rdptr & reg->tx_mask) >>
1349 reg->tx_start_ptr;
1350
1351 skb = card->tx_buf_list[wrdoneidx];
1352
1353 if (skb) {
1354 mwifiex_dbg(adapter, DATA,
1355 "SEND COMP: Detach skb %p at txbd_rdidx=%d\n",
1356 skb, wrdoneidx);
1357 mwifiex_unmap_pci_memory(adapter, skb,
1358 DMA_TO_DEVICE);
1359
1360 unmap_count++;
1361
1362 if (card->txbd_flush)
1363 mwifiex_write_data_complete(adapter, skb, 0,
1364 -1);
1365 else
1366 mwifiex_write_data_complete(adapter, skb, 0, 0);
1367 atomic_dec(&adapter->tx_hw_pending);
1368 }
1369
1370 card->tx_buf_list[wrdoneidx] = NULL;
1371
1372 if (reg->pfu_enabled) {
1373 desc2 = card->txbd_ring[wrdoneidx];
1374 memset(desc2, 0, sizeof(*desc2));
1375 } else {
1376 desc = card->txbd_ring[wrdoneidx];
1377 memset(desc, 0, sizeof(*desc));
1378 }
1379 switch (card->dev->device) {
1380 case PCIE_DEVICE_ID_MARVELL_88W8766P:
1381 card->txbd_rdptr++;
1382 break;
1383 case PCIE_DEVICE_ID_MARVELL_88W8897:
1384 case PCIE_DEVICE_ID_MARVELL_88W8997:
1385 card->txbd_rdptr += reg->ring_tx_start_ptr;
1386 break;
1387 }
1388
1389
1390 if ((card->txbd_rdptr & reg->tx_mask) == num_tx_buffs)
1391 card->txbd_rdptr = ((card->txbd_rdptr &
1392 reg->tx_rollover_ind) ^
1393 reg->tx_rollover_ind);
1394 }
1395
1396 if (unmap_count)
1397 adapter->data_sent = false;
1398
1399 if (card->txbd_flush) {
1400 if (mwifiex_pcie_txbd_empty(card, card->txbd_rdptr))
1401 card->txbd_flush = 0;
1402 else
1403 mwifiex_clean_pcie_ring_buf(adapter);
1404 }
1405
1406 return 0;
1407 }
1408
1409 /* This function sends data buffer to device. First 4 bytes of payload
1410 * are filled with payload length and payload type. Then this payload
1411 * is mapped to PCI device memory. Tx ring pointers are advanced accordingly.
1412 * Download ready interrupt to FW is deffered if Tx ring is not full and
1413 * additional payload can be accomodated.
1414 * Caller must ensure tx_param parameter to this function is not NULL.
1415 */
1416 static int
mwifiex_pcie_send_data(struct mwifiex_adapter * adapter,struct sk_buff * skb,struct mwifiex_tx_param * tx_param)1417 mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb,
1418 struct mwifiex_tx_param *tx_param)
1419 {
1420 struct pcie_service_card *card = adapter->card;
1421 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1422 u32 wrindx, num_tx_buffs, rx_val;
1423 int ret;
1424 dma_addr_t buf_pa;
1425 struct mwifiex_pcie_buf_desc *desc = NULL;
1426 struct mwifiex_pfu_buf_desc *desc2 = NULL;
1427
1428 if (!(skb->data && skb->len)) {
1429 mwifiex_dbg(adapter, ERROR,
1430 "%s(): invalid parameter <%p, %#x>\n",
1431 __func__, skb->data, skb->len);
1432 return -1;
1433 }
1434
1435 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1436 mwifiex_pm_wakeup_card(adapter);
1437
1438 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr;
1439 mwifiex_dbg(adapter, DATA,
1440 "info: SEND DATA: <Rd: %#x, Wr: %#x>\n",
1441 card->txbd_rdptr, card->txbd_wrptr);
1442 if (mwifiex_pcie_txbd_not_full(card)) {
1443 u8 *payload;
1444
1445 adapter->data_sent = true;
1446 payload = skb->data;
1447 put_unaligned_le16((u16)skb->len, payload + 0);
1448 put_unaligned_le16(MWIFIEX_TYPE_DATA, payload + 2);
1449
1450 if (mwifiex_map_pci_memory(adapter, skb, skb->len,
1451 DMA_TO_DEVICE))
1452 return -1;
1453
1454 wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr;
1455 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
1456 card->tx_buf_list[wrindx] = skb;
1457 atomic_inc(&adapter->tx_hw_pending);
1458
1459 if (reg->pfu_enabled) {
1460 desc2 = card->txbd_ring[wrindx];
1461 desc2->paddr = buf_pa;
1462 desc2->len = (u16)skb->len;
1463 desc2->frag_len = (u16)skb->len;
1464 desc2->offset = 0;
1465 desc2->flags = MWIFIEX_BD_FLAG_FIRST_DESC |
1466 MWIFIEX_BD_FLAG_LAST_DESC;
1467 } else {
1468 desc = card->txbd_ring[wrindx];
1469 desc->paddr = buf_pa;
1470 desc->len = (u16)skb->len;
1471 desc->flags = MWIFIEX_BD_FLAG_FIRST_DESC |
1472 MWIFIEX_BD_FLAG_LAST_DESC;
1473 }
1474
1475 switch (card->dev->device) {
1476 case PCIE_DEVICE_ID_MARVELL_88W8766P:
1477 card->txbd_wrptr++;
1478 break;
1479 case PCIE_DEVICE_ID_MARVELL_88W8897:
1480 case PCIE_DEVICE_ID_MARVELL_88W8997:
1481 card->txbd_wrptr += reg->ring_tx_start_ptr;
1482 break;
1483 }
1484
1485 if ((card->txbd_wrptr & reg->tx_mask) == num_tx_buffs)
1486 card->txbd_wrptr = ((card->txbd_wrptr &
1487 reg->tx_rollover_ind) ^
1488 reg->tx_rollover_ind);
1489
1490 rx_val = card->rxbd_rdptr & reg->rx_wrap_mask;
1491 /* Write the TX ring write pointer in to reg->tx_wrptr */
1492 if (mwifiex_write_reg(adapter, reg->tx_wrptr,
1493 card->txbd_wrptr | rx_val)) {
1494 mwifiex_dbg(adapter, ERROR,
1495 "SEND DATA: failed to write reg->tx_wrptr\n");
1496 ret = -1;
1497 goto done_unmap;
1498 }
1499
1500 /* The firmware (latest version 15.68.19.p21) of the 88W8897 PCIe+USB card
1501 * seems to crash randomly after setting the TX ring write pointer when
1502 * ASPM powersaving is enabled. A workaround seems to be keeping the bus
1503 * busy by reading a random register afterwards.
1504 */
1505 mwifiex_read_reg(adapter, PCI_VENDOR_ID, &rx_val);
1506
1507 if ((mwifiex_pcie_txbd_not_full(card)) &&
1508 tx_param->next_pkt_len) {
1509 /* have more packets and TxBD still can hold more */
1510 mwifiex_dbg(adapter, DATA,
1511 "SEND DATA: delay dnld-rdy interrupt.\n");
1512 adapter->data_sent = false;
1513 } else {
1514 /* Send the TX ready interrupt */
1515 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1516 CPU_INTR_DNLD_RDY)) {
1517 mwifiex_dbg(adapter, ERROR,
1518 "SEND DATA: failed to assert dnld-rdy interrupt.\n");
1519 ret = -1;
1520 goto done_unmap;
1521 }
1522 }
1523 mwifiex_dbg(adapter, DATA,
1524 "info: SEND DATA: Updated <Rd: %#x, Wr:\t"
1525 "%#x> and sent packet to firmware successfully\n",
1526 card->txbd_rdptr, card->txbd_wrptr);
1527 } else {
1528 mwifiex_dbg(adapter, DATA,
1529 "info: TX Ring full, can't send packets to fw\n");
1530 adapter->data_sent = true;
1531 /* Send the TX ready interrupt */
1532 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1533 CPU_INTR_DNLD_RDY))
1534 mwifiex_dbg(adapter, ERROR,
1535 "SEND DATA: failed to assert door-bell intr\n");
1536 return -EBUSY;
1537 }
1538
1539 return -EINPROGRESS;
1540 done_unmap:
1541 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1542 card->tx_buf_list[wrindx] = NULL;
1543 atomic_dec(&adapter->tx_hw_pending);
1544 if (reg->pfu_enabled)
1545 memset(desc2, 0, sizeof(*desc2));
1546 else
1547 memset(desc, 0, sizeof(*desc));
1548
1549 return ret;
1550 }
1551
1552 /*
1553 * This function handles received buffer ring and
1554 * dispatches packets to upper
1555 */
mwifiex_pcie_process_recv_data(struct mwifiex_adapter * adapter)1556 static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter)
1557 {
1558 struct pcie_service_card *card = adapter->card;
1559 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1560 u32 wrptr, rd_index, tx_val;
1561 dma_addr_t buf_pa;
1562 int ret = 0;
1563 struct sk_buff *skb_tmp = NULL;
1564 struct mwifiex_pcie_buf_desc *desc;
1565 struct mwifiex_pfu_buf_desc *desc2;
1566
1567 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1568 mwifiex_pm_wakeup_card(adapter);
1569
1570 /* Read the RX ring Write pointer set by firmware */
1571 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) {
1572 mwifiex_dbg(adapter, ERROR,
1573 "RECV DATA: failed to read reg->rx_wrptr\n");
1574 ret = -1;
1575 goto done;
1576 }
1577 card->rxbd_wrptr = wrptr;
1578
1579 while (((wrptr & reg->rx_mask) !=
1580 (card->rxbd_rdptr & reg->rx_mask)) ||
1581 ((wrptr & reg->rx_rollover_ind) ==
1582 (card->rxbd_rdptr & reg->rx_rollover_ind))) {
1583 struct sk_buff *skb_data;
1584 u16 rx_len;
1585
1586 rd_index = card->rxbd_rdptr & reg->rx_mask;
1587 skb_data = card->rx_buf_list[rd_index];
1588
1589 /* If skb allocation was failed earlier for Rx packet,
1590 * rx_buf_list[rd_index] would have been left with a NULL.
1591 */
1592 if (!skb_data)
1593 return -ENOMEM;
1594
1595 mwifiex_unmap_pci_memory(adapter, skb_data, DMA_FROM_DEVICE);
1596 card->rx_buf_list[rd_index] = NULL;
1597
1598 /* Get data length from interface header -
1599 * first 2 bytes for len, next 2 bytes is for type
1600 */
1601 rx_len = get_unaligned_le16(skb_data->data);
1602 if (WARN_ON(rx_len <= adapter->intf_hdr_len ||
1603 rx_len > MWIFIEX_RX_DATA_BUF_SIZE)) {
1604 mwifiex_dbg(adapter, ERROR,
1605 "Invalid RX len %d, Rd=%#x, Wr=%#x\n",
1606 rx_len, card->rxbd_rdptr, wrptr);
1607 dev_kfree_skb_any(skb_data);
1608 } else {
1609 skb_put(skb_data, rx_len);
1610 mwifiex_dbg(adapter, DATA,
1611 "info: RECV DATA: Rd=%#x, Wr=%#x, Len=%d\n",
1612 card->rxbd_rdptr, wrptr, rx_len);
1613 skb_pull(skb_data, adapter->intf_hdr_len);
1614 if (adapter->rx_work_enabled) {
1615 skb_queue_tail(&adapter->rx_data_q, skb_data);
1616 adapter->data_received = true;
1617 atomic_inc(&adapter->rx_pending);
1618 } else {
1619 mwifiex_handle_rx_packet(adapter, skb_data);
1620 }
1621 }
1622
1623 skb_tmp = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE,
1624 GFP_KERNEL);
1625 if (!skb_tmp) {
1626 mwifiex_dbg(adapter, ERROR,
1627 "Unable to allocate skb.\n");
1628 return -ENOMEM;
1629 }
1630
1631 if (mwifiex_map_pci_memory(adapter, skb_tmp,
1632 MWIFIEX_RX_DATA_BUF_SIZE,
1633 DMA_FROM_DEVICE))
1634 return -1;
1635
1636 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb_tmp);
1637
1638 mwifiex_dbg(adapter, INFO,
1639 "RECV DATA: Attach new sk_buff %p at rxbd_rdidx=%d\n",
1640 skb_tmp, rd_index);
1641 card->rx_buf_list[rd_index] = skb_tmp;
1642
1643 if (reg->pfu_enabled) {
1644 desc2 = card->rxbd_ring[rd_index];
1645 desc2->paddr = buf_pa;
1646 desc2->len = skb_tmp->len;
1647 desc2->frag_len = skb_tmp->len;
1648 desc2->offset = 0;
1649 desc2->flags = reg->ring_flag_sop | reg->ring_flag_eop;
1650 } else {
1651 desc = card->rxbd_ring[rd_index];
1652 desc->paddr = buf_pa;
1653 desc->len = skb_tmp->len;
1654 desc->flags = 0;
1655 }
1656
1657 if ((++card->rxbd_rdptr & reg->rx_mask) ==
1658 MWIFIEX_MAX_TXRX_BD) {
1659 card->rxbd_rdptr = ((card->rxbd_rdptr &
1660 reg->rx_rollover_ind) ^
1661 reg->rx_rollover_ind);
1662 }
1663 mwifiex_dbg(adapter, DATA,
1664 "info: RECV DATA: <Rd: %#x, Wr: %#x>\n",
1665 card->rxbd_rdptr, wrptr);
1666
1667 tx_val = card->txbd_wrptr & reg->tx_wrap_mask;
1668 /* Write the RX ring read pointer in to reg->rx_rdptr */
1669 if (mwifiex_write_reg(adapter, reg->rx_rdptr,
1670 card->rxbd_rdptr | tx_val)) {
1671 mwifiex_dbg(adapter, DATA,
1672 "RECV DATA: failed to write reg->rx_rdptr\n");
1673 ret = -1;
1674 goto done;
1675 }
1676
1677 /* Read the RX ring Write pointer set by firmware */
1678 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) {
1679 mwifiex_dbg(adapter, ERROR,
1680 "RECV DATA: failed to read reg->rx_wrptr\n");
1681 ret = -1;
1682 goto done;
1683 }
1684 mwifiex_dbg(adapter, DATA,
1685 "info: RECV DATA: Rcvd packet from fw successfully\n");
1686 card->rxbd_wrptr = wrptr;
1687 }
1688
1689 done:
1690 return ret;
1691 }
1692
1693 /*
1694 * This function downloads the boot command to device
1695 */
1696 static int
mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter * adapter,struct sk_buff * skb)1697 mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb)
1698 {
1699 dma_addr_t buf_pa;
1700 struct pcie_service_card *card = adapter->card;
1701 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1702
1703 if (!(skb->data && skb->len)) {
1704 mwifiex_dbg(adapter, ERROR,
1705 "Invalid parameter in %s <%p. len %d>\n",
1706 __func__, skb->data, skb->len);
1707 return -1;
1708 }
1709
1710 if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE))
1711 return -1;
1712
1713 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
1714
1715 /* Write the lower 32bits of the physical address to low command
1716 * address scratch register
1717 */
1718 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, (u32)buf_pa)) {
1719 mwifiex_dbg(adapter, ERROR,
1720 "%s: failed to write download command to boot code.\n",
1721 __func__);
1722 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1723 return -1;
1724 }
1725
1726 /* Write the upper 32bits of the physical address to high command
1727 * address scratch register
1728 */
1729 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi,
1730 (u32)((u64)buf_pa >> 32))) {
1731 mwifiex_dbg(adapter, ERROR,
1732 "%s: failed to write download command to boot code.\n",
1733 __func__);
1734 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1735 return -1;
1736 }
1737
1738 /* Write the command length to cmd_size scratch register */
1739 if (mwifiex_write_reg(adapter, reg->cmd_size, skb->len)) {
1740 mwifiex_dbg(adapter, ERROR,
1741 "%s: failed to write command len to cmd_size scratch reg\n",
1742 __func__);
1743 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1744 return -1;
1745 }
1746
1747 /* Ring the door bell */
1748 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1749 CPU_INTR_DOOR_BELL)) {
1750 mwifiex_dbg(adapter, ERROR,
1751 "%s: failed to assert door-bell intr\n", __func__);
1752 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1753 return -1;
1754 }
1755
1756 return 0;
1757 }
1758
1759 /* This function init rx port in firmware which in turn enables to receive data
1760 * from device before transmitting any packet.
1761 */
mwifiex_pcie_init_fw_port(struct mwifiex_adapter * adapter)1762 static int mwifiex_pcie_init_fw_port(struct mwifiex_adapter *adapter)
1763 {
1764 struct pcie_service_card *card = adapter->card;
1765 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1766 int tx_wrap = card->txbd_wrptr & reg->tx_wrap_mask;
1767
1768 /* Write the RX ring read pointer in to reg->rx_rdptr */
1769 if (mwifiex_write_reg(adapter, reg->rx_rdptr, card->rxbd_rdptr |
1770 tx_wrap)) {
1771 mwifiex_dbg(adapter, ERROR,
1772 "RECV DATA: failed to write reg->rx_rdptr\n");
1773 return -1;
1774 }
1775 return 0;
1776 }
1777
1778 /* This function downloads commands to the device
1779 */
1780 static int
mwifiex_pcie_send_cmd(struct mwifiex_adapter * adapter,struct sk_buff * skb)1781 mwifiex_pcie_send_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb)
1782 {
1783 struct pcie_service_card *card = adapter->card;
1784 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1785 int ret = 0;
1786 dma_addr_t cmd_buf_pa, cmdrsp_buf_pa;
1787 u8 *payload = (u8 *)skb->data;
1788
1789 if (!(skb->data && skb->len)) {
1790 mwifiex_dbg(adapter, ERROR,
1791 "Invalid parameter in %s <%p, %#x>\n",
1792 __func__, skb->data, skb->len);
1793 return -1;
1794 }
1795
1796 /* Make sure a command response buffer is available */
1797 if (!card->cmdrsp_buf) {
1798 mwifiex_dbg(adapter, ERROR,
1799 "No response buffer available, send command failed\n");
1800 return -EBUSY;
1801 }
1802
1803 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1804 mwifiex_pm_wakeup_card(adapter);
1805
1806 adapter->cmd_sent = true;
1807
1808 put_unaligned_le16((u16)skb->len, &payload[0]);
1809 put_unaligned_le16(MWIFIEX_TYPE_CMD, &payload[2]);
1810
1811 if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE))
1812 return -1;
1813
1814 card->cmd_buf = skb;
1815 /*
1816 * Need to keep a reference, since core driver might free up this
1817 * buffer before we've unmapped it.
1818 */
1819 skb_get(skb);
1820
1821 /* To send a command, the driver will:
1822 1. Write the 64bit physical address of the data buffer to
1823 cmd response address low + cmd response address high
1824 2. Ring the door bell (i.e. set the door bell interrupt)
1825
1826 In response to door bell interrupt, the firmware will perform
1827 the DMA of the command packet (first header to obtain the total
1828 length and then rest of the command).
1829 */
1830
1831 if (card->cmdrsp_buf) {
1832 cmdrsp_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmdrsp_buf);
1833 /* Write the lower 32bits of the cmdrsp buffer physical
1834 address */
1835 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo,
1836 (u32)cmdrsp_buf_pa)) {
1837 mwifiex_dbg(adapter, ERROR,
1838 "Failed to write download cmd to boot code.\n");
1839 ret = -1;
1840 goto done;
1841 }
1842 /* Write the upper 32bits of the cmdrsp buffer physical
1843 address */
1844 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi,
1845 (u32)((u64)cmdrsp_buf_pa >> 32))) {
1846 mwifiex_dbg(adapter, ERROR,
1847 "Failed to write download cmd to boot code.\n");
1848 ret = -1;
1849 goto done;
1850 }
1851 }
1852
1853 cmd_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmd_buf);
1854 /* Write the lower 32bits of the physical address to reg->cmd_addr_lo */
1855 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo,
1856 (u32)cmd_buf_pa)) {
1857 mwifiex_dbg(adapter, ERROR,
1858 "Failed to write download cmd to boot code.\n");
1859 ret = -1;
1860 goto done;
1861 }
1862 /* Write the upper 32bits of the physical address to reg->cmd_addr_hi */
1863 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi,
1864 (u32)((u64)cmd_buf_pa >> 32))) {
1865 mwifiex_dbg(adapter, ERROR,
1866 "Failed to write download cmd to boot code.\n");
1867 ret = -1;
1868 goto done;
1869 }
1870
1871 /* Write the command length to reg->cmd_size */
1872 if (mwifiex_write_reg(adapter, reg->cmd_size,
1873 card->cmd_buf->len)) {
1874 mwifiex_dbg(adapter, ERROR,
1875 "Failed to write cmd len to reg->cmd_size\n");
1876 ret = -1;
1877 goto done;
1878 }
1879
1880 /* Ring the door bell */
1881 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1882 CPU_INTR_DOOR_BELL)) {
1883 mwifiex_dbg(adapter, ERROR,
1884 "Failed to assert door-bell intr\n");
1885 ret = -1;
1886 goto done;
1887 }
1888
1889 done:
1890 if (ret)
1891 adapter->cmd_sent = false;
1892
1893 return 0;
1894 }
1895
1896 /*
1897 * This function handles command complete interrupt
1898 */
mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter * adapter)1899 static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter)
1900 {
1901 struct pcie_service_card *card = adapter->card;
1902 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1903 struct sk_buff *skb = card->cmdrsp_buf;
1904 int count = 0;
1905 u16 rx_len;
1906
1907 mwifiex_dbg(adapter, CMD,
1908 "info: Rx CMD Response\n");
1909
1910 if (adapter->curr_cmd)
1911 mwifiex_unmap_pci_memory(adapter, skb, DMA_FROM_DEVICE);
1912 else
1913 dma_sync_single_for_cpu(&card->dev->dev,
1914 MWIFIEX_SKB_DMA_ADDR(skb),
1915 MWIFIEX_UPLD_SIZE, DMA_FROM_DEVICE);
1916
1917 /* Unmap the command as a response has been received. */
1918 if (card->cmd_buf) {
1919 mwifiex_unmap_pci_memory(adapter, card->cmd_buf,
1920 DMA_TO_DEVICE);
1921 dev_kfree_skb_any(card->cmd_buf);
1922 card->cmd_buf = NULL;
1923 }
1924
1925 rx_len = get_unaligned_le16(skb->data);
1926 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len);
1927 skb_trim(skb, rx_len);
1928
1929 if (!adapter->curr_cmd) {
1930 if (adapter->ps_state == PS_STATE_SLEEP_CFM) {
1931 dma_sync_single_for_device(&card->dev->dev,
1932 MWIFIEX_SKB_DMA_ADDR(skb),
1933 MWIFIEX_SLEEP_COOKIE_SIZE,
1934 DMA_FROM_DEVICE);
1935 if (mwifiex_write_reg(adapter,
1936 PCIE_CPU_INT_EVENT,
1937 CPU_INTR_SLEEP_CFM_DONE)) {
1938 mwifiex_dbg(adapter, ERROR,
1939 "Write register failed\n");
1940 return -1;
1941 }
1942 mwifiex_delay_for_sleep_cookie(adapter,
1943 MWIFIEX_MAX_DELAY_COUNT);
1944 mwifiex_unmap_pci_memory(adapter, skb,
1945 DMA_FROM_DEVICE);
1946 skb_pull(skb, adapter->intf_hdr_len);
1947 while (reg->sleep_cookie && (count++ < 10) &&
1948 mwifiex_pcie_ok_to_access_hw(adapter))
1949 usleep_range(50, 60);
1950 mwifiex_pcie_enable_host_int(adapter);
1951 mwifiex_process_sleep_confirm_resp(adapter, skb->data,
1952 skb->len);
1953 } else {
1954 mwifiex_dbg(adapter, ERROR,
1955 "There is no command but got cmdrsp\n");
1956 }
1957 memcpy(adapter->upld_buf, skb->data,
1958 min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len));
1959 skb_push(skb, adapter->intf_hdr_len);
1960 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
1961 DMA_FROM_DEVICE))
1962 return -1;
1963 } else if (mwifiex_pcie_ok_to_access_hw(adapter)) {
1964 skb_pull(skb, adapter->intf_hdr_len);
1965 adapter->curr_cmd->resp_skb = skb;
1966 adapter->cmd_resp_received = true;
1967 /* Take the pointer and set it to CMD node and will
1968 return in the response complete callback */
1969 card->cmdrsp_buf = NULL;
1970
1971 /* Clear the cmd-rsp buffer address in scratch registers. This
1972 will prevent firmware from writing to the same response
1973 buffer again. */
1974 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 0)) {
1975 mwifiex_dbg(adapter, ERROR,
1976 "cmd_done: failed to clear cmd_rsp_addr_lo\n");
1977 return -1;
1978 }
1979 /* Write the upper 32bits of the cmdrsp buffer physical
1980 address */
1981 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 0)) {
1982 mwifiex_dbg(adapter, ERROR,
1983 "cmd_done: failed to clear cmd_rsp_addr_hi\n");
1984 return -1;
1985 }
1986 }
1987
1988 return 0;
1989 }
1990
1991 /*
1992 * Command Response processing complete handler
1993 */
mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter * adapter,struct sk_buff * skb)1994 static int mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter *adapter,
1995 struct sk_buff *skb)
1996 {
1997 struct pcie_service_card *card = adapter->card;
1998
1999 if (skb) {
2000 card->cmdrsp_buf = skb;
2001 skb_push(card->cmdrsp_buf, adapter->intf_hdr_len);
2002 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
2003 DMA_FROM_DEVICE))
2004 return -1;
2005 }
2006
2007 return 0;
2008 }
2009
2010 /*
2011 * This function handles firmware event ready interrupt
2012 */
mwifiex_pcie_process_event_ready(struct mwifiex_adapter * adapter)2013 static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter)
2014 {
2015 struct pcie_service_card *card = adapter->card;
2016 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2017 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK;
2018 u32 wrptr, event;
2019 struct mwifiex_evt_buf_desc *desc;
2020
2021 if (!mwifiex_pcie_ok_to_access_hw(adapter))
2022 mwifiex_pm_wakeup_card(adapter);
2023
2024 if (adapter->event_received) {
2025 mwifiex_dbg(adapter, EVENT,
2026 "info: Event being processed,\t"
2027 "do not process this interrupt just yet\n");
2028 return 0;
2029 }
2030
2031 if (rdptr >= MWIFIEX_MAX_EVT_BD) {
2032 mwifiex_dbg(adapter, ERROR,
2033 "info: Invalid read pointer...\n");
2034 return -1;
2035 }
2036
2037 /* Read the event ring write pointer set by firmware */
2038 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) {
2039 mwifiex_dbg(adapter, ERROR,
2040 "EventReady: failed to read reg->evt_wrptr\n");
2041 return -1;
2042 }
2043
2044 mwifiex_dbg(adapter, EVENT,
2045 "info: EventReady: Initial <Rd: 0x%x, Wr: 0x%x>",
2046 card->evtbd_rdptr, wrptr);
2047 if (((wrptr & MWIFIEX_EVTBD_MASK) != (card->evtbd_rdptr
2048 & MWIFIEX_EVTBD_MASK)) ||
2049 ((wrptr & reg->evt_rollover_ind) ==
2050 (card->evtbd_rdptr & reg->evt_rollover_ind))) {
2051 struct sk_buff *skb_cmd;
2052 __le16 data_len = 0;
2053 u16 evt_len;
2054
2055 mwifiex_dbg(adapter, INFO,
2056 "info: Read Index: %d\n", rdptr);
2057 skb_cmd = card->evt_buf_list[rdptr];
2058 mwifiex_unmap_pci_memory(adapter, skb_cmd, DMA_FROM_DEVICE);
2059
2060 /* Take the pointer and set it to event pointer in adapter
2061 and will return back after event handling callback */
2062 card->evt_buf_list[rdptr] = NULL;
2063 desc = card->evtbd_ring[rdptr];
2064 memset(desc, 0, sizeof(*desc));
2065
2066 event = get_unaligned_le32(
2067 &skb_cmd->data[adapter->intf_hdr_len]);
2068 adapter->event_cause = event;
2069 /* The first 4bytes will be the event transfer header
2070 len is 2 bytes followed by type which is 2 bytes */
2071 memcpy(&data_len, skb_cmd->data, sizeof(__le16));
2072 evt_len = le16_to_cpu(data_len);
2073 skb_trim(skb_cmd, evt_len);
2074 skb_pull(skb_cmd, adapter->intf_hdr_len);
2075 mwifiex_dbg(adapter, EVENT,
2076 "info: Event length: %d\n", evt_len);
2077
2078 if (evt_len > MWIFIEX_EVENT_HEADER_LEN &&
2079 evt_len < MAX_EVENT_SIZE)
2080 memcpy(adapter->event_body, skb_cmd->data +
2081 MWIFIEX_EVENT_HEADER_LEN, evt_len -
2082 MWIFIEX_EVENT_HEADER_LEN);
2083
2084 adapter->event_received = true;
2085 adapter->event_skb = skb_cmd;
2086
2087 /* Do not update the event read pointer here, wait till the
2088 buffer is released. This is just to make things simpler,
2089 we need to find a better method of managing these buffers.
2090 */
2091 } else {
2092 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
2093 CPU_INTR_EVENT_DONE)) {
2094 mwifiex_dbg(adapter, ERROR,
2095 "Write register failed\n");
2096 return -1;
2097 }
2098 }
2099
2100 return 0;
2101 }
2102
2103 /*
2104 * Event processing complete handler
2105 */
mwifiex_pcie_event_complete(struct mwifiex_adapter * adapter,struct sk_buff * skb)2106 static int mwifiex_pcie_event_complete(struct mwifiex_adapter *adapter,
2107 struct sk_buff *skb)
2108 {
2109 struct pcie_service_card *card = adapter->card;
2110 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2111 int ret = 0;
2112 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK;
2113 u32 wrptr;
2114 struct mwifiex_evt_buf_desc *desc;
2115
2116 if (!skb)
2117 return 0;
2118
2119 if (rdptr >= MWIFIEX_MAX_EVT_BD) {
2120 mwifiex_dbg(adapter, ERROR,
2121 "event_complete: Invalid rdptr 0x%x\n",
2122 rdptr);
2123 return -EINVAL;
2124 }
2125
2126 /* Read the event ring write pointer set by firmware */
2127 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) {
2128 mwifiex_dbg(adapter, ERROR,
2129 "event_complete: failed to read reg->evt_wrptr\n");
2130 return -1;
2131 }
2132
2133 if (!card->evt_buf_list[rdptr]) {
2134 skb_push(skb, adapter->intf_hdr_len);
2135 skb_put(skb, MAX_EVENT_SIZE - skb->len);
2136 if (mwifiex_map_pci_memory(adapter, skb,
2137 MAX_EVENT_SIZE,
2138 DMA_FROM_DEVICE))
2139 return -1;
2140 card->evt_buf_list[rdptr] = skb;
2141 desc = card->evtbd_ring[rdptr];
2142 desc->paddr = MWIFIEX_SKB_DMA_ADDR(skb);
2143 desc->len = (u16)skb->len;
2144 desc->flags = 0;
2145 skb = NULL;
2146 } else {
2147 mwifiex_dbg(adapter, ERROR,
2148 "info: ERROR: buf still valid at index %d, <%p, %p>\n",
2149 rdptr, card->evt_buf_list[rdptr], skb);
2150 }
2151
2152 if ((++card->evtbd_rdptr & MWIFIEX_EVTBD_MASK) == MWIFIEX_MAX_EVT_BD) {
2153 card->evtbd_rdptr = ((card->evtbd_rdptr &
2154 reg->evt_rollover_ind) ^
2155 reg->evt_rollover_ind);
2156 }
2157
2158 mwifiex_dbg(adapter, EVENT,
2159 "info: Updated <Rd: 0x%x, Wr: 0x%x>",
2160 card->evtbd_rdptr, wrptr);
2161
2162 /* Write the event ring read pointer in to reg->evt_rdptr */
2163 if (mwifiex_write_reg(adapter, reg->evt_rdptr,
2164 card->evtbd_rdptr)) {
2165 mwifiex_dbg(adapter, ERROR,
2166 "event_complete: failed to read reg->evt_rdptr\n");
2167 return -1;
2168 }
2169
2170 mwifiex_dbg(adapter, EVENT,
2171 "info: Check Events Again\n");
2172 ret = mwifiex_pcie_process_event_ready(adapter);
2173
2174 return ret;
2175 }
2176
2177 /* Combo firmware image is a combination of
2178 * (1) combo crc heaer, start with CMD5
2179 * (2) bluetooth image, start with CMD7, end with CMD6, data wrapped in CMD1.
2180 * (3) wifi image.
2181 *
2182 * This function bypass the header and bluetooth part, return
2183 * the offset of tail wifi-only part. If the image is already wifi-only,
2184 * that is start with CMD1, return 0.
2185 */
2186
mwifiex_extract_wifi_fw(struct mwifiex_adapter * adapter,const void * firmware,u32 firmware_len)2187 static int mwifiex_extract_wifi_fw(struct mwifiex_adapter *adapter,
2188 const void *firmware, u32 firmware_len) {
2189 const struct mwifiex_fw_data *fwdata;
2190 u32 offset = 0, data_len, dnld_cmd;
2191 int ret = 0;
2192 bool cmd7_before = false, first_cmd = false;
2193
2194 while (1) {
2195 /* Check for integer and buffer overflow */
2196 if (offset + sizeof(fwdata->header) < sizeof(fwdata->header) ||
2197 offset + sizeof(fwdata->header) >= firmware_len) {
2198 mwifiex_dbg(adapter, ERROR,
2199 "extract wifi-only fw failure!\n");
2200 ret = -1;
2201 goto done;
2202 }
2203
2204 fwdata = firmware + offset;
2205 dnld_cmd = le32_to_cpu(fwdata->header.dnld_cmd);
2206 data_len = le32_to_cpu(fwdata->header.data_length);
2207
2208 /* Skip past header */
2209 offset += sizeof(fwdata->header);
2210
2211 switch (dnld_cmd) {
2212 case MWIFIEX_FW_DNLD_CMD_1:
2213 if (offset + data_len < data_len) {
2214 mwifiex_dbg(adapter, ERROR, "bad FW parse\n");
2215 ret = -1;
2216 goto done;
2217 }
2218
2219 /* Image start with cmd1, already wifi-only firmware */
2220 if (!first_cmd) {
2221 mwifiex_dbg(adapter, MSG,
2222 "input wifi-only firmware\n");
2223 return 0;
2224 }
2225
2226 if (!cmd7_before) {
2227 mwifiex_dbg(adapter, ERROR,
2228 "no cmd7 before cmd1!\n");
2229 ret = -1;
2230 goto done;
2231 }
2232 offset += data_len;
2233 break;
2234 case MWIFIEX_FW_DNLD_CMD_5:
2235 first_cmd = true;
2236 /* Check for integer overflow */
2237 if (offset + data_len < data_len) {
2238 mwifiex_dbg(adapter, ERROR, "bad FW parse\n");
2239 ret = -1;
2240 goto done;
2241 }
2242 offset += data_len;
2243 break;
2244 case MWIFIEX_FW_DNLD_CMD_6:
2245 first_cmd = true;
2246 /* Check for integer overflow */
2247 if (offset + data_len < data_len) {
2248 mwifiex_dbg(adapter, ERROR, "bad FW parse\n");
2249 ret = -1;
2250 goto done;
2251 }
2252 offset += data_len;
2253 if (offset >= firmware_len) {
2254 mwifiex_dbg(adapter, ERROR,
2255 "extract wifi-only fw failure!\n");
2256 ret = -1;
2257 } else {
2258 ret = offset;
2259 }
2260 goto done;
2261 case MWIFIEX_FW_DNLD_CMD_7:
2262 first_cmd = true;
2263 cmd7_before = true;
2264 break;
2265 default:
2266 mwifiex_dbg(adapter, ERROR, "unknown dnld_cmd %d\n",
2267 dnld_cmd);
2268 ret = -1;
2269 goto done;
2270 }
2271 }
2272
2273 done:
2274 return ret;
2275 }
2276
2277 /*
2278 * This function downloads the firmware to the card.
2279 *
2280 * Firmware is downloaded to the card in blocks. Every block download
2281 * is tested for CRC errors, and retried a number of times before
2282 * returning failure.
2283 */
mwifiex_prog_fw_w_helper(struct mwifiex_adapter * adapter,struct mwifiex_fw_image * fw)2284 static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter,
2285 struct mwifiex_fw_image *fw)
2286 {
2287 int ret;
2288 u8 *firmware = fw->fw_buf;
2289 u32 firmware_len = fw->fw_len;
2290 u32 offset = 0;
2291 struct sk_buff *skb;
2292 u32 txlen, tx_blocks = 0, tries, len, val;
2293 u32 block_retry_cnt = 0;
2294 struct pcie_service_card *card = adapter->card;
2295 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2296
2297 if (!firmware || !firmware_len) {
2298 mwifiex_dbg(adapter, ERROR,
2299 "No firmware image found! Terminating download\n");
2300 return -1;
2301 }
2302
2303 mwifiex_dbg(adapter, INFO,
2304 "info: Downloading FW image (%d bytes)\n",
2305 firmware_len);
2306
2307 if (mwifiex_pcie_disable_host_int(adapter)) {
2308 mwifiex_dbg(adapter, ERROR,
2309 "%s: Disabling interrupts failed.\n", __func__);
2310 return -1;
2311 }
2312
2313 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE);
2314 if (!skb) {
2315 ret = -ENOMEM;
2316 goto done;
2317 }
2318
2319 ret = mwifiex_read_reg(adapter, PCIE_SCRATCH_13_REG, &val);
2320 if (ret) {
2321 mwifiex_dbg(adapter, FATAL, "Failed to read scratch register 13\n");
2322 goto done;
2323 }
2324
2325 /* PCIE FLR case: extract wifi part from combo firmware*/
2326 if (val == MWIFIEX_PCIE_FLR_HAPPENS) {
2327 ret = mwifiex_extract_wifi_fw(adapter, firmware, firmware_len);
2328 if (ret < 0) {
2329 mwifiex_dbg(adapter, ERROR, "Failed to extract wifi fw\n");
2330 goto done;
2331 }
2332 offset = ret;
2333 mwifiex_dbg(adapter, MSG,
2334 "info: dnld wifi firmware from %d bytes\n", offset);
2335 }
2336
2337 /* Perform firmware data transfer */
2338 do {
2339 u32 ireg_intr = 0;
2340
2341 /* More data? */
2342 if (offset >= firmware_len)
2343 break;
2344
2345 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
2346 ret = mwifiex_read_reg(adapter, reg->cmd_size,
2347 &len);
2348 if (ret) {
2349 mwifiex_dbg(adapter, FATAL,
2350 "Failed reading len from boot code\n");
2351 goto done;
2352 }
2353 if (len)
2354 break;
2355 usleep_range(10, 20);
2356 }
2357
2358 if (!len) {
2359 break;
2360 } else if (len > MWIFIEX_UPLD_SIZE) {
2361 mwifiex_dbg(adapter, ERROR,
2362 "FW download failure @ %d, invalid length %d\n",
2363 offset, len);
2364 ret = -1;
2365 goto done;
2366 }
2367
2368 txlen = len;
2369
2370 if (len & BIT(0)) {
2371 block_retry_cnt++;
2372 if (block_retry_cnt > MAX_WRITE_IOMEM_RETRY) {
2373 mwifiex_dbg(adapter, ERROR,
2374 "FW download failure @ %d, over max\t"
2375 "retry count\n", offset);
2376 ret = -1;
2377 goto done;
2378 }
2379 mwifiex_dbg(adapter, ERROR,
2380 "FW CRC error indicated by the\t"
2381 "helper: len = 0x%04X, txlen = %d\n",
2382 len, txlen);
2383 len &= ~BIT(0);
2384 /* Setting this to 0 to resend from same offset */
2385 txlen = 0;
2386 } else {
2387 block_retry_cnt = 0;
2388 /* Set blocksize to transfer - checking for
2389 last block */
2390 if (firmware_len - offset < txlen)
2391 txlen = firmware_len - offset;
2392
2393 tx_blocks = (txlen + card->pcie.blksz_fw_dl - 1) /
2394 card->pcie.blksz_fw_dl;
2395
2396 /* Copy payload to buffer */
2397 memmove(skb->data, &firmware[offset], txlen);
2398 }
2399
2400 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len);
2401 skb_trim(skb, tx_blocks * card->pcie.blksz_fw_dl);
2402
2403 /* Send the boot command to device */
2404 if (mwifiex_pcie_send_boot_cmd(adapter, skb)) {
2405 mwifiex_dbg(adapter, ERROR,
2406 "Failed to send firmware download command\n");
2407 ret = -1;
2408 goto done;
2409 }
2410
2411 /* Wait for the command done interrupt */
2412 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
2413 if (mwifiex_read_reg(adapter, PCIE_CPU_INT_STATUS,
2414 &ireg_intr)) {
2415 mwifiex_dbg(adapter, ERROR,
2416 "%s: Failed to read\t"
2417 "interrupt status during fw dnld.\n",
2418 __func__);
2419 mwifiex_unmap_pci_memory(adapter, skb,
2420 DMA_TO_DEVICE);
2421 ret = -1;
2422 goto done;
2423 }
2424 if (!(ireg_intr & CPU_INTR_DOOR_BELL))
2425 break;
2426 usleep_range(10, 20);
2427 }
2428 if (ireg_intr & CPU_INTR_DOOR_BELL) {
2429 mwifiex_dbg(adapter, ERROR, "%s: Card failed to ACK download\n",
2430 __func__);
2431 mwifiex_unmap_pci_memory(adapter, skb,
2432 DMA_TO_DEVICE);
2433 ret = -1;
2434 goto done;
2435 }
2436
2437 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
2438
2439 offset += txlen;
2440 } while (true);
2441
2442 mwifiex_dbg(adapter, MSG,
2443 "info: FW download over, size %d bytes\n", offset);
2444
2445 ret = 0;
2446
2447 done:
2448 dev_kfree_skb_any(skb);
2449 return ret;
2450 }
2451
2452 /*
2453 * This function checks the firmware status in card.
2454 */
2455 static int
mwifiex_check_fw_status(struct mwifiex_adapter * adapter,u32 poll_num)2456 mwifiex_check_fw_status(struct mwifiex_adapter *adapter, u32 poll_num)
2457 {
2458 int ret = 0;
2459 u32 firmware_stat;
2460 struct pcie_service_card *card = adapter->card;
2461 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2462 u32 tries;
2463
2464 /* Mask spurios interrupts */
2465 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS_MASK,
2466 HOST_INTR_MASK)) {
2467 mwifiex_dbg(adapter, ERROR,
2468 "Write register failed\n");
2469 return -1;
2470 }
2471
2472 mwifiex_dbg(adapter, INFO,
2473 "Setting driver ready signature\n");
2474 if (mwifiex_write_reg(adapter, reg->drv_rdy,
2475 FIRMWARE_READY_PCIE)) {
2476 mwifiex_dbg(adapter, ERROR,
2477 "Failed to write driver ready signature\n");
2478 return -1;
2479 }
2480
2481 /* Wait for firmware initialization event */
2482 for (tries = 0; tries < poll_num; tries++) {
2483 if (mwifiex_read_reg(adapter, reg->fw_status,
2484 &firmware_stat))
2485 ret = -1;
2486 else
2487 ret = 0;
2488
2489 mwifiex_dbg(adapter, INFO, "Try %d if FW is ready <%d,%#x>",
2490 tries, ret, firmware_stat);
2491
2492 if (ret)
2493 continue;
2494 if (firmware_stat == FIRMWARE_READY_PCIE) {
2495 ret = 0;
2496 break;
2497 } else {
2498 msleep(100);
2499 ret = -1;
2500 }
2501 }
2502
2503 return ret;
2504 }
2505
2506 /* This function checks if WLAN is the winner.
2507 */
2508 static int
mwifiex_check_winner_status(struct mwifiex_adapter * adapter)2509 mwifiex_check_winner_status(struct mwifiex_adapter *adapter)
2510 {
2511 u32 winner = 0;
2512 int ret = 0;
2513 struct pcie_service_card *card = adapter->card;
2514 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2515
2516 if (mwifiex_read_reg(adapter, reg->fw_status, &winner)) {
2517 ret = -1;
2518 } else if (!winner) {
2519 mwifiex_dbg(adapter, INFO, "PCI-E is the winner\n");
2520 adapter->winner = 1;
2521 } else {
2522 mwifiex_dbg(adapter, ERROR,
2523 "PCI-E is not the winner <%#x>", winner);
2524 }
2525
2526 return ret;
2527 }
2528
2529 /*
2530 * This function reads the interrupt status from card.
2531 */
mwifiex_interrupt_status(struct mwifiex_adapter * adapter,int msg_id)2532 static void mwifiex_interrupt_status(struct mwifiex_adapter *adapter,
2533 int msg_id)
2534 {
2535 u32 pcie_ireg;
2536 unsigned long flags;
2537 struct pcie_service_card *card = adapter->card;
2538
2539 if (card->msi_enable) {
2540 spin_lock_irqsave(&adapter->int_lock, flags);
2541 adapter->int_status = 1;
2542 spin_unlock_irqrestore(&adapter->int_lock, flags);
2543 return;
2544 }
2545
2546 if (!mwifiex_pcie_ok_to_access_hw(adapter))
2547 return;
2548
2549 if (card->msix_enable && msg_id >= 0) {
2550 pcie_ireg = BIT(msg_id);
2551 } else {
2552 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS,
2553 &pcie_ireg)) {
2554 mwifiex_dbg(adapter, ERROR, "Read register failed\n");
2555 return;
2556 }
2557
2558 if ((pcie_ireg == 0xFFFFFFFF) || !pcie_ireg)
2559 return;
2560
2561
2562 mwifiex_pcie_disable_host_int(adapter);
2563
2564 /* Clear the pending interrupts */
2565 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS,
2566 ~pcie_ireg)) {
2567 mwifiex_dbg(adapter, ERROR,
2568 "Write register failed\n");
2569 return;
2570 }
2571 }
2572
2573 if (!adapter->pps_uapsd_mode &&
2574 adapter->ps_state == PS_STATE_SLEEP &&
2575 mwifiex_pcie_ok_to_access_hw(adapter)) {
2576 /* Potentially for PCIe we could get other
2577 * interrupts like shared. Don't change power
2578 * state until cookie is set
2579 */
2580 adapter->ps_state = PS_STATE_AWAKE;
2581 adapter->pm_wakeup_fw_try = false;
2582 del_timer(&adapter->wakeup_timer);
2583 }
2584
2585 spin_lock_irqsave(&adapter->int_lock, flags);
2586 adapter->int_status |= pcie_ireg;
2587 spin_unlock_irqrestore(&adapter->int_lock, flags);
2588 mwifiex_dbg(adapter, INTR, "ireg: 0x%08x\n", pcie_ireg);
2589 }
2590
2591 /*
2592 * Interrupt handler for PCIe root port
2593 *
2594 * This function reads the interrupt status from firmware and assigns
2595 * the main process in workqueue which will handle the interrupt.
2596 */
mwifiex_pcie_interrupt(int irq,void * context)2597 static irqreturn_t mwifiex_pcie_interrupt(int irq, void *context)
2598 {
2599 struct mwifiex_msix_context *ctx = context;
2600 struct pci_dev *pdev = ctx->dev;
2601 struct pcie_service_card *card;
2602 struct mwifiex_adapter *adapter;
2603
2604 card = pci_get_drvdata(pdev);
2605
2606 if (!card->adapter) {
2607 pr_err("info: %s: card=%p adapter=%p\n", __func__, card,
2608 card ? card->adapter : NULL);
2609 goto exit;
2610 }
2611 adapter = card->adapter;
2612
2613 if (test_bit(MWIFIEX_SURPRISE_REMOVED, &adapter->work_flags))
2614 goto exit;
2615
2616 if (card->msix_enable)
2617 mwifiex_interrupt_status(adapter, ctx->msg_id);
2618 else
2619 mwifiex_interrupt_status(adapter, -1);
2620
2621 mwifiex_queue_main_work(adapter);
2622
2623 exit:
2624 return IRQ_HANDLED;
2625 }
2626
2627 /*
2628 * This function checks the current interrupt status.
2629 *
2630 * The following interrupts are checked and handled by this function -
2631 * - Data sent
2632 * - Command sent
2633 * - Command received
2634 * - Packets received
2635 * - Events received
2636 *
2637 * In case of Rx packets received, the packets are uploaded from card to
2638 * host and processed accordingly.
2639 */
mwifiex_process_int_status(struct mwifiex_adapter * adapter)2640 static int mwifiex_process_int_status(struct mwifiex_adapter *adapter)
2641 {
2642 int ret;
2643 u32 pcie_ireg = 0;
2644 unsigned long flags;
2645 struct pcie_service_card *card = adapter->card;
2646
2647 spin_lock_irqsave(&adapter->int_lock, flags);
2648 if (!card->msi_enable) {
2649 /* Clear out unused interrupts */
2650 pcie_ireg = adapter->int_status;
2651 }
2652 adapter->int_status = 0;
2653 spin_unlock_irqrestore(&adapter->int_lock, flags);
2654
2655 if (card->msi_enable) {
2656 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
2657 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS,
2658 &pcie_ireg)) {
2659 mwifiex_dbg(adapter, ERROR,
2660 "Read register failed\n");
2661 return -1;
2662 }
2663
2664 if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) {
2665 if (mwifiex_write_reg(adapter,
2666 PCIE_HOST_INT_STATUS,
2667 ~pcie_ireg)) {
2668 mwifiex_dbg(adapter, ERROR,
2669 "Write register failed\n");
2670 return -1;
2671 }
2672 if (!adapter->pps_uapsd_mode &&
2673 adapter->ps_state == PS_STATE_SLEEP) {
2674 adapter->ps_state = PS_STATE_AWAKE;
2675 adapter->pm_wakeup_fw_try = false;
2676 del_timer(&adapter->wakeup_timer);
2677 }
2678 }
2679 }
2680 }
2681
2682 if (pcie_ireg & HOST_INTR_DNLD_DONE) {
2683 mwifiex_dbg(adapter, INTR, "info: TX DNLD Done\n");
2684 ret = mwifiex_pcie_send_data_complete(adapter);
2685 if (ret)
2686 return ret;
2687 }
2688 if (pcie_ireg & HOST_INTR_UPLD_RDY) {
2689 mwifiex_dbg(adapter, INTR, "info: Rx DATA\n");
2690 ret = mwifiex_pcie_process_recv_data(adapter);
2691 if (ret)
2692 return ret;
2693 }
2694 if (pcie_ireg & HOST_INTR_EVENT_RDY) {
2695 mwifiex_dbg(adapter, INTR, "info: Rx EVENT\n");
2696 ret = mwifiex_pcie_process_event_ready(adapter);
2697 if (ret)
2698 return ret;
2699 }
2700 if (pcie_ireg & HOST_INTR_CMD_DONE) {
2701 if (adapter->cmd_sent) {
2702 mwifiex_dbg(adapter, INTR,
2703 "info: CMD sent Interrupt\n");
2704 adapter->cmd_sent = false;
2705 }
2706 /* Handle command response */
2707 ret = mwifiex_pcie_process_cmd_complete(adapter);
2708 if (ret)
2709 return ret;
2710 }
2711
2712 mwifiex_dbg(adapter, INTR,
2713 "info: cmd_sent=%d data_sent=%d\n",
2714 adapter->cmd_sent, adapter->data_sent);
2715 if (!card->msi_enable && !card->msix_enable &&
2716 adapter->ps_state != PS_STATE_SLEEP)
2717 mwifiex_pcie_enable_host_int(adapter);
2718
2719 return 0;
2720 }
2721
2722 /*
2723 * This function downloads data from driver to card.
2724 *
2725 * Both commands and data packets are transferred to the card by this
2726 * function.
2727 *
2728 * This function adds the PCIE specific header to the front of the buffer
2729 * before transferring. The header contains the length of the packet and
2730 * the type. The firmware handles the packets based upon this set type.
2731 */
mwifiex_pcie_host_to_card(struct mwifiex_adapter * adapter,u8 type,struct sk_buff * skb,struct mwifiex_tx_param * tx_param)2732 static int mwifiex_pcie_host_to_card(struct mwifiex_adapter *adapter, u8 type,
2733 struct sk_buff *skb,
2734 struct mwifiex_tx_param *tx_param)
2735 {
2736 if (!skb) {
2737 mwifiex_dbg(adapter, ERROR,
2738 "Passed NULL skb to %s\n", __func__);
2739 return -1;
2740 }
2741
2742 if (type == MWIFIEX_TYPE_DATA)
2743 return mwifiex_pcie_send_data(adapter, skb, tx_param);
2744 else if (type == MWIFIEX_TYPE_CMD)
2745 return mwifiex_pcie_send_cmd(adapter, skb);
2746
2747 return 0;
2748 }
2749
2750 /* Function to dump PCIE scratch registers in case of FW crash
2751 */
2752 static int
mwifiex_pcie_reg_dump(struct mwifiex_adapter * adapter,char * drv_buf)2753 mwifiex_pcie_reg_dump(struct mwifiex_adapter *adapter, char *drv_buf)
2754 {
2755 char *p = drv_buf;
2756 char buf[256], *ptr;
2757 int i;
2758 u32 value;
2759 struct pcie_service_card *card = adapter->card;
2760 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2761 int pcie_scratch_reg[] = {PCIE_SCRATCH_12_REG,
2762 PCIE_SCRATCH_14_REG,
2763 PCIE_SCRATCH_15_REG};
2764
2765 if (!p)
2766 return 0;
2767
2768 mwifiex_dbg(adapter, MSG, "PCIE register dump start\n");
2769
2770 if (mwifiex_read_reg(adapter, reg->fw_status, &value)) {
2771 mwifiex_dbg(adapter, ERROR, "failed to read firmware status");
2772 return 0;
2773 }
2774
2775 ptr = buf;
2776 mwifiex_dbg(adapter, MSG, "pcie scratch register:");
2777 for (i = 0; i < ARRAY_SIZE(pcie_scratch_reg); i++) {
2778 mwifiex_read_reg(adapter, pcie_scratch_reg[i], &value);
2779 ptr += sprintf(ptr, "reg:0x%x, value=0x%x\n",
2780 pcie_scratch_reg[i], value);
2781 }
2782
2783 mwifiex_dbg(adapter, MSG, "%s\n", buf);
2784 p += sprintf(p, "%s\n", buf);
2785
2786 mwifiex_dbg(adapter, MSG, "PCIE register dump end\n");
2787
2788 return p - drv_buf;
2789 }
2790
2791 /* This function read/write firmware */
2792 static enum rdwr_status
mwifiex_pcie_rdwr_firmware(struct mwifiex_adapter * adapter,u8 doneflag)2793 mwifiex_pcie_rdwr_firmware(struct mwifiex_adapter *adapter, u8 doneflag)
2794 {
2795 int ret, tries;
2796 u8 ctrl_data;
2797 u32 fw_status;
2798 struct pcie_service_card *card = adapter->card;
2799 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2800
2801 if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status))
2802 return RDWR_STATUS_FAILURE;
2803
2804 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl,
2805 reg->fw_dump_host_ready);
2806 if (ret) {
2807 mwifiex_dbg(adapter, ERROR,
2808 "PCIE write err\n");
2809 return RDWR_STATUS_FAILURE;
2810 }
2811
2812 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
2813 mwifiex_read_reg_byte(adapter, reg->fw_dump_ctrl, &ctrl_data);
2814 if (ctrl_data == FW_DUMP_DONE)
2815 return RDWR_STATUS_SUCCESS;
2816 if (doneflag && ctrl_data == doneflag)
2817 return RDWR_STATUS_DONE;
2818 if (ctrl_data != reg->fw_dump_host_ready) {
2819 mwifiex_dbg(adapter, WARN,
2820 "The ctrl reg was changed, re-try again!\n");
2821 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl,
2822 reg->fw_dump_host_ready);
2823 if (ret) {
2824 mwifiex_dbg(adapter, ERROR,
2825 "PCIE write err\n");
2826 return RDWR_STATUS_FAILURE;
2827 }
2828 }
2829 usleep_range(100, 200);
2830 }
2831
2832 mwifiex_dbg(adapter, ERROR, "Fail to pull ctrl_data\n");
2833 return RDWR_STATUS_FAILURE;
2834 }
2835
2836 /* This function dump firmware memory to file */
mwifiex_pcie_fw_dump(struct mwifiex_adapter * adapter)2837 static void mwifiex_pcie_fw_dump(struct mwifiex_adapter *adapter)
2838 {
2839 struct pcie_service_card *card = adapter->card;
2840 const struct mwifiex_pcie_card_reg *creg = card->pcie.reg;
2841 unsigned int reg, reg_start, reg_end;
2842 u8 *dbg_ptr, *end_ptr, *tmp_ptr, fw_dump_num, dump_num;
2843 u8 idx, i, read_reg, doneflag = 0;
2844 enum rdwr_status stat;
2845 u32 memory_size;
2846 int ret;
2847
2848 if (!card->pcie.can_dump_fw)
2849 return;
2850
2851 for (idx = 0; idx < adapter->num_mem_types; idx++) {
2852 struct memory_type_mapping *entry =
2853 &adapter->mem_type_mapping_tbl[idx];
2854
2855 if (entry->mem_ptr) {
2856 vfree(entry->mem_ptr);
2857 entry->mem_ptr = NULL;
2858 }
2859 entry->mem_size = 0;
2860 }
2861
2862 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump start ==\n");
2863
2864 /* Read the number of the memories which will dump */
2865 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2866 if (stat == RDWR_STATUS_FAILURE)
2867 return;
2868
2869 reg = creg->fw_dump_start;
2870 mwifiex_read_reg_byte(adapter, reg, &fw_dump_num);
2871
2872 /* W8997 chipset firmware dump will be restore in single region*/
2873 if (fw_dump_num == 0)
2874 dump_num = 1;
2875 else
2876 dump_num = fw_dump_num;
2877
2878 /* Read the length of every memory which will dump */
2879 for (idx = 0; idx < dump_num; idx++) {
2880 struct memory_type_mapping *entry =
2881 &adapter->mem_type_mapping_tbl[idx];
2882 memory_size = 0;
2883 if (fw_dump_num != 0) {
2884 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2885 if (stat == RDWR_STATUS_FAILURE)
2886 return;
2887
2888 reg = creg->fw_dump_start;
2889 for (i = 0; i < 4; i++) {
2890 mwifiex_read_reg_byte(adapter, reg, &read_reg);
2891 memory_size |= (read_reg << (i * 8));
2892 reg++;
2893 }
2894 } else {
2895 memory_size = MWIFIEX_FW_DUMP_MAX_MEMSIZE;
2896 }
2897
2898 if (memory_size == 0) {
2899 mwifiex_dbg(adapter, MSG, "Firmware dump Finished!\n");
2900 ret = mwifiex_write_reg(adapter, creg->fw_dump_ctrl,
2901 creg->fw_dump_read_done);
2902 if (ret) {
2903 mwifiex_dbg(adapter, ERROR, "PCIE write err\n");
2904 return;
2905 }
2906 break;
2907 }
2908
2909 mwifiex_dbg(adapter, DUMP,
2910 "%s_SIZE=0x%x\n", entry->mem_name, memory_size);
2911 entry->mem_ptr = vmalloc(memory_size + 1);
2912 entry->mem_size = memory_size;
2913 if (!entry->mem_ptr) {
2914 mwifiex_dbg(adapter, ERROR,
2915 "Vmalloc %s failed\n", entry->mem_name);
2916 return;
2917 }
2918 dbg_ptr = entry->mem_ptr;
2919 end_ptr = dbg_ptr + memory_size;
2920
2921 doneflag = entry->done_flag;
2922 mwifiex_dbg(adapter, DUMP, "Start %s output, please wait...\n",
2923 entry->mem_name);
2924
2925 do {
2926 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2927 if (RDWR_STATUS_FAILURE == stat)
2928 return;
2929
2930 reg_start = creg->fw_dump_start;
2931 reg_end = creg->fw_dump_end;
2932 for (reg = reg_start; reg <= reg_end; reg++) {
2933 mwifiex_read_reg_byte(adapter, reg, dbg_ptr);
2934 if (dbg_ptr < end_ptr) {
2935 dbg_ptr++;
2936 continue;
2937 }
2938 mwifiex_dbg(adapter, ERROR,
2939 "pre-allocated buf not enough\n");
2940 tmp_ptr =
2941 vzalloc(memory_size + MWIFIEX_SIZE_4K);
2942 if (!tmp_ptr)
2943 return;
2944 memcpy(tmp_ptr, entry->mem_ptr, memory_size);
2945 vfree(entry->mem_ptr);
2946 entry->mem_ptr = tmp_ptr;
2947 tmp_ptr = NULL;
2948 dbg_ptr = entry->mem_ptr + memory_size;
2949 memory_size += MWIFIEX_SIZE_4K;
2950 end_ptr = entry->mem_ptr + memory_size;
2951 }
2952
2953 if (stat != RDWR_STATUS_DONE)
2954 continue;
2955
2956 mwifiex_dbg(adapter, DUMP,
2957 "%s done: size=0x%tx\n",
2958 entry->mem_name, dbg_ptr - entry->mem_ptr);
2959 break;
2960 } while (true);
2961 }
2962 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump end ==\n");
2963 }
2964
mwifiex_pcie_device_dump_work(struct mwifiex_adapter * adapter)2965 static void mwifiex_pcie_device_dump_work(struct mwifiex_adapter *adapter)
2966 {
2967 adapter->devdump_data = vzalloc(MWIFIEX_FW_DUMP_SIZE);
2968 if (!adapter->devdump_data) {
2969 mwifiex_dbg(adapter, ERROR,
2970 "vzalloc devdump data failure!\n");
2971 return;
2972 }
2973
2974 mwifiex_drv_info_dump(adapter);
2975 mwifiex_pcie_fw_dump(adapter);
2976 mwifiex_prepare_fw_dump_info(adapter);
2977 mwifiex_upload_device_dump(adapter);
2978 }
2979
mwifiex_pcie_card_reset_work(struct mwifiex_adapter * adapter)2980 static void mwifiex_pcie_card_reset_work(struct mwifiex_adapter *adapter)
2981 {
2982 struct pcie_service_card *card = adapter->card;
2983
2984 /* We can't afford to wait here; remove() might be waiting on us. If we
2985 * can't grab the device lock, maybe we'll get another chance later.
2986 */
2987 pci_try_reset_function(card->dev);
2988 }
2989
mwifiex_pcie_work(struct work_struct * work)2990 static void mwifiex_pcie_work(struct work_struct *work)
2991 {
2992 struct pcie_service_card *card =
2993 container_of(work, struct pcie_service_card, work);
2994
2995 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP,
2996 &card->work_flags))
2997 mwifiex_pcie_device_dump_work(card->adapter);
2998 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET,
2999 &card->work_flags))
3000 mwifiex_pcie_card_reset_work(card->adapter);
3001 }
3002
3003 /* This function dumps FW information */
mwifiex_pcie_device_dump(struct mwifiex_adapter * adapter)3004 static void mwifiex_pcie_device_dump(struct mwifiex_adapter *adapter)
3005 {
3006 struct pcie_service_card *card = adapter->card;
3007
3008 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP,
3009 &card->work_flags))
3010 schedule_work(&card->work);
3011 }
3012
mwifiex_pcie_card_reset(struct mwifiex_adapter * adapter)3013 static void mwifiex_pcie_card_reset(struct mwifiex_adapter *adapter)
3014 {
3015 struct pcie_service_card *card = adapter->card;
3016
3017 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags))
3018 schedule_work(&card->work);
3019 }
3020
mwifiex_pcie_alloc_buffers(struct mwifiex_adapter * adapter)3021 static int mwifiex_pcie_alloc_buffers(struct mwifiex_adapter *adapter)
3022 {
3023 struct pcie_service_card *card = adapter->card;
3024 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
3025 int ret;
3026
3027 card->cmdrsp_buf = NULL;
3028 ret = mwifiex_pcie_create_txbd_ring(adapter);
3029 if (ret) {
3030 mwifiex_dbg(adapter, ERROR, "Failed to create txbd ring\n");
3031 goto err_cre_txbd;
3032 }
3033
3034 ret = mwifiex_pcie_create_rxbd_ring(adapter);
3035 if (ret) {
3036 mwifiex_dbg(adapter, ERROR, "Failed to create rxbd ring\n");
3037 goto err_cre_rxbd;
3038 }
3039
3040 ret = mwifiex_pcie_create_evtbd_ring(adapter);
3041 if (ret) {
3042 mwifiex_dbg(adapter, ERROR, "Failed to create evtbd ring\n");
3043 goto err_cre_evtbd;
3044 }
3045
3046 ret = mwifiex_pcie_alloc_cmdrsp_buf(adapter);
3047 if (ret) {
3048 mwifiex_dbg(adapter, ERROR, "Failed to allocate cmdbuf buffer\n");
3049 goto err_alloc_cmdbuf;
3050 }
3051
3052 if (reg->sleep_cookie) {
3053 ret = mwifiex_pcie_alloc_sleep_cookie_buf(adapter);
3054 if (ret) {
3055 mwifiex_dbg(adapter, ERROR, "Failed to allocate sleep_cookie buffer\n");
3056 goto err_alloc_cookie;
3057 }
3058 } else {
3059 card->sleep_cookie_vbase = NULL;
3060 }
3061
3062 return 0;
3063
3064 err_alloc_cookie:
3065 mwifiex_pcie_delete_cmdrsp_buf(adapter);
3066 err_alloc_cmdbuf:
3067 mwifiex_pcie_delete_evtbd_ring(adapter);
3068 err_cre_evtbd:
3069 mwifiex_pcie_delete_rxbd_ring(adapter);
3070 err_cre_rxbd:
3071 mwifiex_pcie_delete_txbd_ring(adapter);
3072 err_cre_txbd:
3073 return ret;
3074 }
3075
mwifiex_pcie_free_buffers(struct mwifiex_adapter * adapter)3076 static void mwifiex_pcie_free_buffers(struct mwifiex_adapter *adapter)
3077 {
3078 struct pcie_service_card *card = adapter->card;
3079 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
3080
3081 if (reg->sleep_cookie)
3082 mwifiex_pcie_delete_sleep_cookie_buf(adapter);
3083
3084 mwifiex_pcie_delete_cmdrsp_buf(adapter);
3085 mwifiex_pcie_delete_evtbd_ring(adapter);
3086 mwifiex_pcie_delete_rxbd_ring(adapter);
3087 mwifiex_pcie_delete_txbd_ring(adapter);
3088 }
3089
3090 /*
3091 * This function initializes the PCI-E host memory space, WCB rings, etc.
3092 */
mwifiex_init_pcie(struct mwifiex_adapter * adapter)3093 static int mwifiex_init_pcie(struct mwifiex_adapter *adapter)
3094 {
3095 struct pcie_service_card *card = adapter->card;
3096 int ret;
3097 struct pci_dev *pdev = card->dev;
3098
3099 pci_set_drvdata(pdev, card);
3100
3101 ret = pci_enable_device(pdev);
3102 if (ret)
3103 goto err_enable_dev;
3104
3105 pci_set_master(pdev);
3106
3107 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3108 if (ret) {
3109 pr_err("dma_set_mask(32) failed: %d\n", ret);
3110 goto err_set_dma_mask;
3111 }
3112
3113 ret = pci_request_region(pdev, 0, DRV_NAME);
3114 if (ret) {
3115 pr_err("req_reg(0) error\n");
3116 goto err_req_region0;
3117 }
3118 card->pci_mmap = pci_iomap(pdev, 0, 0);
3119 if (!card->pci_mmap) {
3120 pr_err("iomap(0) error\n");
3121 ret = -EIO;
3122 goto err_iomap0;
3123 }
3124 ret = pci_request_region(pdev, 2, DRV_NAME);
3125 if (ret) {
3126 pr_err("req_reg(2) error\n");
3127 goto err_req_region2;
3128 }
3129 card->pci_mmap1 = pci_iomap(pdev, 2, 0);
3130 if (!card->pci_mmap1) {
3131 pr_err("iomap(2) error\n");
3132 ret = -EIO;
3133 goto err_iomap2;
3134 }
3135
3136 pr_notice("PCI memory map Virt0: %pK PCI memory map Virt2: %pK\n",
3137 card->pci_mmap, card->pci_mmap1);
3138
3139 ret = mwifiex_pcie_alloc_buffers(adapter);
3140 if (ret)
3141 goto err_alloc_buffers;
3142
3143 if (pdev->device == PCIE_DEVICE_ID_MARVELL_88W8897)
3144 adapter->ignore_btcoex_events = true;
3145
3146 return 0;
3147
3148 err_alloc_buffers:
3149 pci_iounmap(pdev, card->pci_mmap1);
3150 err_iomap2:
3151 pci_release_region(pdev, 2);
3152 err_req_region2:
3153 pci_iounmap(pdev, card->pci_mmap);
3154 err_iomap0:
3155 pci_release_region(pdev, 0);
3156 err_req_region0:
3157 err_set_dma_mask:
3158 pci_disable_device(pdev);
3159 err_enable_dev:
3160 return ret;
3161 }
3162
3163 /*
3164 * This function cleans up the allocated card buffers.
3165 */
mwifiex_cleanup_pcie(struct mwifiex_adapter * adapter)3166 static void mwifiex_cleanup_pcie(struct mwifiex_adapter *adapter)
3167 {
3168 struct pcie_service_card *card = adapter->card;
3169 struct pci_dev *pdev = card->dev;
3170 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
3171 u32 fw_status;
3172
3173 /* Perform the cancel_work_sync() only when we're not resetting
3174 * the card. It's because that function never returns if we're
3175 * in reset path. If we're here when resetting the card, it means
3176 * that we failed to reset the card (reset failure path).
3177 */
3178 if (!card->pci_reset_ongoing) {
3179 mwifiex_dbg(adapter, MSG, "performing cancel_work_sync()...\n");
3180 cancel_work_sync(&card->work);
3181 mwifiex_dbg(adapter, MSG, "cancel_work_sync() done\n");
3182 } else {
3183 mwifiex_dbg(adapter, MSG,
3184 "skipped cancel_work_sync() because we're in card reset failure path\n");
3185 }
3186
3187 mwifiex_read_reg(adapter, reg->fw_status, &fw_status);
3188 if (fw_status == FIRMWARE_READY_PCIE) {
3189 mwifiex_dbg(adapter, INFO,
3190 "Clearing driver ready signature\n");
3191 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000))
3192 mwifiex_dbg(adapter, ERROR,
3193 "Failed to write driver not-ready signature\n");
3194 }
3195
3196 pci_disable_device(pdev);
3197
3198 pci_iounmap(pdev, card->pci_mmap);
3199 pci_iounmap(pdev, card->pci_mmap1);
3200 pci_release_region(pdev, 2);
3201 pci_release_region(pdev, 0);
3202
3203 mwifiex_pcie_free_buffers(adapter);
3204 }
3205
mwifiex_pcie_request_irq(struct mwifiex_adapter * adapter)3206 static int mwifiex_pcie_request_irq(struct mwifiex_adapter *adapter)
3207 {
3208 int ret, i, j;
3209 struct pcie_service_card *card = adapter->card;
3210 struct pci_dev *pdev = card->dev;
3211
3212 if (card->pcie.reg->msix_support) {
3213 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
3214 card->msix_entries[i].entry = i;
3215 ret = pci_enable_msix_exact(pdev, card->msix_entries,
3216 MWIFIEX_NUM_MSIX_VECTORS);
3217 if (!ret) {
3218 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) {
3219 card->msix_ctx[i].dev = pdev;
3220 card->msix_ctx[i].msg_id = i;
3221
3222 ret = request_irq(card->msix_entries[i].vector,
3223 mwifiex_pcie_interrupt, 0,
3224 "MWIFIEX_PCIE_MSIX",
3225 &card->msix_ctx[i]);
3226 if (ret)
3227 break;
3228 }
3229
3230 if (ret) {
3231 mwifiex_dbg(adapter, INFO, "request_irq fail: %d\n",
3232 ret);
3233 for (j = 0; j < i; j++)
3234 free_irq(card->msix_entries[j].vector,
3235 &card->msix_ctx[i]);
3236 pci_disable_msix(pdev);
3237 } else {
3238 mwifiex_dbg(adapter, MSG, "MSIx enabled!");
3239 card->msix_enable = 1;
3240 return 0;
3241 }
3242 }
3243 }
3244
3245 if (pci_enable_msi(pdev) != 0)
3246 pci_disable_msi(pdev);
3247 else
3248 card->msi_enable = 1;
3249
3250 mwifiex_dbg(adapter, INFO, "msi_enable = %d\n", card->msi_enable);
3251
3252 card->share_irq_ctx.dev = pdev;
3253 card->share_irq_ctx.msg_id = -1;
3254 ret = request_irq(pdev->irq, mwifiex_pcie_interrupt, IRQF_SHARED,
3255 "MRVL_PCIE", &card->share_irq_ctx);
3256 if (ret) {
3257 pr_err("request_irq failed: ret=%d\n", ret);
3258 return -1;
3259 }
3260
3261 return 0;
3262 }
3263
3264 /*
3265 * This function gets the firmware name for downloading by revision id
3266 *
3267 * Read revision id register to get revision id
3268 */
mwifiex_pcie_get_fw_name(struct mwifiex_adapter * adapter)3269 static void mwifiex_pcie_get_fw_name(struct mwifiex_adapter *adapter)
3270 {
3271 int revision_id = 0;
3272 int version, magic;
3273 struct pcie_service_card *card = adapter->card;
3274
3275 switch (card->dev->device) {
3276 case PCIE_DEVICE_ID_MARVELL_88W8766P:
3277 strcpy(adapter->fw_name, PCIE8766_DEFAULT_FW_NAME);
3278 break;
3279 case PCIE_DEVICE_ID_MARVELL_88W8897:
3280 mwifiex_write_reg(adapter, 0x0c58, 0x80c00000);
3281 mwifiex_read_reg(adapter, 0x0c58, &revision_id);
3282 revision_id &= 0xff00;
3283 switch (revision_id) {
3284 case PCIE8897_A0:
3285 strcpy(adapter->fw_name, PCIE8897_A0_FW_NAME);
3286 break;
3287 case PCIE8897_B0:
3288 strcpy(adapter->fw_name, PCIE8897_B0_FW_NAME);
3289 break;
3290 default:
3291 strcpy(adapter->fw_name, PCIE8897_DEFAULT_FW_NAME);
3292
3293 break;
3294 }
3295 break;
3296 case PCIE_DEVICE_ID_MARVELL_88W8997:
3297 mwifiex_read_reg(adapter, 0x8, &revision_id);
3298 mwifiex_read_reg(adapter, 0x0cd0, &version);
3299 mwifiex_read_reg(adapter, 0x0cd4, &magic);
3300 revision_id &= 0xff;
3301 version &= 0x7;
3302 magic &= 0xff;
3303 if (revision_id == PCIE8997_A1 &&
3304 magic == CHIP_MAGIC_VALUE &&
3305 version == CHIP_VER_PCIEUART)
3306 strcpy(adapter->fw_name, PCIEUART8997_FW_NAME_V4);
3307 else
3308 strcpy(adapter->fw_name, PCIEUSB8997_FW_NAME_V4);
3309 break;
3310 default:
3311 break;
3312 }
3313 }
3314
3315 /*
3316 * This function registers the PCIE device.
3317 *
3318 * PCIE IRQ is claimed, block size is set and driver data is initialized.
3319 */
mwifiex_register_dev(struct mwifiex_adapter * adapter)3320 static int mwifiex_register_dev(struct mwifiex_adapter *adapter)
3321 {
3322 struct pcie_service_card *card = adapter->card;
3323
3324 /* save adapter pointer in card */
3325 card->adapter = adapter;
3326
3327 if (mwifiex_pcie_request_irq(adapter))
3328 return -1;
3329
3330 adapter->tx_buf_size = card->pcie.tx_buf_size;
3331 adapter->mem_type_mapping_tbl = card->pcie.mem_type_mapping_tbl;
3332 adapter->num_mem_types = card->pcie.num_mem_types;
3333 adapter->ext_scan = card->pcie.can_ext_scan;
3334 mwifiex_pcie_get_fw_name(adapter);
3335
3336 return 0;
3337 }
3338
3339 /*
3340 * This function unregisters the PCIE device.
3341 *
3342 * The PCIE IRQ is released, the function is disabled and driver
3343 * data is set to null.
3344 */
mwifiex_unregister_dev(struct mwifiex_adapter * adapter)3345 static void mwifiex_unregister_dev(struct mwifiex_adapter *adapter)
3346 {
3347 struct pcie_service_card *card = adapter->card;
3348 struct pci_dev *pdev = card->dev;
3349 int i;
3350
3351 if (card->msix_enable) {
3352 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
3353 synchronize_irq(card->msix_entries[i].vector);
3354
3355 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
3356 free_irq(card->msix_entries[i].vector,
3357 &card->msix_ctx[i]);
3358
3359 card->msix_enable = 0;
3360 pci_disable_msix(pdev);
3361 } else {
3362 mwifiex_dbg(adapter, INFO,
3363 "%s(): calling free_irq()\n", __func__);
3364 free_irq(card->dev->irq, &card->share_irq_ctx);
3365
3366 if (card->msi_enable)
3367 pci_disable_msi(pdev);
3368 }
3369 card->adapter = NULL;
3370 }
3371
3372 /*
3373 * This function initializes the PCI-E host memory space, WCB rings, etc.,
3374 * similar to mwifiex_init_pcie(), but without resetting PCI-E state.
3375 */
mwifiex_pcie_up_dev(struct mwifiex_adapter * adapter)3376 static void mwifiex_pcie_up_dev(struct mwifiex_adapter *adapter)
3377 {
3378 struct pcie_service_card *card = adapter->card;
3379 struct pci_dev *pdev = card->dev;
3380
3381 /* tx_buf_size might be changed to 3584 by firmware during
3382 * data transfer, we should reset it to default size.
3383 */
3384 adapter->tx_buf_size = card->pcie.tx_buf_size;
3385
3386 mwifiex_pcie_alloc_buffers(adapter);
3387
3388 pci_set_master(pdev);
3389 }
3390
3391 /* This function cleans up the PCI-E host memory space. */
mwifiex_pcie_down_dev(struct mwifiex_adapter * adapter)3392 static void mwifiex_pcie_down_dev(struct mwifiex_adapter *adapter)
3393 {
3394 struct pcie_service_card *card = adapter->card;
3395 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
3396 struct pci_dev *pdev = card->dev;
3397
3398 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000))
3399 mwifiex_dbg(adapter, ERROR, "Failed to write driver not-ready signature\n");
3400
3401 pci_clear_master(pdev);
3402
3403 adapter->seq_num = 0;
3404
3405 mwifiex_pcie_free_buffers(adapter);
3406 }
3407
3408 static struct mwifiex_if_ops pcie_ops = {
3409 .init_if = mwifiex_init_pcie,
3410 .cleanup_if = mwifiex_cleanup_pcie,
3411 .check_fw_status = mwifiex_check_fw_status,
3412 .check_winner_status = mwifiex_check_winner_status,
3413 .prog_fw = mwifiex_prog_fw_w_helper,
3414 .register_dev = mwifiex_register_dev,
3415 .unregister_dev = mwifiex_unregister_dev,
3416 .enable_int = mwifiex_pcie_enable_host_int,
3417 .disable_int = mwifiex_pcie_disable_host_int_noerr,
3418 .process_int_status = mwifiex_process_int_status,
3419 .host_to_card = mwifiex_pcie_host_to_card,
3420 .wakeup = mwifiex_pm_wakeup_card,
3421 .wakeup_complete = mwifiex_pm_wakeup_card_complete,
3422
3423 /* PCIE specific */
3424 .cmdrsp_complete = mwifiex_pcie_cmdrsp_complete,
3425 .event_complete = mwifiex_pcie_event_complete,
3426 .update_mp_end_port = NULL,
3427 .cleanup_mpa_buf = NULL,
3428 .init_fw_port = mwifiex_pcie_init_fw_port,
3429 .clean_pcie_ring = mwifiex_clean_pcie_ring_buf,
3430 .card_reset = mwifiex_pcie_card_reset,
3431 .reg_dump = mwifiex_pcie_reg_dump,
3432 .device_dump = mwifiex_pcie_device_dump,
3433 .down_dev = mwifiex_pcie_down_dev,
3434 .up_dev = mwifiex_pcie_up_dev,
3435 };
3436
3437 module_pci_driver(mwifiex_pcie);
3438
3439 MODULE_AUTHOR("Marvell International Ltd.");
3440 MODULE_DESCRIPTION("Marvell WiFi-Ex PCI-Express Driver version " PCIE_VERSION);
3441 MODULE_VERSION(PCIE_VERSION);
3442 MODULE_LICENSE("GPL v2");
3443
