1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Microchip Technology
4 */
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/mii.h>
8 #include <linux/ethtool.h>
9 #include <linux/phy.h>
10 #include <linux/microchipphy.h>
11 #include <linux/delay.h>
12 #include <linux/of.h>
13 #include <dt-bindings/net/microchip-lan78xx.h>
14
15 #define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
16 #define DRIVER_DESC "Microchip LAN88XX PHY driver"
17
18 struct lan88xx_priv {
19 int chip_id;
20 int chip_rev;
21 __u32 wolopts;
22 };
23
lan88xx_read_page(struct phy_device * phydev)24 static int lan88xx_read_page(struct phy_device *phydev)
25 {
26 return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS);
27 }
28
lan88xx_write_page(struct phy_device * phydev,int page)29 static int lan88xx_write_page(struct phy_device *phydev, int page)
30 {
31 return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page);
32 }
33
lan88xx_phy_config_intr(struct phy_device * phydev)34 static int lan88xx_phy_config_intr(struct phy_device *phydev)
35 {
36 int rc;
37
38 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
39 /* unmask all source and clear them before enable */
40 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF);
41 rc = phy_read(phydev, LAN88XX_INT_STS);
42 rc = phy_write(phydev, LAN88XX_INT_MASK,
43 LAN88XX_INT_MASK_MDINTPIN_EN_ |
44 LAN88XX_INT_MASK_LINK_CHANGE_);
45 } else {
46 rc = phy_write(phydev, LAN88XX_INT_MASK, 0);
47 if (rc)
48 return rc;
49
50 /* Ack interrupts after they have been disabled */
51 rc = phy_read(phydev, LAN88XX_INT_STS);
52 }
53
54 return rc < 0 ? rc : 0;
55 }
56
lan88xx_handle_interrupt(struct phy_device * phydev)57 static irqreturn_t lan88xx_handle_interrupt(struct phy_device *phydev)
58 {
59 int irq_status;
60
61 irq_status = phy_read(phydev, LAN88XX_INT_STS);
62 if (irq_status < 0) {
63 phy_error(phydev);
64 return IRQ_NONE;
65 }
66
67 if (!(irq_status & LAN88XX_INT_STS_LINK_CHANGE_))
68 return IRQ_NONE;
69
70 phy_trigger_machine(phydev);
71
72 return IRQ_HANDLED;
73 }
74
lan88xx_suspend(struct phy_device * phydev)75 static int lan88xx_suspend(struct phy_device *phydev)
76 {
77 struct lan88xx_priv *priv = phydev->priv;
78
79 /* do not power down PHY when WOL is enabled */
80 if (!priv->wolopts)
81 genphy_suspend(phydev);
82
83 return 0;
84 }
85
lan88xx_TR_reg_set(struct phy_device * phydev,u16 regaddr,u32 data)86 static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
87 u32 data)
88 {
89 int val, save_page, ret = 0;
90 u16 buf;
91
92 /* Save current page */
93 save_page = phy_save_page(phydev);
94 if (save_page < 0) {
95 phydev_warn(phydev, "Failed to get current page\n");
96 goto err;
97 }
98
99 /* Switch to TR page */
100 lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR);
101
102 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA,
103 (data & 0xFFFF));
104 if (ret < 0) {
105 phydev_warn(phydev, "Failed to write TR low data\n");
106 goto err;
107 }
108
109 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA,
110 (data & 0x00FF0000) >> 16);
111 if (ret < 0) {
112 phydev_warn(phydev, "Failed to write TR high data\n");
113 goto err;
114 }
115
116 /* Config control bits [15:13] of register */
117 buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */
118 buf |= 0x8000; /* Set [15] to Packet transmit */
119
120 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf);
121 if (ret < 0) {
122 phydev_warn(phydev, "Failed to write data in reg\n");
123 goto err;
124 }
125
126 usleep_range(1000, 2000);/* Wait for Data to be written */
127 val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR);
128 if (!(val & 0x8000))
129 phydev_warn(phydev, "TR Register[0x%X] configuration failed\n",
130 regaddr);
131 err:
132 return phy_restore_page(phydev, save_page, ret);
133 }
134
lan88xx_config_TR_regs(struct phy_device * phydev)135 static void lan88xx_config_TR_regs(struct phy_device *phydev)
136 {
137 int err;
138
139 /* Get access to Channel 0x1, Node 0xF , Register 0x01.
140 * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf,
141 * MrvlTrFix1000Kp, MasterEnableTR bits.
142 */
143 err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A);
144 if (err < 0)
145 phydev_warn(phydev, "Failed to Set Register[0x0F82]\n");
146
147 /* Get access to Channel b'10, Node b'1101, Register 0x06.
148 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv,
149 * SSTrKp1000Mas bits.
150 */
151 err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F);
152 if (err < 0)
153 phydev_warn(phydev, "Failed to Set Register[0x168C]\n");
154
155 /* Get access to Channel b'10, Node b'1111, Register 0x11.
156 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh
157 * bits
158 */
159 err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620);
160 if (err < 0)
161 phydev_warn(phydev, "Failed to Set Register[0x17A2]\n");
162
163 /* Get access to Channel b'10, Node b'1101, Register 0x10.
164 * Write 24-bit value 0xEEFFDD to register. Setting
165 * eee_TrKp1Long_1000, eee_TrKp2Long_1000, eee_TrKp3Long_1000,
166 * eee_TrKp1Short_1000,eee_TrKp2Short_1000, eee_TrKp3Short_1000 bits.
167 */
168 err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD);
169 if (err < 0)
170 phydev_warn(phydev, "Failed to Set Register[0x16A0]\n");
171
172 /* Get access to Channel b'10, Node b'1101, Register 0x13.
173 * Write 24-bit value 0x071448 to register. Setting
174 * slv_lpi_tr_tmr_val1, slv_lpi_tr_tmr_val2 bits.
175 */
176 err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448);
177 if (err < 0)
178 phydev_warn(phydev, "Failed to Set Register[0x16A6]\n");
179
180 /* Get access to Channel b'10, Node b'1101, Register 0x12.
181 * Write 24-bit value 0x13132F to register. Setting
182 * slv_sigdet_timer_val1, slv_sigdet_timer_val2 bits.
183 */
184 err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F);
185 if (err < 0)
186 phydev_warn(phydev, "Failed to Set Register[0x16A4]\n");
187
188 /* Get access to Channel b'10, Node b'1101, Register 0x14.
189 * Write 24-bit value 0x0 to register. Setting eee_3level_delay,
190 * eee_TrKf_freeze_delay bits.
191 */
192 err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0);
193 if (err < 0)
194 phydev_warn(phydev, "Failed to Set Register[0x16A8]\n");
195
196 /* Get access to Channel b'01, Node b'1111, Register 0x34.
197 * Write 24-bit value 0x91B06C to register. Setting
198 * FastMseSearchThreshLong1000, FastMseSearchThreshShort1000,
199 * FastMseSearchUpdGain1000 bits.
200 */
201 err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C);
202 if (err < 0)
203 phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n");
204
205 /* Get access to Channel b'01, Node b'1111, Register 0x3E.
206 * Write 24-bit value 0xC0A028 to register. Setting
207 * FastMseKp2ThreshLong1000, FastMseKp2ThreshShort1000,
208 * FastMseKp2UpdGain1000, FastMseKp2ExitEn1000 bits.
209 */
210 err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028);
211 if (err < 0)
212 phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n");
213
214 /* Get access to Channel b'01, Node b'1111, Register 0x35.
215 * Write 24-bit value 0x041600 to register. Setting
216 * FastMseSearchPhShNum1000, FastMseSearchClksPerPh1000,
217 * FastMsePhChangeDelay1000 bits.
218 */
219 err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600);
220 if (err < 0)
221 phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n");
222
223 /* Get access to Channel b'10, Node b'1101, Register 0x03.
224 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits.
225 */
226 err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004);
227 if (err < 0)
228 phydev_warn(phydev, "Failed to Set Register[0x1686]\n");
229 }
230
lan88xx_probe(struct phy_device * phydev)231 static int lan88xx_probe(struct phy_device *phydev)
232 {
233 struct device *dev = &phydev->mdio.dev;
234 struct lan88xx_priv *priv;
235 u32 led_modes[4];
236 int len;
237
238 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
239 if (!priv)
240 return -ENOMEM;
241
242 priv->wolopts = 0;
243
244 len = of_property_read_variable_u32_array(dev->of_node,
245 "microchip,led-modes",
246 led_modes,
247 0,
248 ARRAY_SIZE(led_modes));
249 if (len >= 0) {
250 u32 reg = 0;
251 int i;
252
253 for (i = 0; i < len; i++) {
254 if (led_modes[i] > 15)
255 return -EINVAL;
256 reg |= led_modes[i] << (i * 4);
257 }
258 for (; i < ARRAY_SIZE(led_modes); i++)
259 reg |= LAN78XX_FORCE_LED_OFF << (i * 4);
260 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg);
261 } else if (len == -EOVERFLOW) {
262 return -EINVAL;
263 }
264
265 /* these values can be used to identify internal PHY */
266 priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);
267 priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);
268
269 phydev->priv = priv;
270
271 return 0;
272 }
273
lan88xx_remove(struct phy_device * phydev)274 static void lan88xx_remove(struct phy_device *phydev)
275 {
276 struct device *dev = &phydev->mdio.dev;
277 struct lan88xx_priv *priv = phydev->priv;
278
279 if (priv)
280 devm_kfree(dev, priv);
281 }
282
lan88xx_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)283 static int lan88xx_set_wol(struct phy_device *phydev,
284 struct ethtool_wolinfo *wol)
285 {
286 struct lan88xx_priv *priv = phydev->priv;
287
288 priv->wolopts = wol->wolopts;
289
290 return 0;
291 }
292
lan88xx_set_mdix(struct phy_device * phydev)293 static void lan88xx_set_mdix(struct phy_device *phydev)
294 {
295 int buf;
296 int val;
297
298 switch (phydev->mdix_ctrl) {
299 case ETH_TP_MDI:
300 val = LAN88XX_EXT_MODE_CTRL_MDI_;
301 break;
302 case ETH_TP_MDI_X:
303 val = LAN88XX_EXT_MODE_CTRL_MDI_X_;
304 break;
305 case ETH_TP_MDI_AUTO:
306 val = LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_;
307 break;
308 default:
309 return;
310 }
311
312 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1);
313 buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
314 buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
315 buf |= val;
316 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf);
317 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
318 }
319
lan88xx_config_init(struct phy_device * phydev)320 static int lan88xx_config_init(struct phy_device *phydev)
321 {
322 int val;
323
324 /*Zerodetect delay enable */
325 val = phy_read_mmd(phydev, MDIO_MMD_PCS,
326 PHY_ARDENNES_MMD_DEV_3_PHY_CFG);
327 val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_;
328
329 phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG,
330 val);
331
332 /* Config DSP registers */
333 lan88xx_config_TR_regs(phydev);
334
335 return 0;
336 }
337
lan88xx_config_aneg(struct phy_device * phydev)338 static int lan88xx_config_aneg(struct phy_device *phydev)
339 {
340 lan88xx_set_mdix(phydev);
341
342 return genphy_config_aneg(phydev);
343 }
344
345 static struct phy_driver microchip_phy_driver[] = {
346 {
347 .phy_id = 0x0007c132,
348 /* This mask (0xfffffff2) is to differentiate from
349 * LAN8742 (phy_id 0x0007c130 and 0x0007c131)
350 * and allows future phy_id revisions.
351 */
352 .phy_id_mask = 0xfffffff2,
353 .name = "Microchip LAN88xx",
354
355 /* PHY_GBIT_FEATURES */
356
357 .probe = lan88xx_probe,
358 .remove = lan88xx_remove,
359
360 .config_init = lan88xx_config_init,
361 .config_aneg = lan88xx_config_aneg,
362
363 .config_intr = lan88xx_phy_config_intr,
364 .handle_interrupt = lan88xx_handle_interrupt,
365
366 .suspend = lan88xx_suspend,
367 .resume = genphy_resume,
368 .set_wol = lan88xx_set_wol,
369 .read_page = lan88xx_read_page,
370 .write_page = lan88xx_write_page,
371 } };
372
373 module_phy_driver(microchip_phy_driver);
374
375 static struct mdio_device_id __maybe_unused microchip_tbl[] = {
376 { 0x0007c132, 0xfffffff2 },
377 { }
378 };
379
380 MODULE_DEVICE_TABLE(mdio, microchip_tbl);
381
382 MODULE_AUTHOR(DRIVER_AUTHOR);
383 MODULE_DESCRIPTION(DRIVER_DESC);
384 MODULE_LICENSE("GPL");
385
