1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Copyright (C) 2019 IBM Corp. */
3
4 #include <linux/bitfield.h>
5 #include <linux/delay.h>
6 #include <linux/reset.h>
7 #include <linux/iopoll.h>
8 #include <linux/mdio.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_mdio.h>
12 #include <linux/phy.h>
13 #include <linux/platform_device.h>
14
15 #define DRV_NAME "mdio-aspeed"
16
17 #define ASPEED_MDIO_CTRL 0x0
18 #define ASPEED_MDIO_CTRL_FIRE BIT(31)
19 #define ASPEED_MDIO_CTRL_ST BIT(28)
20 #define ASPEED_MDIO_CTRL_ST_C45 0
21 #define ASPEED_MDIO_CTRL_ST_C22 1
22 #define ASPEED_MDIO_CTRL_OP GENMASK(27, 26)
23 #define MDIO_C22_OP_WRITE 0b01
24 #define MDIO_C22_OP_READ 0b10
25 #define MDIO_C45_OP_ADDR 0b00
26 #define MDIO_C45_OP_WRITE 0b01
27 #define MDIO_C45_OP_PREAD 0b10
28 #define MDIO_C45_OP_READ 0b11
29 #define ASPEED_MDIO_CTRL_PHYAD GENMASK(25, 21)
30 #define ASPEED_MDIO_CTRL_REGAD GENMASK(20, 16)
31 #define ASPEED_MDIO_CTRL_MIIWDATA GENMASK(15, 0)
32
33 #define ASPEED_MDIO_DATA 0x4
34 #define ASPEED_MDIO_DATA_MDC_THRES GENMASK(31, 24)
35 #define ASPEED_MDIO_DATA_MDIO_EDGE BIT(23)
36 #define ASPEED_MDIO_DATA_MDIO_LATCH GENMASK(22, 20)
37 #define ASPEED_MDIO_DATA_IDLE BIT(16)
38 #define ASPEED_MDIO_DATA_MIIRDATA GENMASK(15, 0)
39
40 #define ASPEED_MDIO_INTERVAL_US 100
41 #define ASPEED_MDIO_TIMEOUT_US (ASPEED_MDIO_INTERVAL_US * 10)
42
43 struct aspeed_mdio {
44 void __iomem *base;
45 struct reset_control *reset;
46 };
47
aspeed_mdio_op(struct mii_bus * bus,u8 st,u8 op,u8 phyad,u8 regad,u16 data)48 static int aspeed_mdio_op(struct mii_bus *bus, u8 st, u8 op, u8 phyad, u8 regad,
49 u16 data)
50 {
51 struct aspeed_mdio *ctx = bus->priv;
52 u32 ctrl;
53
54 dev_dbg(&bus->dev, "%s: st: %u op: %u, phyad: %u, regad: %u, data: %u\n",
55 __func__, st, op, phyad, regad, data);
56
57 ctrl = ASPEED_MDIO_CTRL_FIRE
58 | FIELD_PREP(ASPEED_MDIO_CTRL_ST, st)
59 | FIELD_PREP(ASPEED_MDIO_CTRL_OP, op)
60 | FIELD_PREP(ASPEED_MDIO_CTRL_PHYAD, phyad)
61 | FIELD_PREP(ASPEED_MDIO_CTRL_REGAD, regad)
62 | FIELD_PREP(ASPEED_MDIO_DATA_MIIRDATA, data);
63
64 iowrite32(ctrl, ctx->base + ASPEED_MDIO_CTRL);
65
66 return readl_poll_timeout(ctx->base + ASPEED_MDIO_CTRL, ctrl,
67 !(ctrl & ASPEED_MDIO_CTRL_FIRE),
68 ASPEED_MDIO_INTERVAL_US,
69 ASPEED_MDIO_TIMEOUT_US);
70 }
71
aspeed_mdio_get_data(struct mii_bus * bus)72 static int aspeed_mdio_get_data(struct mii_bus *bus)
73 {
74 struct aspeed_mdio *ctx = bus->priv;
75 u32 data;
76 int rc;
77
78 rc = readl_poll_timeout(ctx->base + ASPEED_MDIO_DATA, data,
79 data & ASPEED_MDIO_DATA_IDLE,
80 ASPEED_MDIO_INTERVAL_US,
81 ASPEED_MDIO_TIMEOUT_US);
82 if (rc < 0)
83 return rc;
84
85 return FIELD_GET(ASPEED_MDIO_DATA_MIIRDATA, data);
86 }
87
aspeed_mdio_read_c22(struct mii_bus * bus,int addr,int regnum)88 static int aspeed_mdio_read_c22(struct mii_bus *bus, int addr, int regnum)
89 {
90 int rc;
91
92 rc = aspeed_mdio_op(bus, ASPEED_MDIO_CTRL_ST_C22, MDIO_C22_OP_READ,
93 addr, regnum, 0);
94 if (rc < 0)
95 return rc;
96
97 return aspeed_mdio_get_data(bus);
98 }
99
aspeed_mdio_write_c22(struct mii_bus * bus,int addr,int regnum,u16 val)100 static int aspeed_mdio_write_c22(struct mii_bus *bus, int addr, int regnum,
101 u16 val)
102 {
103 return aspeed_mdio_op(bus, ASPEED_MDIO_CTRL_ST_C22, MDIO_C22_OP_WRITE,
104 addr, regnum, val);
105 }
106
aspeed_mdio_read_c45(struct mii_bus * bus,int addr,int regnum)107 static int aspeed_mdio_read_c45(struct mii_bus *bus, int addr, int regnum)
108 {
109 u8 c45_dev = (regnum >> 16) & 0x1F;
110 u16 c45_addr = regnum & 0xFFFF;
111 int rc;
112
113 rc = aspeed_mdio_op(bus, ASPEED_MDIO_CTRL_ST_C45, MDIO_C45_OP_ADDR,
114 addr, c45_dev, c45_addr);
115 if (rc < 0)
116 return rc;
117
118 rc = aspeed_mdio_op(bus, ASPEED_MDIO_CTRL_ST_C45, MDIO_C45_OP_READ,
119 addr, c45_dev, 0);
120 if (rc < 0)
121 return rc;
122
123 return aspeed_mdio_get_data(bus);
124 }
125
aspeed_mdio_write_c45(struct mii_bus * bus,int addr,int regnum,u16 val)126 static int aspeed_mdio_write_c45(struct mii_bus *bus, int addr, int regnum,
127 u16 val)
128 {
129 u8 c45_dev = (regnum >> 16) & 0x1F;
130 u16 c45_addr = regnum & 0xFFFF;
131 int rc;
132
133 rc = aspeed_mdio_op(bus, ASPEED_MDIO_CTRL_ST_C45, MDIO_C45_OP_ADDR,
134 addr, c45_dev, c45_addr);
135 if (rc < 0)
136 return rc;
137
138 return aspeed_mdio_op(bus, ASPEED_MDIO_CTRL_ST_C45, MDIO_C45_OP_WRITE,
139 addr, c45_dev, val);
140 }
141
aspeed_mdio_read(struct mii_bus * bus,int addr,int regnum)142 static int aspeed_mdio_read(struct mii_bus *bus, int addr, int regnum)
143 {
144 dev_dbg(&bus->dev, "%s: addr: %d, regnum: %d\n", __func__, addr,
145 regnum);
146
147 if (regnum & MII_ADDR_C45)
148 return aspeed_mdio_read_c45(bus, addr, regnum);
149
150 return aspeed_mdio_read_c22(bus, addr, regnum);
151 }
152
aspeed_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)153 static int aspeed_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val)
154 {
155 dev_dbg(&bus->dev, "%s: addr: %d, regnum: %d, val: 0x%x\n",
156 __func__, addr, regnum, val);
157
158 if (regnum & MII_ADDR_C45)
159 return aspeed_mdio_write_c45(bus, addr, regnum, val);
160
161 return aspeed_mdio_write_c22(bus, addr, regnum, val);
162 }
163
aspeed_mdio_probe(struct platform_device * pdev)164 static int aspeed_mdio_probe(struct platform_device *pdev)
165 {
166 struct aspeed_mdio *ctx;
167 struct mii_bus *bus;
168 int rc;
169
170 bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*ctx));
171 if (!bus)
172 return -ENOMEM;
173
174 ctx = bus->priv;
175 ctx->base = devm_platform_ioremap_resource(pdev, 0);
176 if (IS_ERR(ctx->base))
177 return PTR_ERR(ctx->base);
178
179 ctx->reset = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
180 if (IS_ERR(ctx->reset))
181 return PTR_ERR(ctx->reset);
182
183 reset_control_deassert(ctx->reset);
184
185 bus->name = DRV_NAME;
186 snprintf(bus->id, MII_BUS_ID_SIZE, "%s%d", pdev->name, pdev->id);
187 bus->parent = &pdev->dev;
188 bus->read = aspeed_mdio_read;
189 bus->write = aspeed_mdio_write;
190 bus->probe_capabilities = MDIOBUS_C22_C45;
191
192 rc = of_mdiobus_register(bus, pdev->dev.of_node);
193 if (rc) {
194 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
195 reset_control_assert(ctx->reset);
196 return rc;
197 }
198
199 platform_set_drvdata(pdev, bus);
200
201 return 0;
202 }
203
aspeed_mdio_remove(struct platform_device * pdev)204 static int aspeed_mdio_remove(struct platform_device *pdev)
205 {
206 struct mii_bus *bus = (struct mii_bus *)platform_get_drvdata(pdev);
207 struct aspeed_mdio *ctx = bus->priv;
208
209 reset_control_assert(ctx->reset);
210 mdiobus_unregister(bus);
211
212 return 0;
213 }
214
215 static const struct of_device_id aspeed_mdio_of_match[] = {
216 { .compatible = "aspeed,ast2600-mdio", },
217 { },
218 };
219 MODULE_DEVICE_TABLE(of, aspeed_mdio_of_match);
220
221 static struct platform_driver aspeed_mdio_driver = {
222 .driver = {
223 .name = DRV_NAME,
224 .of_match_table = aspeed_mdio_of_match,
225 },
226 .probe = aspeed_mdio_probe,
227 .remove = aspeed_mdio_remove,
228 };
229
230 module_platform_driver(aspeed_mdio_driver);
231
232 MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>");
233 MODULE_LICENSE("GPL");
234
