1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2020 Intel Corporation.
3
4 #include <asm/unaligned.h>
5 #include <linux/acpi.h>
6 #include <linux/delay.h>
7 #include <linux/i2c.h>
8 #include <linux/module.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/nvmem-provider.h>
11 #include <linux/regmap.h>
12 #include <media/v4l2-ctrls.h>
13 #include <media/v4l2-device.h>
14 #include <media/v4l2-fwnode.h>
15
16 #define OV2740_LINK_FREQ_360MHZ 360000000ULL
17 #define OV2740_SCLK 72000000LL
18 #define OV2740_MCLK 19200000
19 #define OV2740_DATA_LANES 2
20 #define OV2740_RGB_DEPTH 10
21
22 #define OV2740_REG_CHIP_ID 0x300a
23 #define OV2740_CHIP_ID 0x2740
24
25 #define OV2740_REG_MODE_SELECT 0x0100
26 #define OV2740_MODE_STANDBY 0x00
27 #define OV2740_MODE_STREAMING 0x01
28
29 /* vertical-timings from sensor */
30 #define OV2740_REG_VTS 0x380e
31 #define OV2740_VTS_DEF 0x088a
32 #define OV2740_VTS_MIN 0x0460
33 #define OV2740_VTS_MAX 0x7fff
34
35 /* horizontal-timings from sensor */
36 #define OV2740_REG_HTS 0x380c
37
38 /* Exposure controls from sensor */
39 #define OV2740_REG_EXPOSURE 0x3500
40 #define OV2740_EXPOSURE_MIN 4
41 #define OV2740_EXPOSURE_MAX_MARGIN 8
42 #define OV2740_EXPOSURE_STEP 1
43
44 /* Analog gain controls from sensor */
45 #define OV2740_REG_ANALOG_GAIN 0x3508
46 #define OV2740_ANAL_GAIN_MIN 128
47 #define OV2740_ANAL_GAIN_MAX 1983
48 #define OV2740_ANAL_GAIN_STEP 1
49
50 /* Digital gain controls from sensor */
51 #define OV2740_REG_MWB_R_GAIN 0x500a
52 #define OV2740_REG_MWB_G_GAIN 0x500c
53 #define OV2740_REG_MWB_B_GAIN 0x500e
54 #define OV2740_DGTL_GAIN_MIN 1024
55 #define OV2740_DGTL_GAIN_MAX 4095
56 #define OV2740_DGTL_GAIN_STEP 1
57 #define OV2740_DGTL_GAIN_DEFAULT 1024
58
59 /* Test Pattern Control */
60 #define OV2740_REG_TEST_PATTERN 0x5040
61 #define OV2740_TEST_PATTERN_ENABLE BIT(7)
62 #define OV2740_TEST_PATTERN_BAR_SHIFT 2
63
64 /* Group Access */
65 #define OV2740_REG_GROUP_ACCESS 0x3208
66 #define OV2740_GROUP_HOLD_START 0x0
67 #define OV2740_GROUP_HOLD_END 0x10
68 #define OV2740_GROUP_HOLD_LAUNCH 0xa0
69
70 /* ISP CTRL00 */
71 #define OV2740_REG_ISP_CTRL00 0x5000
72 /* ISP CTRL01 */
73 #define OV2740_REG_ISP_CTRL01 0x5001
74 /* Customer Addresses: 0x7010 - 0x710F */
75 #define CUSTOMER_USE_OTP_SIZE 0x100
76 /* OTP registers from sensor */
77 #define OV2740_REG_OTP_CUSTOMER 0x7010
78
79 struct nvm_data {
80 struct i2c_client *client;
81 struct nvmem_device *nvmem;
82 struct regmap *regmap;
83 char *nvm_buffer;
84 };
85
86 enum {
87 OV2740_LINK_FREQ_360MHZ_INDEX,
88 };
89
90 struct ov2740_reg {
91 u16 address;
92 u8 val;
93 };
94
95 struct ov2740_reg_list {
96 u32 num_of_regs;
97 const struct ov2740_reg *regs;
98 };
99
100 struct ov2740_link_freq_config {
101 const struct ov2740_reg_list reg_list;
102 };
103
104 struct ov2740_mode {
105 /* Frame width in pixels */
106 u32 width;
107
108 /* Frame height in pixels */
109 u32 height;
110
111 /* Horizontal timining size */
112 u32 hts;
113
114 /* Default vertical timining size */
115 u32 vts_def;
116
117 /* Min vertical timining size */
118 u32 vts_min;
119
120 /* Link frequency needed for this resolution */
121 u32 link_freq_index;
122
123 /* Sensor register settings for this resolution */
124 const struct ov2740_reg_list reg_list;
125 };
126
127 static const struct ov2740_reg mipi_data_rate_720mbps[] = {
128 {0x0103, 0x01},
129 {0x0302, 0x4b},
130 {0x030d, 0x4b},
131 {0x030e, 0x02},
132 {0x030a, 0x01},
133 {0x0312, 0x11},
134 };
135
136 static const struct ov2740_reg mode_1932x1092_regs[] = {
137 {0x3000, 0x00},
138 {0x3018, 0x32},
139 {0x3031, 0x0a},
140 {0x3080, 0x08},
141 {0x3083, 0xB4},
142 {0x3103, 0x00},
143 {0x3104, 0x01},
144 {0x3106, 0x01},
145 {0x3500, 0x00},
146 {0x3501, 0x44},
147 {0x3502, 0x40},
148 {0x3503, 0x88},
149 {0x3507, 0x00},
150 {0x3508, 0x00},
151 {0x3509, 0x80},
152 {0x350c, 0x00},
153 {0x350d, 0x80},
154 {0x3510, 0x00},
155 {0x3511, 0x00},
156 {0x3512, 0x20},
157 {0x3632, 0x00},
158 {0x3633, 0x10},
159 {0x3634, 0x10},
160 {0x3635, 0x10},
161 {0x3645, 0x13},
162 {0x3646, 0x81},
163 {0x3636, 0x10},
164 {0x3651, 0x0a},
165 {0x3656, 0x02},
166 {0x3659, 0x04},
167 {0x365a, 0xda},
168 {0x365b, 0xa2},
169 {0x365c, 0x04},
170 {0x365d, 0x1d},
171 {0x365e, 0x1a},
172 {0x3662, 0xd7},
173 {0x3667, 0x78},
174 {0x3669, 0x0a},
175 {0x366a, 0x92},
176 {0x3700, 0x54},
177 {0x3702, 0x10},
178 {0x3706, 0x42},
179 {0x3709, 0x30},
180 {0x370b, 0xc2},
181 {0x3714, 0x63},
182 {0x3715, 0x01},
183 {0x3716, 0x00},
184 {0x371a, 0x3e},
185 {0x3732, 0x0e},
186 {0x3733, 0x10},
187 {0x375f, 0x0e},
188 {0x3768, 0x30},
189 {0x3769, 0x44},
190 {0x376a, 0x22},
191 {0x377b, 0x20},
192 {0x377c, 0x00},
193 {0x377d, 0x0c},
194 {0x3798, 0x00},
195 {0x37a1, 0x55},
196 {0x37a8, 0x6d},
197 {0x37c2, 0x04},
198 {0x37c5, 0x00},
199 {0x37c8, 0x00},
200 {0x3800, 0x00},
201 {0x3801, 0x00},
202 {0x3802, 0x00},
203 {0x3803, 0x00},
204 {0x3804, 0x07},
205 {0x3805, 0x8f},
206 {0x3806, 0x04},
207 {0x3807, 0x47},
208 {0x3808, 0x07},
209 {0x3809, 0x88},
210 {0x380a, 0x04},
211 {0x380b, 0x40},
212 {0x380c, 0x04},
213 {0x380d, 0x38},
214 {0x380e, 0x04},
215 {0x380f, 0x60},
216 {0x3810, 0x00},
217 {0x3811, 0x04},
218 {0x3812, 0x00},
219 {0x3813, 0x04},
220 {0x3814, 0x01},
221 {0x3815, 0x01},
222 {0x3820, 0x80},
223 {0x3821, 0x46},
224 {0x3822, 0x84},
225 {0x3829, 0x00},
226 {0x382a, 0x01},
227 {0x382b, 0x01},
228 {0x3830, 0x04},
229 {0x3836, 0x01},
230 {0x3837, 0x08},
231 {0x3839, 0x01},
232 {0x383a, 0x00},
233 {0x383b, 0x08},
234 {0x383c, 0x00},
235 {0x3f0b, 0x00},
236 {0x4001, 0x20},
237 {0x4009, 0x07},
238 {0x4003, 0x10},
239 {0x4010, 0xe0},
240 {0x4016, 0x00},
241 {0x4017, 0x10},
242 {0x4044, 0x02},
243 {0x4304, 0x08},
244 {0x4307, 0x30},
245 {0x4320, 0x80},
246 {0x4322, 0x00},
247 {0x4323, 0x00},
248 {0x4324, 0x00},
249 {0x4325, 0x00},
250 {0x4326, 0x00},
251 {0x4327, 0x00},
252 {0x4328, 0x00},
253 {0x4329, 0x00},
254 {0x432c, 0x03},
255 {0x432d, 0x81},
256 {0x4501, 0x84},
257 {0x4502, 0x40},
258 {0x4503, 0x18},
259 {0x4504, 0x04},
260 {0x4508, 0x02},
261 {0x4601, 0x10},
262 {0x4800, 0x00},
263 {0x4816, 0x52},
264 {0x4837, 0x16},
265 {0x5000, 0x7f},
266 {0x5001, 0x00},
267 {0x5005, 0x38},
268 {0x501e, 0x0d},
269 {0x5040, 0x00},
270 {0x5901, 0x00},
271 {0x3800, 0x00},
272 {0x3801, 0x00},
273 {0x3802, 0x00},
274 {0x3803, 0x00},
275 {0x3804, 0x07},
276 {0x3805, 0x8f},
277 {0x3806, 0x04},
278 {0x3807, 0x47},
279 {0x3808, 0x07},
280 {0x3809, 0x8c},
281 {0x380a, 0x04},
282 {0x380b, 0x44},
283 {0x3810, 0x00},
284 {0x3811, 0x00},
285 {0x3812, 0x00},
286 {0x3813, 0x01},
287 };
288
289 static const char * const ov2740_test_pattern_menu[] = {
290 "Disabled",
291 "Color Bar",
292 "Top-Bottom Darker Color Bar",
293 "Right-Left Darker Color Bar",
294 "Bottom-Top Darker Color Bar",
295 };
296
297 static const s64 link_freq_menu_items[] = {
298 OV2740_LINK_FREQ_360MHZ,
299 };
300
301 static const struct ov2740_link_freq_config link_freq_configs[] = {
302 [OV2740_LINK_FREQ_360MHZ_INDEX] = {
303 .reg_list = {
304 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
305 .regs = mipi_data_rate_720mbps,
306 }
307 },
308 };
309
310 static const struct ov2740_mode supported_modes[] = {
311 {
312 .width = 1932,
313 .height = 1092,
314 .hts = 1080,
315 .vts_def = OV2740_VTS_DEF,
316 .vts_min = OV2740_VTS_MIN,
317 .reg_list = {
318 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs),
319 .regs = mode_1932x1092_regs,
320 },
321 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX,
322 },
323 };
324
325 struct ov2740 {
326 struct v4l2_subdev sd;
327 struct media_pad pad;
328 struct v4l2_ctrl_handler ctrl_handler;
329
330 /* V4L2 Controls */
331 struct v4l2_ctrl *link_freq;
332 struct v4l2_ctrl *pixel_rate;
333 struct v4l2_ctrl *vblank;
334 struct v4l2_ctrl *hblank;
335 struct v4l2_ctrl *exposure;
336
337 /* Current mode */
338 const struct ov2740_mode *cur_mode;
339
340 /* To serialize asynchronus callbacks */
341 struct mutex mutex;
342
343 /* Streaming on/off */
344 bool streaming;
345
346 /* NVM data inforamtion */
347 struct nvm_data *nvm;
348
349 /* True if the device has been identified */
350 bool identified;
351 };
352
to_ov2740(struct v4l2_subdev * subdev)353 static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev)
354 {
355 return container_of(subdev, struct ov2740, sd);
356 }
357
to_pixel_rate(u32 f_index)358 static u64 to_pixel_rate(u32 f_index)
359 {
360 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES;
361
362 do_div(pixel_rate, OV2740_RGB_DEPTH);
363
364 return pixel_rate;
365 }
366
to_pixels_per_line(u32 hts,u32 f_index)367 static u64 to_pixels_per_line(u32 hts, u32 f_index)
368 {
369 u64 ppl = hts * to_pixel_rate(f_index);
370
371 do_div(ppl, OV2740_SCLK);
372
373 return ppl;
374 }
375
ov2740_read_reg(struct ov2740 * ov2740,u16 reg,u16 len,u32 * val)376 static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val)
377 {
378 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
379 struct i2c_msg msgs[2];
380 u8 addr_buf[2];
381 u8 data_buf[4] = {0};
382 int ret = 0;
383
384 if (len > sizeof(data_buf))
385 return -EINVAL;
386
387 put_unaligned_be16(reg, addr_buf);
388 msgs[0].addr = client->addr;
389 msgs[0].flags = 0;
390 msgs[0].len = sizeof(addr_buf);
391 msgs[0].buf = addr_buf;
392 msgs[1].addr = client->addr;
393 msgs[1].flags = I2C_M_RD;
394 msgs[1].len = len;
395 msgs[1].buf = &data_buf[sizeof(data_buf) - len];
396
397 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
398 if (ret != ARRAY_SIZE(msgs))
399 return ret < 0 ? ret : -EIO;
400
401 *val = get_unaligned_be32(data_buf);
402
403 return 0;
404 }
405
ov2740_write_reg(struct ov2740 * ov2740,u16 reg,u16 len,u32 val)406 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val)
407 {
408 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
409 u8 buf[6];
410 int ret = 0;
411
412 if (len > 4)
413 return -EINVAL;
414
415 put_unaligned_be16(reg, buf);
416 put_unaligned_be32(val << 8 * (4 - len), buf + 2);
417
418 ret = i2c_master_send(client, buf, len + 2);
419 if (ret != len + 2)
420 return ret < 0 ? ret : -EIO;
421
422 return 0;
423 }
424
ov2740_write_reg_list(struct ov2740 * ov2740,const struct ov2740_reg_list * r_list)425 static int ov2740_write_reg_list(struct ov2740 *ov2740,
426 const struct ov2740_reg_list *r_list)
427 {
428 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
429 unsigned int i;
430 int ret = 0;
431
432 for (i = 0; i < r_list->num_of_regs; i++) {
433 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1,
434 r_list->regs[i].val);
435 if (ret) {
436 dev_err_ratelimited(&client->dev,
437 "write reg 0x%4.4x return err = %d",
438 r_list->regs[i].address, ret);
439 return ret;
440 }
441 }
442
443 return 0;
444 }
445
ov2740_identify_module(struct ov2740 * ov2740)446 static int ov2740_identify_module(struct ov2740 *ov2740)
447 {
448 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
449 int ret;
450 u32 val;
451
452 if (ov2740->identified)
453 return 0;
454
455 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val);
456 if (ret)
457 return ret;
458
459 if (val != OV2740_CHIP_ID) {
460 dev_err(&client->dev, "chip id mismatch: %x!=%x",
461 OV2740_CHIP_ID, val);
462 return -ENXIO;
463 }
464
465 ov2740->identified = true;
466
467 return 0;
468 }
469
ov2740_update_digital_gain(struct ov2740 * ov2740,u32 d_gain)470 static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain)
471 {
472 int ret = 0;
473
474 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
475 OV2740_GROUP_HOLD_START);
476 if (ret)
477 return ret;
478
479 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain);
480 if (ret)
481 return ret;
482
483 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain);
484 if (ret)
485 return ret;
486
487 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain);
488 if (ret)
489 return ret;
490
491 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
492 OV2740_GROUP_HOLD_END);
493 if (ret)
494 return ret;
495
496 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
497 OV2740_GROUP_HOLD_LAUNCH);
498 return ret;
499 }
500
ov2740_test_pattern(struct ov2740 * ov2740,u32 pattern)501 static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern)
502 {
503 if (pattern)
504 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT |
505 OV2740_TEST_PATTERN_ENABLE;
506
507 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern);
508 }
509
ov2740_set_ctrl(struct v4l2_ctrl * ctrl)510 static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl)
511 {
512 struct ov2740 *ov2740 = container_of(ctrl->handler,
513 struct ov2740, ctrl_handler);
514 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
515 s64 exposure_max;
516 int ret = 0;
517
518 /* Propagate change of current control to all related controls */
519 if (ctrl->id == V4L2_CID_VBLANK) {
520 /* Update max exposure while meeting expected vblanking */
521 exposure_max = ov2740->cur_mode->height + ctrl->val -
522 OV2740_EXPOSURE_MAX_MARGIN;
523 __v4l2_ctrl_modify_range(ov2740->exposure,
524 ov2740->exposure->minimum,
525 exposure_max, ov2740->exposure->step,
526 exposure_max);
527 }
528
529 /* V4L2 controls values will be applied only when power is already up */
530 if (!pm_runtime_get_if_in_use(&client->dev))
531 return 0;
532
533 switch (ctrl->id) {
534 case V4L2_CID_ANALOGUE_GAIN:
535 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2,
536 ctrl->val);
537 break;
538
539 case V4L2_CID_DIGITAL_GAIN:
540 ret = ov2740_update_digital_gain(ov2740, ctrl->val);
541 break;
542
543 case V4L2_CID_EXPOSURE:
544 /* 4 least significant bits of expsoure are fractional part */
545 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3,
546 ctrl->val << 4);
547 break;
548
549 case V4L2_CID_VBLANK:
550 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2,
551 ov2740->cur_mode->height + ctrl->val);
552 break;
553
554 case V4L2_CID_TEST_PATTERN:
555 ret = ov2740_test_pattern(ov2740, ctrl->val);
556 break;
557
558 default:
559 ret = -EINVAL;
560 break;
561 }
562
563 pm_runtime_put(&client->dev);
564
565 return ret;
566 }
567
568 static const struct v4l2_ctrl_ops ov2740_ctrl_ops = {
569 .s_ctrl = ov2740_set_ctrl,
570 };
571
ov2740_init_controls(struct ov2740 * ov2740)572 static int ov2740_init_controls(struct ov2740 *ov2740)
573 {
574 struct v4l2_ctrl_handler *ctrl_hdlr;
575 const struct ov2740_mode *cur_mode;
576 s64 exposure_max, h_blank, pixel_rate;
577 u32 vblank_min, vblank_max, vblank_default;
578 int size;
579 int ret = 0;
580
581 ctrl_hdlr = &ov2740->ctrl_handler;
582 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
583 if (ret)
584 return ret;
585
586 ctrl_hdlr->lock = &ov2740->mutex;
587 cur_mode = ov2740->cur_mode;
588 size = ARRAY_SIZE(link_freq_menu_items);
589
590 ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops,
591 V4L2_CID_LINK_FREQ,
592 size - 1, 0,
593 link_freq_menu_items);
594 if (ov2740->link_freq)
595 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
596
597 pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX);
598 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
599 V4L2_CID_PIXEL_RATE, 0,
600 pixel_rate, 1, pixel_rate);
601
602 vblank_min = cur_mode->vts_min - cur_mode->height;
603 vblank_max = OV2740_VTS_MAX - cur_mode->height;
604 vblank_default = cur_mode->vts_def - cur_mode->height;
605 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
606 V4L2_CID_VBLANK, vblank_min,
607 vblank_max, 1, vblank_default);
608
609 h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index);
610 h_blank -= cur_mode->width;
611 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
612 V4L2_CID_HBLANK, h_blank, h_blank, 1,
613 h_blank);
614 if (ov2740->hblank)
615 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
616
617 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
618 OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX,
619 OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN);
620 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
621 OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX,
622 OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT);
623 exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN;
624 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
625 V4L2_CID_EXPOSURE,
626 OV2740_EXPOSURE_MIN, exposure_max,
627 OV2740_EXPOSURE_STEP,
628 exposure_max);
629 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops,
630 V4L2_CID_TEST_PATTERN,
631 ARRAY_SIZE(ov2740_test_pattern_menu) - 1,
632 0, 0, ov2740_test_pattern_menu);
633 if (ctrl_hdlr->error)
634 return ctrl_hdlr->error;
635
636 ov2740->sd.ctrl_handler = ctrl_hdlr;
637
638 return 0;
639 }
640
ov2740_update_pad_format(const struct ov2740_mode * mode,struct v4l2_mbus_framefmt * fmt)641 static void ov2740_update_pad_format(const struct ov2740_mode *mode,
642 struct v4l2_mbus_framefmt *fmt)
643 {
644 fmt->width = mode->width;
645 fmt->height = mode->height;
646 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
647 fmt->field = V4L2_FIELD_NONE;
648 }
649
ov2740_load_otp_data(struct nvm_data * nvm)650 static int ov2740_load_otp_data(struct nvm_data *nvm)
651 {
652 struct i2c_client *client;
653 struct ov2740 *ov2740;
654 u32 isp_ctrl00 = 0;
655 u32 isp_ctrl01 = 0;
656 int ret;
657
658 if (!nvm)
659 return -EINVAL;
660
661 if (nvm->nvm_buffer)
662 return 0;
663
664 client = nvm->client;
665 ov2740 = to_ov2740(i2c_get_clientdata(client));
666
667 nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL);
668 if (!nvm->nvm_buffer)
669 return -ENOMEM;
670
671 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00);
672 if (ret) {
673 dev_err(&client->dev, "failed to read ISP CTRL00\n");
674 goto err;
675 }
676
677 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01);
678 if (ret) {
679 dev_err(&client->dev, "failed to read ISP CTRL01\n");
680 goto err;
681 }
682
683 /* Clear bit 5 of ISP CTRL00 */
684 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1,
685 isp_ctrl00 & ~BIT(5));
686 if (ret) {
687 dev_err(&client->dev, "failed to set ISP CTRL00\n");
688 goto err;
689 }
690
691 /* Clear bit 7 of ISP CTRL01 */
692 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1,
693 isp_ctrl01 & ~BIT(7));
694 if (ret) {
695 dev_err(&client->dev, "failed to set ISP CTRL01\n");
696 goto err;
697 }
698
699 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
700 OV2740_MODE_STREAMING);
701 if (ret) {
702 dev_err(&client->dev, "failed to set streaming mode\n");
703 goto err;
704 }
705
706 /*
707 * Users are not allowed to access OTP-related registers and memory
708 * during the 20 ms period after streaming starts (0x100 = 0x01).
709 */
710 msleep(20);
711
712 ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER,
713 nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE);
714 if (ret) {
715 dev_err(&client->dev, "failed to read OTP data, ret %d\n", ret);
716 goto err;
717 }
718
719 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
720 OV2740_MODE_STANDBY);
721 if (ret) {
722 dev_err(&client->dev, "failed to set streaming mode\n");
723 goto err;
724 }
725
726 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01);
727 if (ret) {
728 dev_err(&client->dev, "failed to set ISP CTRL01\n");
729 goto err;
730 }
731
732 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00);
733 if (ret) {
734 dev_err(&client->dev, "failed to set ISP CTRL00\n");
735 goto err;
736 }
737
738 return 0;
739 err:
740 kfree(nvm->nvm_buffer);
741 nvm->nvm_buffer = NULL;
742
743 return ret;
744 }
745
ov2740_start_streaming(struct ov2740 * ov2740)746 static int ov2740_start_streaming(struct ov2740 *ov2740)
747 {
748 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
749 struct nvm_data *nvm = ov2740->nvm;
750 const struct ov2740_reg_list *reg_list;
751 int link_freq_index;
752 int ret = 0;
753
754 ret = ov2740_identify_module(ov2740);
755 if (ret)
756 return ret;
757
758 ov2740_load_otp_data(nvm);
759
760 link_freq_index = ov2740->cur_mode->link_freq_index;
761 reg_list = &link_freq_configs[link_freq_index].reg_list;
762 ret = ov2740_write_reg_list(ov2740, reg_list);
763 if (ret) {
764 dev_err(&client->dev, "failed to set plls");
765 return ret;
766 }
767
768 reg_list = &ov2740->cur_mode->reg_list;
769 ret = ov2740_write_reg_list(ov2740, reg_list);
770 if (ret) {
771 dev_err(&client->dev, "failed to set mode");
772 return ret;
773 }
774
775 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler);
776 if (ret)
777 return ret;
778
779 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
780 OV2740_MODE_STREAMING);
781 if (ret)
782 dev_err(&client->dev, "failed to start streaming");
783
784 return ret;
785 }
786
ov2740_stop_streaming(struct ov2740 * ov2740)787 static void ov2740_stop_streaming(struct ov2740 *ov2740)
788 {
789 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
790
791 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
792 OV2740_MODE_STANDBY))
793 dev_err(&client->dev, "failed to stop streaming");
794 }
795
ov2740_set_stream(struct v4l2_subdev * sd,int enable)796 static int ov2740_set_stream(struct v4l2_subdev *sd, int enable)
797 {
798 struct ov2740 *ov2740 = to_ov2740(sd);
799 struct i2c_client *client = v4l2_get_subdevdata(sd);
800 int ret = 0;
801
802 if (ov2740->streaming == enable)
803 return 0;
804
805 mutex_lock(&ov2740->mutex);
806 if (enable) {
807 ret = pm_runtime_resume_and_get(&client->dev);
808 if (ret < 0) {
809 mutex_unlock(&ov2740->mutex);
810 return ret;
811 }
812
813 ret = ov2740_start_streaming(ov2740);
814 if (ret) {
815 enable = 0;
816 ov2740_stop_streaming(ov2740);
817 pm_runtime_put(&client->dev);
818 }
819 } else {
820 ov2740_stop_streaming(ov2740);
821 pm_runtime_put(&client->dev);
822 }
823
824 ov2740->streaming = enable;
825 mutex_unlock(&ov2740->mutex);
826
827 return ret;
828 }
829
ov2740_suspend(struct device * dev)830 static int __maybe_unused ov2740_suspend(struct device *dev)
831 {
832 struct v4l2_subdev *sd = dev_get_drvdata(dev);
833 struct ov2740 *ov2740 = to_ov2740(sd);
834
835 mutex_lock(&ov2740->mutex);
836 if (ov2740->streaming)
837 ov2740_stop_streaming(ov2740);
838
839 mutex_unlock(&ov2740->mutex);
840
841 return 0;
842 }
843
ov2740_resume(struct device * dev)844 static int __maybe_unused ov2740_resume(struct device *dev)
845 {
846 struct v4l2_subdev *sd = dev_get_drvdata(dev);
847 struct ov2740 *ov2740 = to_ov2740(sd);
848 int ret = 0;
849
850 mutex_lock(&ov2740->mutex);
851 if (!ov2740->streaming)
852 goto exit;
853
854 ret = ov2740_start_streaming(ov2740);
855 if (ret) {
856 ov2740->streaming = false;
857 ov2740_stop_streaming(ov2740);
858 }
859
860 exit:
861 mutex_unlock(&ov2740->mutex);
862 return ret;
863 }
864
ov2740_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)865 static int ov2740_set_format(struct v4l2_subdev *sd,
866 struct v4l2_subdev_state *sd_state,
867 struct v4l2_subdev_format *fmt)
868 {
869 struct ov2740 *ov2740 = to_ov2740(sd);
870 const struct ov2740_mode *mode;
871 s32 vblank_def, h_blank;
872
873 mode = v4l2_find_nearest_size(supported_modes,
874 ARRAY_SIZE(supported_modes), width,
875 height, fmt->format.width,
876 fmt->format.height);
877
878 mutex_lock(&ov2740->mutex);
879 ov2740_update_pad_format(mode, &fmt->format);
880 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
881 *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format;
882 } else {
883 ov2740->cur_mode = mode;
884 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index);
885 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate,
886 to_pixel_rate(mode->link_freq_index));
887
888 /* Update limits and set FPS to default */
889 vblank_def = mode->vts_def - mode->height;
890 __v4l2_ctrl_modify_range(ov2740->vblank,
891 mode->vts_min - mode->height,
892 OV2740_VTS_MAX - mode->height, 1,
893 vblank_def);
894 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def);
895 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
896 mode->width;
897 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1,
898 h_blank);
899 }
900 mutex_unlock(&ov2740->mutex);
901
902 return 0;
903 }
904
ov2740_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)905 static int ov2740_get_format(struct v4l2_subdev *sd,
906 struct v4l2_subdev_state *sd_state,
907 struct v4l2_subdev_format *fmt)
908 {
909 struct ov2740 *ov2740 = to_ov2740(sd);
910
911 mutex_lock(&ov2740->mutex);
912 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
913 fmt->format = *v4l2_subdev_get_try_format(&ov2740->sd,
914 sd_state,
915 fmt->pad);
916 else
917 ov2740_update_pad_format(ov2740->cur_mode, &fmt->format);
918
919 mutex_unlock(&ov2740->mutex);
920
921 return 0;
922 }
923
ov2740_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)924 static int ov2740_enum_mbus_code(struct v4l2_subdev *sd,
925 struct v4l2_subdev_state *sd_state,
926 struct v4l2_subdev_mbus_code_enum *code)
927 {
928 if (code->index > 0)
929 return -EINVAL;
930
931 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
932
933 return 0;
934 }
935
ov2740_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)936 static int ov2740_enum_frame_size(struct v4l2_subdev *sd,
937 struct v4l2_subdev_state *sd_state,
938 struct v4l2_subdev_frame_size_enum *fse)
939 {
940 if (fse->index >= ARRAY_SIZE(supported_modes))
941 return -EINVAL;
942
943 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
944 return -EINVAL;
945
946 fse->min_width = supported_modes[fse->index].width;
947 fse->max_width = fse->min_width;
948 fse->min_height = supported_modes[fse->index].height;
949 fse->max_height = fse->min_height;
950
951 return 0;
952 }
953
ov2740_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)954 static int ov2740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
955 {
956 struct ov2740 *ov2740 = to_ov2740(sd);
957
958 mutex_lock(&ov2740->mutex);
959 ov2740_update_pad_format(&supported_modes[0],
960 v4l2_subdev_get_try_format(sd, fh->state, 0));
961 mutex_unlock(&ov2740->mutex);
962
963 return 0;
964 }
965
966 static const struct v4l2_subdev_video_ops ov2740_video_ops = {
967 .s_stream = ov2740_set_stream,
968 };
969
970 static const struct v4l2_subdev_pad_ops ov2740_pad_ops = {
971 .set_fmt = ov2740_set_format,
972 .get_fmt = ov2740_get_format,
973 .enum_mbus_code = ov2740_enum_mbus_code,
974 .enum_frame_size = ov2740_enum_frame_size,
975 };
976
977 static const struct v4l2_subdev_ops ov2740_subdev_ops = {
978 .video = &ov2740_video_ops,
979 .pad = &ov2740_pad_ops,
980 };
981
982 static const struct media_entity_operations ov2740_subdev_entity_ops = {
983 .link_validate = v4l2_subdev_link_validate,
984 };
985
986 static const struct v4l2_subdev_internal_ops ov2740_internal_ops = {
987 .open = ov2740_open,
988 };
989
ov2740_check_hwcfg(struct device * dev)990 static int ov2740_check_hwcfg(struct device *dev)
991 {
992 struct fwnode_handle *ep;
993 struct fwnode_handle *fwnode = dev_fwnode(dev);
994 struct v4l2_fwnode_endpoint bus_cfg = {
995 .bus_type = V4L2_MBUS_CSI2_DPHY
996 };
997 u32 mclk;
998 int ret;
999 unsigned int i, j;
1000
1001 if (!fwnode)
1002 return -ENXIO;
1003
1004 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
1005 if (ret)
1006 return ret;
1007
1008 if (mclk != OV2740_MCLK) {
1009 dev_err(dev, "external clock %d is not supported", mclk);
1010 return -EINVAL;
1011 }
1012
1013 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1014 if (!ep)
1015 return -ENXIO;
1016
1017 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1018 fwnode_handle_put(ep);
1019 if (ret)
1020 return ret;
1021
1022 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) {
1023 dev_err(dev, "number of CSI2 data lanes %d is not supported",
1024 bus_cfg.bus.mipi_csi2.num_data_lanes);
1025 ret = -EINVAL;
1026 goto check_hwcfg_error;
1027 }
1028
1029 if (!bus_cfg.nr_of_link_frequencies) {
1030 dev_err(dev, "no link frequencies defined");
1031 ret = -EINVAL;
1032 goto check_hwcfg_error;
1033 }
1034
1035 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1036 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1037 if (link_freq_menu_items[i] ==
1038 bus_cfg.link_frequencies[j])
1039 break;
1040 }
1041
1042 if (j == bus_cfg.nr_of_link_frequencies) {
1043 dev_err(dev, "no link frequency %lld supported",
1044 link_freq_menu_items[i]);
1045 ret = -EINVAL;
1046 goto check_hwcfg_error;
1047 }
1048 }
1049
1050 check_hwcfg_error:
1051 v4l2_fwnode_endpoint_free(&bus_cfg);
1052
1053 return ret;
1054 }
1055
ov2740_remove(struct i2c_client * client)1056 static void ov2740_remove(struct i2c_client *client)
1057 {
1058 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1059 struct ov2740 *ov2740 = to_ov2740(sd);
1060
1061 v4l2_async_unregister_subdev(sd);
1062 media_entity_cleanup(&sd->entity);
1063 v4l2_ctrl_handler_free(sd->ctrl_handler);
1064 pm_runtime_disable(&client->dev);
1065 mutex_destroy(&ov2740->mutex);
1066 }
1067
ov2740_nvmem_read(void * priv,unsigned int off,void * val,size_t count)1068 static int ov2740_nvmem_read(void *priv, unsigned int off, void *val,
1069 size_t count)
1070 {
1071 struct nvm_data *nvm = priv;
1072 struct v4l2_subdev *sd = i2c_get_clientdata(nvm->client);
1073 struct device *dev = &nvm->client->dev;
1074 struct ov2740 *ov2740 = to_ov2740(sd);
1075 int ret = 0;
1076
1077 mutex_lock(&ov2740->mutex);
1078
1079 if (nvm->nvm_buffer) {
1080 memcpy(val, nvm->nvm_buffer + off, count);
1081 goto exit;
1082 }
1083
1084 ret = pm_runtime_resume_and_get(dev);
1085 if (ret < 0) {
1086 goto exit;
1087 }
1088
1089 ret = ov2740_load_otp_data(nvm);
1090 if (!ret)
1091 memcpy(val, nvm->nvm_buffer + off, count);
1092
1093 pm_runtime_put(dev);
1094 exit:
1095 mutex_unlock(&ov2740->mutex);
1096 return ret;
1097 }
1098
ov2740_register_nvmem(struct i2c_client * client,struct ov2740 * ov2740)1099 static int ov2740_register_nvmem(struct i2c_client *client,
1100 struct ov2740 *ov2740)
1101 {
1102 struct nvm_data *nvm;
1103 struct regmap_config regmap_config = { };
1104 struct nvmem_config nvmem_config = { };
1105 struct regmap *regmap;
1106 struct device *dev = &client->dev;
1107 int ret;
1108
1109 nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL);
1110 if (!nvm)
1111 return -ENOMEM;
1112
1113 regmap_config.val_bits = 8;
1114 regmap_config.reg_bits = 16;
1115 regmap_config.disable_locking = true;
1116 regmap = devm_regmap_init_i2c(client, ®map_config);
1117 if (IS_ERR(regmap))
1118 return PTR_ERR(regmap);
1119
1120 nvm->regmap = regmap;
1121 nvm->client = client;
1122
1123 nvmem_config.name = dev_name(dev);
1124 nvmem_config.dev = dev;
1125 nvmem_config.read_only = true;
1126 nvmem_config.root_only = true;
1127 nvmem_config.owner = THIS_MODULE;
1128 nvmem_config.compat = true;
1129 nvmem_config.base_dev = dev;
1130 nvmem_config.reg_read = ov2740_nvmem_read;
1131 nvmem_config.reg_write = NULL;
1132 nvmem_config.priv = nvm;
1133 nvmem_config.stride = 1;
1134 nvmem_config.word_size = 1;
1135 nvmem_config.size = CUSTOMER_USE_OTP_SIZE;
1136
1137 nvm->nvmem = devm_nvmem_register(dev, &nvmem_config);
1138
1139 ret = PTR_ERR_OR_ZERO(nvm->nvmem);
1140 if (!ret)
1141 ov2740->nvm = nvm;
1142
1143 return ret;
1144 }
1145
ov2740_probe(struct i2c_client * client)1146 static int ov2740_probe(struct i2c_client *client)
1147 {
1148 struct ov2740 *ov2740;
1149 int ret = 0;
1150 bool full_power;
1151
1152 ret = ov2740_check_hwcfg(&client->dev);
1153 if (ret) {
1154 dev_err(&client->dev, "failed to check HW configuration: %d",
1155 ret);
1156 return ret;
1157 }
1158
1159 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL);
1160 if (!ov2740)
1161 return -ENOMEM;
1162
1163 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops);
1164 full_power = acpi_dev_state_d0(&client->dev);
1165 if (full_power) {
1166 ret = ov2740_identify_module(ov2740);
1167 if (ret) {
1168 dev_err(&client->dev, "failed to find sensor: %d", ret);
1169 return ret;
1170 }
1171 }
1172
1173 mutex_init(&ov2740->mutex);
1174 ov2740->cur_mode = &supported_modes[0];
1175 ret = ov2740_init_controls(ov2740);
1176 if (ret) {
1177 dev_err(&client->dev, "failed to init controls: %d", ret);
1178 goto probe_error_v4l2_ctrl_handler_free;
1179 }
1180
1181 ov2740->sd.internal_ops = &ov2740_internal_ops;
1182 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1183 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops;
1184 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1185 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE;
1186 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad);
1187 if (ret) {
1188 dev_err(&client->dev, "failed to init entity pads: %d", ret);
1189 goto probe_error_v4l2_ctrl_handler_free;
1190 }
1191
1192 ret = v4l2_async_register_subdev_sensor(&ov2740->sd);
1193 if (ret < 0) {
1194 dev_err(&client->dev, "failed to register V4L2 subdev: %d",
1195 ret);
1196 goto probe_error_media_entity_cleanup;
1197 }
1198
1199 ret = ov2740_register_nvmem(client, ov2740);
1200 if (ret)
1201 dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret);
1202
1203 /* Set the device's state to active if it's in D0 state. */
1204 if (full_power)
1205 pm_runtime_set_active(&client->dev);
1206 pm_runtime_enable(&client->dev);
1207 pm_runtime_idle(&client->dev);
1208
1209 return 0;
1210
1211 probe_error_media_entity_cleanup:
1212 media_entity_cleanup(&ov2740->sd.entity);
1213
1214 probe_error_v4l2_ctrl_handler_free:
1215 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler);
1216 mutex_destroy(&ov2740->mutex);
1217
1218 return ret;
1219 }
1220
1221 static const struct dev_pm_ops ov2740_pm_ops = {
1222 SET_SYSTEM_SLEEP_PM_OPS(ov2740_suspend, ov2740_resume)
1223 };
1224
1225 static const struct acpi_device_id ov2740_acpi_ids[] = {
1226 {"INT3474"},
1227 {}
1228 };
1229
1230 MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids);
1231
1232 static struct i2c_driver ov2740_i2c_driver = {
1233 .driver = {
1234 .name = "ov2740",
1235 .pm = &ov2740_pm_ops,
1236 .acpi_match_table = ov2740_acpi_ids,
1237 },
1238 .probe_new = ov2740_probe,
1239 .remove = ov2740_remove,
1240 .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE,
1241 };
1242
1243 module_i2c_driver(ov2740_i2c_driver);
1244
1245 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
1246 MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>");
1247 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
1248 MODULE_DESCRIPTION("OmniVision OV2740 sensor driver");
1249 MODULE_LICENSE("GPL v2");
1250
