1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
4 *
5 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/io.h>
13 #include <linux/iio/iio.h>
14 #include <linux/module.h>
15 #include <linux/nvmem-consumer.h>
16 #include <linux/interrupt.h>
17 #include <linux/of.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/mfd/syscon.h>
24
25 #define MESON_SAR_ADC_REG0 0x00
26 #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
27 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
28 #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
29 #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
30 #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
31 #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
32 #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
33 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
34 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
35 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
36 #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
37 #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
38 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
39 #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
40 #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
41 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
42 #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
43 #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
44 #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
45 #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
46
47 #define MESON_SAR_ADC_CHAN_LIST 0x04
48 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
49 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
50 (GENMASK(2, 0) << ((_chan) * 3))
51
52 #define MESON_SAR_ADC_AVG_CNTL 0x08
53 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
54 (16 + ((_chan) * 2))
55 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
56 (GENMASK(17, 16) << ((_chan) * 2))
57 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
58 (0 + ((_chan) * 2))
59 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
60 (GENMASK(1, 0) << ((_chan) * 2))
61
62 #define MESON_SAR_ADC_REG3 0x0c
63 #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
64 #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
65 #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
66 #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
67 #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
68 #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
69 #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
70 #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
71 #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
72 #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
73 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
74 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
75 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
76 #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
77
78 #define MESON_SAR_ADC_DELAY 0x10
79 #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
80 #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
81 #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
82 #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
83 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
84 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
85
86 #define MESON_SAR_ADC_LAST_RD 0x14
87 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
88 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
89
90 #define MESON_SAR_ADC_FIFO_RD 0x18
91 #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
92 #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
93
94 #define MESON_SAR_ADC_AUX_SW 0x1c
95 #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \
96 (8 + (((_chan) - 2) * 3))
97 #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
98 #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
99 #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
100 #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
101 #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
102 #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
103 #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
104
105 #define MESON_SAR_ADC_CHAN_10_SW 0x20
106 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
107 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
108 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
109 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
110 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
111 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
112 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
113 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
114 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
115 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
116 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
117 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
118 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
119 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
120 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
121 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
122
123 #define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
124 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
125 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
126 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
127 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
128 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
129 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
130 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
131 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
132 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
133 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
134 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
135 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
136 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
137 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
138 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
139 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
140 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
141
142 #define MESON_SAR_ADC_DELTA_10 0x28
143 #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
144 #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
145 #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
146 #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
147 #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
148 #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
149 #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
150
151 /*
152 * NOTE: registers from here are undocumented (the vendor Linux kernel driver
153 * and u-boot source served as reference). These only seem to be relevant on
154 * GXBB and newer.
155 */
156 #define MESON_SAR_ADC_REG11 0x2c
157 #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
158
159 #define MESON_SAR_ADC_REG13 0x34
160 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
161
162 #define MESON_SAR_ADC_MAX_FIFO_SIZE 32
163 #define MESON_SAR_ADC_TIMEOUT 100 /* ms */
164 #define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL 6
165 #define MESON_SAR_ADC_TEMP_OFFSET 27
166
167 /* temperature sensor calibration information in eFuse */
168 #define MESON_SAR_ADC_EFUSE_BYTES 4
169 #define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL GENMASK(6, 0)
170 #define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED BIT(7)
171
172 #define MESON_HHI_DPLL_TOP_0 0x318
173 #define MESON_HHI_DPLL_TOP_0_TSC_BIT4 BIT(9)
174
175 /* for use with IIO_VAL_INT_PLUS_MICRO */
176 #define MILLION 1000000
177
178 #define MESON_SAR_ADC_CHAN(_chan) { \
179 .type = IIO_VOLTAGE, \
180 .indexed = 1, \
181 .channel = _chan, \
182 .address = _chan, \
183 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
184 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
185 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
186 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
187 BIT(IIO_CHAN_INFO_CALIBSCALE), \
188 .datasheet_name = "SAR_ADC_CH"#_chan, \
189 }
190
191 #define MESON_SAR_ADC_TEMP_CHAN(_chan) { \
192 .type = IIO_TEMP, \
193 .channel = _chan, \
194 .address = MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL, \
195 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
196 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
197 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \
198 BIT(IIO_CHAN_INFO_SCALE), \
199 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
200 BIT(IIO_CHAN_INFO_CALIBSCALE), \
201 .datasheet_name = "TEMP_SENSOR", \
202 }
203
204 static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
205 MESON_SAR_ADC_CHAN(0),
206 MESON_SAR_ADC_CHAN(1),
207 MESON_SAR_ADC_CHAN(2),
208 MESON_SAR_ADC_CHAN(3),
209 MESON_SAR_ADC_CHAN(4),
210 MESON_SAR_ADC_CHAN(5),
211 MESON_SAR_ADC_CHAN(6),
212 MESON_SAR_ADC_CHAN(7),
213 IIO_CHAN_SOFT_TIMESTAMP(8),
214 };
215
216 static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = {
217 MESON_SAR_ADC_CHAN(0),
218 MESON_SAR_ADC_CHAN(1),
219 MESON_SAR_ADC_CHAN(2),
220 MESON_SAR_ADC_CHAN(3),
221 MESON_SAR_ADC_CHAN(4),
222 MESON_SAR_ADC_CHAN(5),
223 MESON_SAR_ADC_CHAN(6),
224 MESON_SAR_ADC_CHAN(7),
225 MESON_SAR_ADC_TEMP_CHAN(8),
226 IIO_CHAN_SOFT_TIMESTAMP(9),
227 };
228
229 enum meson_sar_adc_avg_mode {
230 NO_AVERAGING = 0x0,
231 MEAN_AVERAGING = 0x1,
232 MEDIAN_AVERAGING = 0x2,
233 };
234
235 enum meson_sar_adc_num_samples {
236 ONE_SAMPLE = 0x0,
237 TWO_SAMPLES = 0x1,
238 FOUR_SAMPLES = 0x2,
239 EIGHT_SAMPLES = 0x3,
240 };
241
242 enum meson_sar_adc_chan7_mux_sel {
243 CHAN7_MUX_VSS = 0x0,
244 CHAN7_MUX_VDD_DIV4 = 0x1,
245 CHAN7_MUX_VDD_DIV2 = 0x2,
246 CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
247 CHAN7_MUX_VDD = 0x4,
248 CHAN7_MUX_CH7_INPUT = 0x7,
249 };
250
251 struct meson_sar_adc_param {
252 bool has_bl30_integration;
253 unsigned long clock_rate;
254 u32 bandgap_reg;
255 unsigned int resolution;
256 const struct regmap_config *regmap_config;
257 u8 temperature_trimming_bits;
258 unsigned int temperature_multiplier;
259 unsigned int temperature_divider;
260 };
261
262 struct meson_sar_adc_data {
263 const struct meson_sar_adc_param *param;
264 const char *name;
265 };
266
267 struct meson_sar_adc_priv {
268 struct regmap *regmap;
269 struct regulator *vref;
270 const struct meson_sar_adc_param *param;
271 struct clk *clkin;
272 struct clk *core_clk;
273 struct clk *adc_sel_clk;
274 struct clk *adc_clk;
275 struct clk_gate clk_gate;
276 struct clk *adc_div_clk;
277 struct clk_divider clk_div;
278 struct completion done;
279 int calibbias;
280 int calibscale;
281 struct regmap *tsc_regmap;
282 bool temperature_sensor_calibrated;
283 u8 temperature_sensor_coefficient;
284 u16 temperature_sensor_adc_val;
285 };
286
287 static const struct regmap_config meson_sar_adc_regmap_config_gxbb = {
288 .reg_bits = 8,
289 .val_bits = 32,
290 .reg_stride = 4,
291 .max_register = MESON_SAR_ADC_REG13,
292 };
293
294 static const struct regmap_config meson_sar_adc_regmap_config_meson8 = {
295 .reg_bits = 8,
296 .val_bits = 32,
297 .reg_stride = 4,
298 .max_register = MESON_SAR_ADC_DELTA_10,
299 };
300
meson_sar_adc_get_fifo_count(struct iio_dev * indio_dev)301 static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
302 {
303 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
304 u32 regval;
305
306 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
307
308 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
309 }
310
meson_sar_adc_calib_val(struct iio_dev * indio_dev,int val)311 static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val)
312 {
313 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
314 int tmp;
315
316 /* use val_calib = scale * val_raw + offset calibration function */
317 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
318
319 return clamp(tmp, 0, (1 << priv->param->resolution) - 1);
320 }
321
meson_sar_adc_wait_busy_clear(struct iio_dev * indio_dev)322 static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
323 {
324 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
325 int val;
326
327 /*
328 * NOTE: we need a small delay before reading the status, otherwise
329 * the sample engine may not have started internally (which would
330 * seem to us that sampling is already finished).
331 */
332 udelay(1);
333 return regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_REG0, val,
334 !FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, val),
335 1, 10000);
336 }
337
meson_sar_adc_read_raw_sample(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val)338 static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
339 const struct iio_chan_spec *chan,
340 int *val)
341 {
342 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
343 struct device *dev = indio_dev->dev.parent;
344 int regval, fifo_chan, fifo_val, count;
345
346 if (!wait_for_completion_timeout(&priv->done,
347 msecs_to_jiffies(MESON_SAR_ADC_TIMEOUT)))
348 return -ETIMEDOUT;
349
350 count = meson_sar_adc_get_fifo_count(indio_dev);
351 if (count != 1) {
352 dev_err(dev, "ADC FIFO has %d element(s) instead of one\n", count);
353 return -EINVAL;
354 }
355
356 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val);
357 fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
358 if (fifo_chan != chan->address) {
359 dev_err(dev, "ADC FIFO entry belongs to channel %d instead of %lu\n",
360 fifo_chan, chan->address);
361 return -EINVAL;
362 }
363
364 fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
365 fifo_val &= GENMASK(priv->param->resolution - 1, 0);
366 *val = meson_sar_adc_calib_val(indio_dev, fifo_val);
367
368 return 0;
369 }
370
meson_sar_adc_set_averaging(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum meson_sar_adc_avg_mode mode,enum meson_sar_adc_num_samples samples)371 static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
372 const struct iio_chan_spec *chan,
373 enum meson_sar_adc_avg_mode mode,
374 enum meson_sar_adc_num_samples samples)
375 {
376 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
377 int val, address = chan->address;
378
379 val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(address);
380 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
381 MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(address),
382 val);
383
384 val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(address);
385 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
386 MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(address), val);
387 }
388
meson_sar_adc_enable_channel(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)389 static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
390 const struct iio_chan_spec *chan)
391 {
392 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
393 u32 regval;
394
395 /*
396 * the SAR ADC engine allows sampling multiple channels at the same
397 * time. to keep it simple we're only working with one *internal*
398 * channel, which starts counting at index 0 (which means: count = 1).
399 */
400 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
401 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
402 MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
403
404 /* map channel index 0 to the channel which we want to read */
405 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
406 chan->address);
407 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
408 MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
409
410 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
411 chan->address);
412 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
413 MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
414 regval);
415
416 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
417 chan->address);
418 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
419 MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
420 regval);
421
422 if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) {
423 if (chan->type == IIO_TEMP)
424 regval = MESON_SAR_ADC_DELTA_10_TEMP_SEL;
425 else
426 regval = 0;
427
428 regmap_update_bits(priv->regmap,
429 MESON_SAR_ADC_DELTA_10,
430 MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval);
431 }
432 }
433
meson_sar_adc_set_chan7_mux(struct iio_dev * indio_dev,enum meson_sar_adc_chan7_mux_sel sel)434 static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
435 enum meson_sar_adc_chan7_mux_sel sel)
436 {
437 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
438 u32 regval;
439
440 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
441 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
442 MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
443
444 usleep_range(10, 20);
445 }
446
meson_sar_adc_start_sample_engine(struct iio_dev * indio_dev)447 static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
448 {
449 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
450
451 reinit_completion(&priv->done);
452
453 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
454 MESON_SAR_ADC_REG0_FIFO_IRQ_EN,
455 MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
456
457 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
458 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
459 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
460
461 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
462 MESON_SAR_ADC_REG0_SAMPLING_START,
463 MESON_SAR_ADC_REG0_SAMPLING_START);
464 }
465
meson_sar_adc_stop_sample_engine(struct iio_dev * indio_dev)466 static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
467 {
468 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
469
470 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
471 MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0);
472
473 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
474 MESON_SAR_ADC_REG0_SAMPLING_STOP,
475 MESON_SAR_ADC_REG0_SAMPLING_STOP);
476
477 /* wait until all modules are stopped */
478 meson_sar_adc_wait_busy_clear(indio_dev);
479
480 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
481 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
482 }
483
meson_sar_adc_lock(struct iio_dev * indio_dev)484 static int meson_sar_adc_lock(struct iio_dev *indio_dev)
485 {
486 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
487 int val, ret;
488
489 mutex_lock(&indio_dev->mlock);
490
491 if (priv->param->has_bl30_integration) {
492 /* prevent BL30 from using the SAR ADC while we are using it */
493 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
494 MESON_SAR_ADC_DELAY_KERNEL_BUSY,
495 MESON_SAR_ADC_DELAY_KERNEL_BUSY);
496
497 udelay(1);
498
499 /*
500 * wait until BL30 releases it's lock (so we can use the SAR
501 * ADC)
502 */
503 ret = regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_DELAY, val,
504 !(val & MESON_SAR_ADC_DELAY_BL30_BUSY),
505 1, 10000);
506 if (ret) {
507 mutex_unlock(&indio_dev->mlock);
508 return ret;
509 }
510 }
511
512 return 0;
513 }
514
meson_sar_adc_unlock(struct iio_dev * indio_dev)515 static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
516 {
517 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
518
519 if (priv->param->has_bl30_integration)
520 /* allow BL30 to use the SAR ADC again */
521 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
522 MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
523
524 mutex_unlock(&indio_dev->mlock);
525 }
526
meson_sar_adc_clear_fifo(struct iio_dev * indio_dev)527 static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
528 {
529 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
530 unsigned int count, tmp;
531
532 for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
533 if (!meson_sar_adc_get_fifo_count(indio_dev))
534 break;
535
536 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
537 }
538 }
539
meson_sar_adc_get_sample(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum meson_sar_adc_avg_mode avg_mode,enum meson_sar_adc_num_samples avg_samples,int * val)540 static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
541 const struct iio_chan_spec *chan,
542 enum meson_sar_adc_avg_mode avg_mode,
543 enum meson_sar_adc_num_samples avg_samples,
544 int *val)
545 {
546 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
547 struct device *dev = indio_dev->dev.parent;
548 int ret;
549
550 if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated)
551 return -ENOTSUPP;
552
553 ret = meson_sar_adc_lock(indio_dev);
554 if (ret)
555 return ret;
556
557 /* clear the FIFO to make sure we're not reading old values */
558 meson_sar_adc_clear_fifo(indio_dev);
559
560 meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
561
562 meson_sar_adc_enable_channel(indio_dev, chan);
563
564 meson_sar_adc_start_sample_engine(indio_dev);
565 ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
566 meson_sar_adc_stop_sample_engine(indio_dev);
567
568 meson_sar_adc_unlock(indio_dev);
569
570 if (ret) {
571 dev_warn(dev, "failed to read sample for channel %lu: %d\n",
572 chan->address, ret);
573 return ret;
574 }
575
576 return IIO_VAL_INT;
577 }
578
meson_sar_adc_iio_info_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long mask)579 static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
580 const struct iio_chan_spec *chan,
581 int *val, int *val2, long mask)
582 {
583 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
584 struct device *dev = indio_dev->dev.parent;
585 int ret;
586
587 switch (mask) {
588 case IIO_CHAN_INFO_RAW:
589 return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
590 ONE_SAMPLE, val);
591
592 case IIO_CHAN_INFO_AVERAGE_RAW:
593 return meson_sar_adc_get_sample(indio_dev, chan,
594 MEAN_AVERAGING, EIGHT_SAMPLES,
595 val);
596
597 case IIO_CHAN_INFO_SCALE:
598 if (chan->type == IIO_VOLTAGE) {
599 ret = regulator_get_voltage(priv->vref);
600 if (ret < 0) {
601 dev_err(dev, "failed to get vref voltage: %d\n", ret);
602 return ret;
603 }
604
605 *val = ret / 1000;
606 *val2 = priv->param->resolution;
607 return IIO_VAL_FRACTIONAL_LOG2;
608 } else if (chan->type == IIO_TEMP) {
609 /* SoC specific multiplier and divider */
610 *val = priv->param->temperature_multiplier;
611 *val2 = priv->param->temperature_divider;
612
613 /* celsius to millicelsius */
614 *val *= 1000;
615
616 return IIO_VAL_FRACTIONAL;
617 } else {
618 return -EINVAL;
619 }
620
621 case IIO_CHAN_INFO_CALIBBIAS:
622 *val = priv->calibbias;
623 return IIO_VAL_INT;
624
625 case IIO_CHAN_INFO_CALIBSCALE:
626 *val = priv->calibscale / MILLION;
627 *val2 = priv->calibscale % MILLION;
628 return IIO_VAL_INT_PLUS_MICRO;
629
630 case IIO_CHAN_INFO_OFFSET:
631 *val = DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET *
632 priv->param->temperature_divider,
633 priv->param->temperature_multiplier);
634 *val -= priv->temperature_sensor_adc_val;
635 return IIO_VAL_INT;
636
637 default:
638 return -EINVAL;
639 }
640 }
641
meson_sar_adc_clk_init(struct iio_dev * indio_dev,void __iomem * base)642 static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
643 void __iomem *base)
644 {
645 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
646 struct device *dev = indio_dev->dev.parent;
647 struct clk_init_data init;
648 const char *clk_parents[1];
649
650 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_div", dev_name(dev));
651 if (!init.name)
652 return -ENOMEM;
653
654 init.flags = 0;
655 init.ops = &clk_divider_ops;
656 clk_parents[0] = __clk_get_name(priv->clkin);
657 init.parent_names = clk_parents;
658 init.num_parents = 1;
659
660 priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
661 priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
662 priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
663 priv->clk_div.hw.init = &init;
664 priv->clk_div.flags = 0;
665
666 priv->adc_div_clk = devm_clk_register(dev, &priv->clk_div.hw);
667 if (WARN_ON(IS_ERR(priv->adc_div_clk)))
668 return PTR_ERR(priv->adc_div_clk);
669
670 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_en", dev_name(dev));
671 if (!init.name)
672 return -ENOMEM;
673
674 init.flags = CLK_SET_RATE_PARENT;
675 init.ops = &clk_gate_ops;
676 clk_parents[0] = __clk_get_name(priv->adc_div_clk);
677 init.parent_names = clk_parents;
678 init.num_parents = 1;
679
680 priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
681 priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);
682 priv->clk_gate.hw.init = &init;
683
684 priv->adc_clk = devm_clk_register(dev, &priv->clk_gate.hw);
685 if (WARN_ON(IS_ERR(priv->adc_clk)))
686 return PTR_ERR(priv->adc_clk);
687
688 return 0;
689 }
690
meson_sar_adc_temp_sensor_init(struct iio_dev * indio_dev)691 static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev)
692 {
693 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
694 u8 *buf, trimming_bits, trimming_mask, upper_adc_val;
695 struct device *dev = indio_dev->dev.parent;
696 struct nvmem_cell *temperature_calib;
697 size_t read_len;
698 int ret;
699
700 temperature_calib = devm_nvmem_cell_get(dev, "temperature_calib");
701 if (IS_ERR(temperature_calib)) {
702 ret = PTR_ERR(temperature_calib);
703
704 /*
705 * leave the temperature sensor disabled if no calibration data
706 * was passed via nvmem-cells.
707 */
708 if (ret == -ENODEV)
709 return 0;
710
711 return dev_err_probe(dev, ret, "failed to get temperature_calib cell\n");
712 }
713
714 priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl");
715 if (IS_ERR(priv->tsc_regmap))
716 return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap),
717 "failed to get amlogic,hhi-sysctrl regmap\n");
718
719 read_len = MESON_SAR_ADC_EFUSE_BYTES;
720 buf = nvmem_cell_read(temperature_calib, &read_len);
721 if (IS_ERR(buf))
722 return dev_err_probe(dev, PTR_ERR(buf), "failed to read temperature_calib cell\n");
723 if (read_len != MESON_SAR_ADC_EFUSE_BYTES) {
724 kfree(buf);
725 return dev_err_probe(dev, -EINVAL, "invalid read size of temperature_calib cell\n");
726 }
727
728 trimming_bits = priv->param->temperature_trimming_bits;
729 trimming_mask = BIT(trimming_bits) - 1;
730
731 priv->temperature_sensor_calibrated =
732 buf[3] & MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED;
733 priv->temperature_sensor_coefficient = buf[2] & trimming_mask;
734
735 upper_adc_val = FIELD_GET(MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL,
736 buf[3]);
737
738 priv->temperature_sensor_adc_val = buf[2];
739 priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE;
740 priv->temperature_sensor_adc_val >>= trimming_bits;
741
742 kfree(buf);
743
744 return 0;
745 }
746
meson_sar_adc_init(struct iio_dev * indio_dev)747 static int meson_sar_adc_init(struct iio_dev *indio_dev)
748 {
749 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
750 struct device *dev = indio_dev->dev.parent;
751 int regval, i, ret;
752
753 /*
754 * make sure we start at CH7 input since the other muxes are only used
755 * for internal calibration.
756 */
757 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
758
759 if (priv->param->has_bl30_integration) {
760 /*
761 * leave sampling delay and the input clocks as configured by
762 * BL30 to make sure BL30 gets the values it expects when
763 * reading the temperature sensor.
764 */
765 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);
766 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
767 return 0;
768 }
769
770 meson_sar_adc_stop_sample_engine(indio_dev);
771
772 /*
773 * disable this bit as seems to be only relevant for Meson6 (based
774 * on the vendor driver), which we don't support at the moment.
775 */
776 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
777 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL, 0);
778
779 /* disable all channels by default */
780 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
781
782 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
783 MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
784 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
785 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
786 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
787
788 /* delay between two samples = (10+1) * 1uS */
789 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
790 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
791 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
792 10));
793 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
794 MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
795 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
796 0));
797
798 /* delay between two samples = (10+1) * 1uS */
799 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
800 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
801 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
802 10));
803 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
804 MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
805 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
806 1));
807
808 /*
809 * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
810 * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
811 */
812 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
813 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
814 MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
815 regval);
816 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
817 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
818 MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
819 regval);
820
821 /*
822 * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
823 * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
824 * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
825 * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
826 */
827 regval = 0;
828 for (i = 2; i <= 7; i++)
829 regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
830 regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
831 regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
832 regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
833
834 if (priv->temperature_sensor_calibrated) {
835 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
836 MESON_SAR_ADC_DELTA_10_TS_REVE1,
837 MESON_SAR_ADC_DELTA_10_TS_REVE1);
838 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
839 MESON_SAR_ADC_DELTA_10_TS_REVE0,
840 MESON_SAR_ADC_DELTA_10_TS_REVE0);
841
842 /*
843 * set bits [3:0] of the TSC (temperature sensor coefficient)
844 * to get the correct values when reading the temperature.
845 */
846 regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK,
847 priv->temperature_sensor_coefficient);
848 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
849 MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval);
850
851 if (priv->param->temperature_trimming_bits == 5) {
852 if (priv->temperature_sensor_coefficient & BIT(4))
853 regval = MESON_HHI_DPLL_TOP_0_TSC_BIT4;
854 else
855 regval = 0;
856
857 /*
858 * bit [4] (the 5th bit when starting to count at 1)
859 * of the TSC is located in the HHI register area.
860 */
861 regmap_update_bits(priv->tsc_regmap,
862 MESON_HHI_DPLL_TOP_0,
863 MESON_HHI_DPLL_TOP_0_TSC_BIT4,
864 regval);
865 }
866 } else {
867 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
868 MESON_SAR_ADC_DELTA_10_TS_REVE1, 0);
869 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
870 MESON_SAR_ADC_DELTA_10_TS_REVE0, 0);
871 }
872
873 ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
874 if (ret)
875 return dev_err_probe(dev, ret, "failed to set adc parent to clkin\n");
876
877 ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate);
878 if (ret)
879 return dev_err_probe(dev, ret, "failed to set adc clock rate\n");
880
881 return 0;
882 }
883
meson_sar_adc_set_bandgap(struct iio_dev * indio_dev,bool on_off)884 static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off)
885 {
886 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
887 const struct meson_sar_adc_param *param = priv->param;
888 u32 enable_mask;
889
890 if (param->bandgap_reg == MESON_SAR_ADC_REG11)
891 enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN;
892 else
893 enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN;
894
895 regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask,
896 on_off ? enable_mask : 0);
897 }
898
meson_sar_adc_hw_enable(struct iio_dev * indio_dev)899 static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
900 {
901 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
902 struct device *dev = indio_dev->dev.parent;
903 int ret;
904 u32 regval;
905
906 ret = meson_sar_adc_lock(indio_dev);
907 if (ret)
908 goto err_lock;
909
910 ret = regulator_enable(priv->vref);
911 if (ret < 0) {
912 dev_err(dev, "failed to enable vref regulator\n");
913 goto err_vref;
914 }
915
916 ret = clk_prepare_enable(priv->core_clk);
917 if (ret) {
918 dev_err(dev, "failed to enable core clk\n");
919 goto err_core_clk;
920 }
921
922 regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
923 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
924 MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
925
926 meson_sar_adc_set_bandgap(indio_dev, true);
927
928 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
929 MESON_SAR_ADC_REG3_ADC_EN,
930 MESON_SAR_ADC_REG3_ADC_EN);
931
932 udelay(5);
933
934 ret = clk_prepare_enable(priv->adc_clk);
935 if (ret) {
936 dev_err(dev, "failed to enable adc clk\n");
937 goto err_adc_clk;
938 }
939
940 meson_sar_adc_unlock(indio_dev);
941
942 return 0;
943
944 err_adc_clk:
945 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
946 MESON_SAR_ADC_REG3_ADC_EN, 0);
947 meson_sar_adc_set_bandgap(indio_dev, false);
948 clk_disable_unprepare(priv->core_clk);
949 err_core_clk:
950 regulator_disable(priv->vref);
951 err_vref:
952 meson_sar_adc_unlock(indio_dev);
953 err_lock:
954 return ret;
955 }
956
meson_sar_adc_hw_disable(struct iio_dev * indio_dev)957 static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
958 {
959 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
960 int ret;
961
962 ret = meson_sar_adc_lock(indio_dev);
963 if (ret)
964 return ret;
965
966 clk_disable_unprepare(priv->adc_clk);
967
968 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
969 MESON_SAR_ADC_REG3_ADC_EN, 0);
970
971 meson_sar_adc_set_bandgap(indio_dev, false);
972
973 clk_disable_unprepare(priv->core_clk);
974
975 regulator_disable(priv->vref);
976
977 meson_sar_adc_unlock(indio_dev);
978
979 return 0;
980 }
981
meson_sar_adc_irq(int irq,void * data)982 static irqreturn_t meson_sar_adc_irq(int irq, void *data)
983 {
984 struct iio_dev *indio_dev = data;
985 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
986 unsigned int cnt, threshold;
987 u32 regval;
988
989 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
990 cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
991 threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
992
993 if (cnt < threshold)
994 return IRQ_NONE;
995
996 complete(&priv->done);
997
998 return IRQ_HANDLED;
999 }
1000
meson_sar_adc_calib(struct iio_dev * indio_dev)1001 static int meson_sar_adc_calib(struct iio_dev *indio_dev)
1002 {
1003 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1004 int ret, nominal0, nominal1, value0, value1;
1005
1006 /* use points 25% and 75% for calibration */
1007 nominal0 = (1 << priv->param->resolution) / 4;
1008 nominal1 = (1 << priv->param->resolution) * 3 / 4;
1009
1010 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_DIV4);
1011 usleep_range(10, 20);
1012 ret = meson_sar_adc_get_sample(indio_dev,
1013 &indio_dev->channels[7],
1014 MEAN_AVERAGING, EIGHT_SAMPLES, &value0);
1015 if (ret < 0)
1016 goto out;
1017
1018 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4);
1019 usleep_range(10, 20);
1020 ret = meson_sar_adc_get_sample(indio_dev,
1021 &indio_dev->channels[7],
1022 MEAN_AVERAGING, EIGHT_SAMPLES, &value1);
1023 if (ret < 0)
1024 goto out;
1025
1026 if (value1 <= value0) {
1027 ret = -EINVAL;
1028 goto out;
1029 }
1030
1031 priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
1032 value1 - value0);
1033 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
1034 MILLION);
1035 ret = 0;
1036 out:
1037 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
1038
1039 return ret;
1040 }
1041
1042 static const struct iio_info meson_sar_adc_iio_info = {
1043 .read_raw = meson_sar_adc_iio_info_read_raw,
1044 };
1045
1046 static const struct meson_sar_adc_param meson_sar_adc_meson8_param = {
1047 .has_bl30_integration = false,
1048 .clock_rate = 1150000,
1049 .bandgap_reg = MESON_SAR_ADC_DELTA_10,
1050 .regmap_config = &meson_sar_adc_regmap_config_meson8,
1051 .resolution = 10,
1052 .temperature_trimming_bits = 4,
1053 .temperature_multiplier = 18 * 10000,
1054 .temperature_divider = 1024 * 10 * 85,
1055 };
1056
1057 static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = {
1058 .has_bl30_integration = false,
1059 .clock_rate = 1150000,
1060 .bandgap_reg = MESON_SAR_ADC_DELTA_10,
1061 .regmap_config = &meson_sar_adc_regmap_config_meson8,
1062 .resolution = 10,
1063 .temperature_trimming_bits = 5,
1064 .temperature_multiplier = 10,
1065 .temperature_divider = 32,
1066 };
1067
1068 static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
1069 .has_bl30_integration = true,
1070 .clock_rate = 1200000,
1071 .bandgap_reg = MESON_SAR_ADC_REG11,
1072 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1073 .resolution = 10,
1074 };
1075
1076 static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
1077 .has_bl30_integration = true,
1078 .clock_rate = 1200000,
1079 .bandgap_reg = MESON_SAR_ADC_REG11,
1080 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1081 .resolution = 12,
1082 };
1083
1084 static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
1085 .has_bl30_integration = false,
1086 .clock_rate = 1200000,
1087 .bandgap_reg = MESON_SAR_ADC_REG11,
1088 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1089 .resolution = 12,
1090 };
1091
1092 static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
1093 .param = &meson_sar_adc_meson8_param,
1094 .name = "meson-meson8-saradc",
1095 };
1096
1097 static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = {
1098 .param = &meson_sar_adc_meson8b_param,
1099 .name = "meson-meson8b-saradc",
1100 };
1101
1102 static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data = {
1103 .param = &meson_sar_adc_meson8b_param,
1104 .name = "meson-meson8m2-saradc",
1105 };
1106
1107 static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
1108 .param = &meson_sar_adc_gxbb_param,
1109 .name = "meson-gxbb-saradc",
1110 };
1111
1112 static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {
1113 .param = &meson_sar_adc_gxl_param,
1114 .name = "meson-gxl-saradc",
1115 };
1116
1117 static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {
1118 .param = &meson_sar_adc_gxl_param,
1119 .name = "meson-gxm-saradc",
1120 };
1121
1122 static const struct meson_sar_adc_data meson_sar_adc_axg_data = {
1123 .param = &meson_sar_adc_gxl_param,
1124 .name = "meson-axg-saradc",
1125 };
1126
1127 static const struct meson_sar_adc_data meson_sar_adc_g12a_data = {
1128 .param = &meson_sar_adc_g12a_param,
1129 .name = "meson-g12a-saradc",
1130 };
1131
1132 static const struct of_device_id meson_sar_adc_of_match[] = {
1133 {
1134 .compatible = "amlogic,meson8-saradc",
1135 .data = &meson_sar_adc_meson8_data,
1136 }, {
1137 .compatible = "amlogic,meson8b-saradc",
1138 .data = &meson_sar_adc_meson8b_data,
1139 }, {
1140 .compatible = "amlogic,meson8m2-saradc",
1141 .data = &meson_sar_adc_meson8m2_data,
1142 }, {
1143 .compatible = "amlogic,meson-gxbb-saradc",
1144 .data = &meson_sar_adc_gxbb_data,
1145 }, {
1146 .compatible = "amlogic,meson-gxl-saradc",
1147 .data = &meson_sar_adc_gxl_data,
1148 }, {
1149 .compatible = "amlogic,meson-gxm-saradc",
1150 .data = &meson_sar_adc_gxm_data,
1151 }, {
1152 .compatible = "amlogic,meson-axg-saradc",
1153 .data = &meson_sar_adc_axg_data,
1154 }, {
1155 .compatible = "amlogic,meson-g12a-saradc",
1156 .data = &meson_sar_adc_g12a_data,
1157 },
1158 { /* sentinel */ }
1159 };
1160 MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
1161
meson_sar_adc_probe(struct platform_device * pdev)1162 static int meson_sar_adc_probe(struct platform_device *pdev)
1163 {
1164 const struct meson_sar_adc_data *match_data;
1165 struct meson_sar_adc_priv *priv;
1166 struct device *dev = &pdev->dev;
1167 struct iio_dev *indio_dev;
1168 void __iomem *base;
1169 int irq, ret;
1170
1171 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
1172 if (!indio_dev)
1173 return dev_err_probe(dev, -ENOMEM, "failed allocating iio device\n");
1174
1175 priv = iio_priv(indio_dev);
1176 init_completion(&priv->done);
1177
1178 match_data = of_device_get_match_data(dev);
1179 if (!match_data)
1180 return dev_err_probe(dev, -ENODEV, "failed to get match data\n");
1181
1182 priv->param = match_data->param;
1183
1184 indio_dev->name = match_data->name;
1185 indio_dev->modes = INDIO_DIRECT_MODE;
1186 indio_dev->info = &meson_sar_adc_iio_info;
1187
1188 base = devm_platform_ioremap_resource(pdev, 0);
1189 if (IS_ERR(base))
1190 return PTR_ERR(base);
1191
1192 priv->regmap = devm_regmap_init_mmio(dev, base, priv->param->regmap_config);
1193 if (IS_ERR(priv->regmap))
1194 return PTR_ERR(priv->regmap);
1195
1196 irq = irq_of_parse_and_map(dev->of_node, 0);
1197 if (!irq)
1198 return -EINVAL;
1199
1200 ret = devm_request_irq(dev, irq, meson_sar_adc_irq, IRQF_SHARED, dev_name(dev), indio_dev);
1201 if (ret)
1202 return ret;
1203
1204 priv->clkin = devm_clk_get(dev, "clkin");
1205 if (IS_ERR(priv->clkin))
1206 return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n");
1207
1208 priv->core_clk = devm_clk_get(dev, "core");
1209 if (IS_ERR(priv->core_clk))
1210 return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n");
1211
1212 priv->adc_clk = devm_clk_get_optional(dev, "adc_clk");
1213 if (IS_ERR(priv->adc_clk))
1214 return dev_err_probe(dev, PTR_ERR(priv->adc_clk), "failed to get adc clk\n");
1215
1216 priv->adc_sel_clk = devm_clk_get_optional(dev, "adc_sel");
1217 if (IS_ERR(priv->adc_sel_clk))
1218 return dev_err_probe(dev, PTR_ERR(priv->adc_sel_clk), "failed to get adc_sel clk\n");
1219
1220 /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
1221 if (!priv->adc_clk) {
1222 ret = meson_sar_adc_clk_init(indio_dev, base);
1223 if (ret)
1224 return ret;
1225 }
1226
1227 priv->vref = devm_regulator_get(dev, "vref");
1228 if (IS_ERR(priv->vref))
1229 return dev_err_probe(dev, PTR_ERR(priv->vref), "failed to get vref regulator\n");
1230
1231 priv->calibscale = MILLION;
1232
1233 if (priv->param->temperature_trimming_bits) {
1234 ret = meson_sar_adc_temp_sensor_init(indio_dev);
1235 if (ret)
1236 return ret;
1237 }
1238
1239 if (priv->temperature_sensor_calibrated) {
1240 indio_dev->channels = meson_sar_adc_and_temp_iio_channels;
1241 indio_dev->num_channels =
1242 ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels);
1243 } else {
1244 indio_dev->channels = meson_sar_adc_iio_channels;
1245 indio_dev->num_channels =
1246 ARRAY_SIZE(meson_sar_adc_iio_channels);
1247 }
1248
1249 ret = meson_sar_adc_init(indio_dev);
1250 if (ret)
1251 goto err;
1252
1253 ret = meson_sar_adc_hw_enable(indio_dev);
1254 if (ret)
1255 goto err;
1256
1257 ret = meson_sar_adc_calib(indio_dev);
1258 if (ret)
1259 dev_warn(dev, "calibration failed\n");
1260
1261 platform_set_drvdata(pdev, indio_dev);
1262
1263 ret = iio_device_register(indio_dev);
1264 if (ret)
1265 goto err_hw;
1266
1267 return 0;
1268
1269 err_hw:
1270 meson_sar_adc_hw_disable(indio_dev);
1271 err:
1272 return ret;
1273 }
1274
meson_sar_adc_remove(struct platform_device * pdev)1275 static int meson_sar_adc_remove(struct platform_device *pdev)
1276 {
1277 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1278
1279 iio_device_unregister(indio_dev);
1280
1281 return meson_sar_adc_hw_disable(indio_dev);
1282 }
1283
meson_sar_adc_suspend(struct device * dev)1284 static int meson_sar_adc_suspend(struct device *dev)
1285 {
1286 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1287
1288 return meson_sar_adc_hw_disable(indio_dev);
1289 }
1290
meson_sar_adc_resume(struct device * dev)1291 static int meson_sar_adc_resume(struct device *dev)
1292 {
1293 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1294
1295 return meson_sar_adc_hw_enable(indio_dev);
1296 }
1297
1298 static DEFINE_SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
1299 meson_sar_adc_suspend, meson_sar_adc_resume);
1300
1301 static struct platform_driver meson_sar_adc_driver = {
1302 .probe = meson_sar_adc_probe,
1303 .remove = meson_sar_adc_remove,
1304 .driver = {
1305 .name = "meson-saradc",
1306 .of_match_table = meson_sar_adc_of_match,
1307 .pm = pm_sleep_ptr(&meson_sar_adc_pm_ops),
1308 },
1309 };
1310
1311 module_platform_driver(meson_sar_adc_driver);
1312
1313 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
1314 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
1315 MODULE_LICENSE("GPL v2");
1316
