1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * NXP i.MX8QXP ADC driver
4 *
5 * Based on the work of Haibo Chen <haibo.chen@nxp.com>
6 * The initial developer of the original code is Haibo Chen.
7 * Portions created by Haibo Chen are Copyright (C) 2018 NXP.
8 * All Rights Reserved.
9 *
10 * Copyright (C) 2018 NXP
11 * Copyright (C) 2021 Cai Huoqing
12 */
13 #include <linux/bitfield.h>
14 #include <linux/bits.h>
15 #include <linux/clk.h>
16 #include <linux/completion.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/kernel.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/regulator/consumer.h>
27
28 #include <linux/iio/iio.h>
29
30 #define ADC_DRIVER_NAME "imx8qxp-adc"
31
32 /* Register map definition */
33 #define IMX8QXP_ADR_ADC_CTRL 0x10
34 #define IMX8QXP_ADR_ADC_STAT 0x14
35 #define IMX8QXP_ADR_ADC_IE 0x18
36 #define IMX8QXP_ADR_ADC_DE 0x1c
37 #define IMX8QXP_ADR_ADC_CFG 0x20
38 #define IMX8QXP_ADR_ADC_FCTRL 0x30
39 #define IMX8QXP_ADR_ADC_SWTRIG 0x34
40 #define IMX8QXP_ADR_ADC_TCTRL(tid) (0xc0 + (tid) * 4)
41 #define IMX8QXP_ADR_ADC_CMDH(cid) (0x100 + (cid) * 8)
42 #define IMX8QXP_ADR_ADC_CMDL(cid) (0x104 + (cid) * 8)
43 #define IMX8QXP_ADR_ADC_RESFIFO 0x300
44 #define IMX8QXP_ADR_ADC_TST 0xffc
45
46 /* ADC bit shift */
47 #define IMX8QXP_ADC_IE_FWMIE_MASK GENMASK(1, 0)
48 #define IMX8QXP_ADC_CTRL_FIFO_RESET_MASK BIT(8)
49 #define IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK BIT(1)
50 #define IMX8QXP_ADC_CTRL_ADC_EN_MASK BIT(0)
51 #define IMX8QXP_ADC_TCTRL_TCMD_MASK GENMASK(31, 24)
52 #define IMX8QXP_ADC_TCTRL_TDLY_MASK GENMASK(23, 16)
53 #define IMX8QXP_ADC_TCTRL_TPRI_MASK GENMASK(15, 8)
54 #define IMX8QXP_ADC_TCTRL_HTEN_MASK GENMASK(7, 0)
55 #define IMX8QXP_ADC_CMDL_CSCALE_MASK GENMASK(13, 8)
56 #define IMX8QXP_ADC_CMDL_MODE_MASK BIT(7)
57 #define IMX8QXP_ADC_CMDL_DIFF_MASK BIT(6)
58 #define IMX8QXP_ADC_CMDL_ABSEL_MASK BIT(5)
59 #define IMX8QXP_ADC_CMDL_ADCH_MASK GENMASK(2, 0)
60 #define IMX8QXP_ADC_CMDH_NEXT_MASK GENMASK(31, 24)
61 #define IMX8QXP_ADC_CMDH_LOOP_MASK GENMASK(23, 16)
62 #define IMX8QXP_ADC_CMDH_AVGS_MASK GENMASK(15, 12)
63 #define IMX8QXP_ADC_CMDH_STS_MASK BIT(8)
64 #define IMX8QXP_ADC_CMDH_LWI_MASK GENMASK(7, 7)
65 #define IMX8QXP_ADC_CMDH_CMPEN_MASK GENMASK(0, 0)
66 #define IMX8QXP_ADC_CFG_PWREN_MASK BIT(28)
67 #define IMX8QXP_ADC_CFG_PUDLY_MASK GENMASK(23, 16)
68 #define IMX8QXP_ADC_CFG_REFSEL_MASK GENMASK(7, 6)
69 #define IMX8QXP_ADC_CFG_PWRSEL_MASK GENMASK(5, 4)
70 #define IMX8QXP_ADC_CFG_TPRICTRL_MASK GENMASK(3, 0)
71 #define IMX8QXP_ADC_FCTRL_FWMARK_MASK GENMASK(20, 16)
72 #define IMX8QXP_ADC_FCTRL_FCOUNT_MASK GENMASK(4, 0)
73 #define IMX8QXP_ADC_RESFIFO_VAL_MASK GENMASK(18, 3)
74
75 /* ADC PARAMETER*/
76 #define IMX8QXP_ADC_CMDL_CHANNEL_SCALE_FULL GENMASK(5, 0)
77 #define IMX8QXP_ADC_CMDL_SEL_A_A_B_CHANNEL 0
78 #define IMX8QXP_ADC_CMDL_STANDARD_RESOLUTION 0
79 #define IMX8QXP_ADC_CMDL_MODE_SINGLE 0
80 #define IMX8QXP_ADC_CMDH_LWI_INCREMENT_DIS 0
81 #define IMX8QXP_ADC_CMDH_CMPEN_DIS 0
82 #define IMX8QXP_ADC_PAUSE_EN BIT(31)
83 #define IMX8QXP_ADC_TCTRL_TPRI_PRIORITY_HIGH 0
84
85 #define IMX8QXP_ADC_TCTRL_HTEN_HW_TIRG_DIS 0
86
87 #define IMX8QXP_ADC_TIMEOUT msecs_to_jiffies(100)
88
89 struct imx8qxp_adc {
90 struct device *dev;
91 void __iomem *regs;
92 struct clk *clk;
93 struct clk *ipg_clk;
94 struct regulator *vref;
95 /* Serialise ADC channel reads */
96 struct mutex lock;
97 struct completion completion;
98 };
99
100 #define IMX8QXP_ADC_CHAN(_idx) { \
101 .type = IIO_VOLTAGE, \
102 .indexed = 1, \
103 .channel = (_idx), \
104 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
105 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
106 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
107 }
108
109 static const struct iio_chan_spec imx8qxp_adc_iio_channels[] = {
110 IMX8QXP_ADC_CHAN(0),
111 IMX8QXP_ADC_CHAN(1),
112 IMX8QXP_ADC_CHAN(2),
113 IMX8QXP_ADC_CHAN(3),
114 IMX8QXP_ADC_CHAN(4),
115 IMX8QXP_ADC_CHAN(5),
116 IMX8QXP_ADC_CHAN(6),
117 IMX8QXP_ADC_CHAN(7),
118 };
119
imx8qxp_adc_reset(struct imx8qxp_adc * adc)120 static void imx8qxp_adc_reset(struct imx8qxp_adc *adc)
121 {
122 u32 ctrl;
123
124 /*software reset, need to clear the set bit*/
125 ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL);
126 ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK, 1);
127 writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
128 udelay(10);
129 ctrl &= ~FIELD_PREP(IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK, 1);
130 writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
131
132 /* reset the fifo */
133 ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_FIFO_RESET_MASK, 1);
134 writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
135 }
136
imx8qxp_adc_reg_config(struct imx8qxp_adc * adc,int channel)137 static void imx8qxp_adc_reg_config(struct imx8qxp_adc *adc, int channel)
138 {
139 u32 adc_cfg, adc_tctrl, adc_cmdl, adc_cmdh;
140
141 /* ADC configuration */
142 adc_cfg = FIELD_PREP(IMX8QXP_ADC_CFG_PWREN_MASK, 1) |
143 FIELD_PREP(IMX8QXP_ADC_CFG_PUDLY_MASK, 0x80)|
144 FIELD_PREP(IMX8QXP_ADC_CFG_REFSEL_MASK, 0) |
145 FIELD_PREP(IMX8QXP_ADC_CFG_PWRSEL_MASK, 3) |
146 FIELD_PREP(IMX8QXP_ADC_CFG_TPRICTRL_MASK, 0);
147 writel(adc_cfg, adc->regs + IMX8QXP_ADR_ADC_CFG);
148
149 /* config the trigger control */
150 adc_tctrl = FIELD_PREP(IMX8QXP_ADC_TCTRL_TCMD_MASK, 1) |
151 FIELD_PREP(IMX8QXP_ADC_TCTRL_TDLY_MASK, 0) |
152 FIELD_PREP(IMX8QXP_ADC_TCTRL_TPRI_MASK, IMX8QXP_ADC_TCTRL_TPRI_PRIORITY_HIGH) |
153 FIELD_PREP(IMX8QXP_ADC_TCTRL_HTEN_MASK, IMX8QXP_ADC_TCTRL_HTEN_HW_TIRG_DIS);
154 writel(adc_tctrl, adc->regs + IMX8QXP_ADR_ADC_TCTRL(0));
155
156 /* config the cmd */
157 adc_cmdl = FIELD_PREP(IMX8QXP_ADC_CMDL_CSCALE_MASK, IMX8QXP_ADC_CMDL_CHANNEL_SCALE_FULL) |
158 FIELD_PREP(IMX8QXP_ADC_CMDL_MODE_MASK, IMX8QXP_ADC_CMDL_STANDARD_RESOLUTION) |
159 FIELD_PREP(IMX8QXP_ADC_CMDL_DIFF_MASK, IMX8QXP_ADC_CMDL_MODE_SINGLE) |
160 FIELD_PREP(IMX8QXP_ADC_CMDL_ABSEL_MASK, IMX8QXP_ADC_CMDL_SEL_A_A_B_CHANNEL) |
161 FIELD_PREP(IMX8QXP_ADC_CMDL_ADCH_MASK, channel);
162 writel(adc_cmdl, adc->regs + IMX8QXP_ADR_ADC_CMDL(0));
163
164 adc_cmdh = FIELD_PREP(IMX8QXP_ADC_CMDH_NEXT_MASK, 0) |
165 FIELD_PREP(IMX8QXP_ADC_CMDH_LOOP_MASK, 0) |
166 FIELD_PREP(IMX8QXP_ADC_CMDH_AVGS_MASK, 7) |
167 FIELD_PREP(IMX8QXP_ADC_CMDH_STS_MASK, 0) |
168 FIELD_PREP(IMX8QXP_ADC_CMDH_LWI_MASK, IMX8QXP_ADC_CMDH_LWI_INCREMENT_DIS) |
169 FIELD_PREP(IMX8QXP_ADC_CMDH_CMPEN_MASK, IMX8QXP_ADC_CMDH_CMPEN_DIS);
170 writel(adc_cmdh, adc->regs + IMX8QXP_ADR_ADC_CMDH(0));
171 }
172
imx8qxp_adc_fifo_config(struct imx8qxp_adc * adc)173 static void imx8qxp_adc_fifo_config(struct imx8qxp_adc *adc)
174 {
175 u32 fifo_ctrl, interrupt_en;
176
177 fifo_ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL);
178 fifo_ctrl &= ~IMX8QXP_ADC_FCTRL_FWMARK_MASK;
179 /* set the watermark level to 1 */
180 fifo_ctrl |= FIELD_PREP(IMX8QXP_ADC_FCTRL_FWMARK_MASK, 0);
181 writel(fifo_ctrl, adc->regs + IMX8QXP_ADR_ADC_FCTRL);
182
183 /* FIFO Watermark Interrupt Enable */
184 interrupt_en = readl(adc->regs + IMX8QXP_ADR_ADC_IE);
185 interrupt_en |= FIELD_PREP(IMX8QXP_ADC_IE_FWMIE_MASK, 1);
186 writel(interrupt_en, adc->regs + IMX8QXP_ADR_ADC_IE);
187 }
188
imx8qxp_adc_disable(struct imx8qxp_adc * adc)189 static void imx8qxp_adc_disable(struct imx8qxp_adc *adc)
190 {
191 u32 ctrl;
192
193 ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL);
194 ctrl &= ~FIELD_PREP(IMX8QXP_ADC_CTRL_ADC_EN_MASK, 1);
195 writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
196 }
197
imx8qxp_adc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)198 static int imx8qxp_adc_read_raw(struct iio_dev *indio_dev,
199 struct iio_chan_spec const *chan,
200 int *val, int *val2, long mask)
201 {
202 struct imx8qxp_adc *adc = iio_priv(indio_dev);
203 struct device *dev = adc->dev;
204
205 u32 ctrl;
206 long ret;
207
208 switch (mask) {
209 case IIO_CHAN_INFO_RAW:
210 pm_runtime_get_sync(dev);
211
212 mutex_lock(&adc->lock);
213 reinit_completion(&adc->completion);
214
215 imx8qxp_adc_reg_config(adc, chan->channel);
216
217 imx8qxp_adc_fifo_config(adc);
218
219 /* adc enable */
220 ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL);
221 ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_ADC_EN_MASK, 1);
222 writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
223 /* adc start */
224 writel(1, adc->regs + IMX8QXP_ADR_ADC_SWTRIG);
225
226 ret = wait_for_completion_interruptible_timeout(&adc->completion,
227 IMX8QXP_ADC_TIMEOUT);
228
229 pm_runtime_mark_last_busy(dev);
230 pm_runtime_put_sync_autosuspend(dev);
231
232 if (ret == 0) {
233 mutex_unlock(&adc->lock);
234 return -ETIMEDOUT;
235 }
236 if (ret < 0) {
237 mutex_unlock(&adc->lock);
238 return ret;
239 }
240
241 *val = FIELD_GET(IMX8QXP_ADC_RESFIFO_VAL_MASK,
242 readl(adc->regs + IMX8QXP_ADR_ADC_RESFIFO));
243
244 mutex_unlock(&adc->lock);
245 return IIO_VAL_INT;
246
247 case IIO_CHAN_INFO_SCALE:
248 ret = regulator_get_voltage(adc->vref);
249 if (ret < 0)
250 return ret;
251 *val = ret / 1000;
252 *val2 = 12;
253 return IIO_VAL_FRACTIONAL_LOG2;
254
255 case IIO_CHAN_INFO_SAMP_FREQ:
256 *val = clk_get_rate(adc->clk) / 3;
257 return IIO_VAL_INT;
258
259 default:
260 return -EINVAL;
261 }
262 }
263
imx8qxp_adc_isr(int irq,void * dev_id)264 static irqreturn_t imx8qxp_adc_isr(int irq, void *dev_id)
265 {
266 struct imx8qxp_adc *adc = dev_id;
267 u32 fifo_count;
268
269 fifo_count = FIELD_GET(IMX8QXP_ADC_FCTRL_FCOUNT_MASK,
270 readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL));
271
272 if (fifo_count)
273 complete(&adc->completion);
274
275 return IRQ_HANDLED;
276 }
277
imx8qxp_adc_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)278 static int imx8qxp_adc_reg_access(struct iio_dev *indio_dev, unsigned int reg,
279 unsigned int writeval, unsigned int *readval)
280 {
281 struct imx8qxp_adc *adc = iio_priv(indio_dev);
282 struct device *dev = adc->dev;
283
284 if (!readval || reg % 4 || reg > IMX8QXP_ADR_ADC_TST)
285 return -EINVAL;
286
287 pm_runtime_get_sync(dev);
288
289 *readval = readl(adc->regs + reg);
290
291 pm_runtime_mark_last_busy(dev);
292 pm_runtime_put_sync_autosuspend(dev);
293
294 return 0;
295 }
296
297 static const struct iio_info imx8qxp_adc_iio_info = {
298 .read_raw = &imx8qxp_adc_read_raw,
299 .debugfs_reg_access = &imx8qxp_adc_reg_access,
300 };
301
imx8qxp_adc_probe(struct platform_device * pdev)302 static int imx8qxp_adc_probe(struct platform_device *pdev)
303 {
304 struct imx8qxp_adc *adc;
305 struct iio_dev *indio_dev;
306 struct device *dev = &pdev->dev;
307 int irq;
308 int ret;
309
310 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
311 if (!indio_dev) {
312 dev_err(dev, "Failed allocating iio device\n");
313 return -ENOMEM;
314 }
315
316 adc = iio_priv(indio_dev);
317 adc->dev = dev;
318
319 mutex_init(&adc->lock);
320 adc->regs = devm_platform_ioremap_resource(pdev, 0);
321 if (IS_ERR(adc->regs))
322 return PTR_ERR(adc->regs);
323
324 irq = platform_get_irq(pdev, 0);
325 if (irq < 0)
326 return irq;
327
328 adc->clk = devm_clk_get(dev, "per");
329 if (IS_ERR(adc->clk))
330 return dev_err_probe(dev, PTR_ERR(adc->clk), "Failed getting clock\n");
331
332 adc->ipg_clk = devm_clk_get(dev, "ipg");
333 if (IS_ERR(adc->ipg_clk))
334 return dev_err_probe(dev, PTR_ERR(adc->ipg_clk), "Failed getting clock\n");
335
336 adc->vref = devm_regulator_get(dev, "vref");
337 if (IS_ERR(adc->vref))
338 return dev_err_probe(dev, PTR_ERR(adc->vref), "Failed getting reference voltage\n");
339
340 ret = regulator_enable(adc->vref);
341 if (ret) {
342 dev_err(dev, "Can't enable adc reference top voltage\n");
343 return ret;
344 }
345
346 platform_set_drvdata(pdev, indio_dev);
347
348 init_completion(&adc->completion);
349
350 indio_dev->name = ADC_DRIVER_NAME;
351 indio_dev->info = &imx8qxp_adc_iio_info;
352 indio_dev->modes = INDIO_DIRECT_MODE;
353 indio_dev->channels = imx8qxp_adc_iio_channels;
354 indio_dev->num_channels = ARRAY_SIZE(imx8qxp_adc_iio_channels);
355
356 ret = clk_prepare_enable(adc->clk);
357 if (ret) {
358 dev_err(&pdev->dev, "Could not prepare or enable the clock.\n");
359 goto error_regulator_disable;
360 }
361
362 ret = clk_prepare_enable(adc->ipg_clk);
363 if (ret) {
364 dev_err(&pdev->dev, "Could not prepare or enable the clock.\n");
365 goto error_adc_clk_disable;
366 }
367
368 ret = devm_request_irq(dev, irq, imx8qxp_adc_isr, 0, ADC_DRIVER_NAME, adc);
369 if (ret < 0) {
370 dev_err(dev, "Failed requesting irq, irq = %d\n", irq);
371 goto error_ipg_clk_disable;
372 }
373
374 imx8qxp_adc_reset(adc);
375
376 ret = iio_device_register(indio_dev);
377 if (ret) {
378 imx8qxp_adc_disable(adc);
379 dev_err(dev, "Couldn't register the device.\n");
380 goto error_ipg_clk_disable;
381 }
382
383 pm_runtime_set_active(dev);
384 pm_runtime_set_autosuspend_delay(dev, 50);
385 pm_runtime_use_autosuspend(dev);
386 pm_runtime_enable(dev);
387
388 return 0;
389
390 error_ipg_clk_disable:
391 clk_disable_unprepare(adc->ipg_clk);
392 error_adc_clk_disable:
393 clk_disable_unprepare(adc->clk);
394 error_regulator_disable:
395 regulator_disable(adc->vref);
396
397 return ret;
398 }
399
imx8qxp_adc_remove(struct platform_device * pdev)400 static int imx8qxp_adc_remove(struct platform_device *pdev)
401 {
402 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
403 struct imx8qxp_adc *adc = iio_priv(indio_dev);
404 struct device *dev = adc->dev;
405
406 pm_runtime_get_sync(dev);
407
408 iio_device_unregister(indio_dev);
409
410 imx8qxp_adc_disable(adc);
411
412 clk_disable_unprepare(adc->clk);
413 clk_disable_unprepare(adc->ipg_clk);
414 regulator_disable(adc->vref);
415
416 pm_runtime_disable(dev);
417 pm_runtime_put_noidle(dev);
418
419 return 0;
420 }
421
imx8qxp_adc_runtime_suspend(struct device * dev)422 static int imx8qxp_adc_runtime_suspend(struct device *dev)
423 {
424 struct iio_dev *indio_dev = dev_get_drvdata(dev);
425 struct imx8qxp_adc *adc = iio_priv(indio_dev);
426
427 imx8qxp_adc_disable(adc);
428
429 clk_disable_unprepare(adc->clk);
430 clk_disable_unprepare(adc->ipg_clk);
431 regulator_disable(adc->vref);
432
433 return 0;
434 }
435
imx8qxp_adc_runtime_resume(struct device * dev)436 static int imx8qxp_adc_runtime_resume(struct device *dev)
437 {
438 struct iio_dev *indio_dev = dev_get_drvdata(dev);
439 struct imx8qxp_adc *adc = iio_priv(indio_dev);
440 int ret;
441
442 ret = regulator_enable(adc->vref);
443 if (ret) {
444 dev_err(dev, "Can't enable adc reference top voltage, err = %d\n", ret);
445 return ret;
446 }
447
448 ret = clk_prepare_enable(adc->clk);
449 if (ret) {
450 dev_err(dev, "Could not prepare or enable clock.\n");
451 goto err_disable_reg;
452 }
453
454 ret = clk_prepare_enable(adc->ipg_clk);
455 if (ret) {
456 dev_err(dev, "Could not prepare or enable clock.\n");
457 goto err_unprepare_clk;
458 }
459
460 imx8qxp_adc_reset(adc);
461
462 return 0;
463
464 err_unprepare_clk:
465 clk_disable_unprepare(adc->clk);
466
467 err_disable_reg:
468 regulator_disable(adc->vref);
469
470 return ret;
471 }
472
473 static DEFINE_RUNTIME_DEV_PM_OPS(imx8qxp_adc_pm_ops,
474 imx8qxp_adc_runtime_suspend,
475 imx8qxp_adc_runtime_resume, NULL);
476
477 static const struct of_device_id imx8qxp_adc_match[] = {
478 { .compatible = "nxp,imx8qxp-adc", },
479 { /* sentinel */ }
480 };
481 MODULE_DEVICE_TABLE(of, imx8qxp_adc_match);
482
483 static struct platform_driver imx8qxp_adc_driver = {
484 .probe = imx8qxp_adc_probe,
485 .remove = imx8qxp_adc_remove,
486 .driver = {
487 .name = ADC_DRIVER_NAME,
488 .of_match_table = imx8qxp_adc_match,
489 .pm = pm_ptr(&imx8qxp_adc_pm_ops),
490 },
491 };
492
493 module_platform_driver(imx8qxp_adc_driver);
494
495 MODULE_DESCRIPTION("i.MX8QuadXPlus ADC driver");
496 MODULE_LICENSE("GPL v2");
497
