1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2021 Intel Corporation
4 */
5
6 #define NUM_STEPS 5
7 #define H2G_DELAY 50000
8 #define delay_for_h2g() usleep_range(H2G_DELAY, H2G_DELAY + 10000)
9 #define FREQUENCY_REQ_UNIT DIV_ROUND_CLOSEST(GT_FREQUENCY_MULTIPLIER, \
10 GEN9_FREQ_SCALER)
11 enum test_type {
12 VARY_MIN,
13 VARY_MAX,
14 MAX_GRANTED
15 };
16
slpc_set_min_freq(struct intel_guc_slpc * slpc,u32 freq)17 static int slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 freq)
18 {
19 int ret;
20
21 ret = intel_guc_slpc_set_min_freq(slpc, freq);
22 if (ret)
23 pr_err("Could not set min frequency to [%u]\n", freq);
24 else /* Delay to ensure h2g completes */
25 delay_for_h2g();
26
27 return ret;
28 }
29
slpc_set_max_freq(struct intel_guc_slpc * slpc,u32 freq)30 static int slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 freq)
31 {
32 int ret;
33
34 ret = intel_guc_slpc_set_max_freq(slpc, freq);
35 if (ret)
36 pr_err("Could not set maximum frequency [%u]\n",
37 freq);
38 else /* Delay to ensure h2g completes */
39 delay_for_h2g();
40
41 return ret;
42 }
43
vary_max_freq(struct intel_guc_slpc * slpc,struct intel_rps * rps,u32 * max_act_freq)44 static int vary_max_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps,
45 u32 *max_act_freq)
46 {
47 u32 step, max_freq, req_freq;
48 u32 act_freq;
49 int err = 0;
50
51 /* Go from max to min in 5 steps */
52 step = (slpc->rp0_freq - slpc->min_freq) / NUM_STEPS;
53 *max_act_freq = slpc->min_freq;
54 for (max_freq = slpc->rp0_freq; max_freq > slpc->min_freq;
55 max_freq -= step) {
56 err = slpc_set_max_freq(slpc, max_freq);
57 if (err)
58 break;
59
60 req_freq = intel_rps_read_punit_req_frequency(rps);
61
62 /* GuC requests freq in multiples of 50/3 MHz */
63 if (req_freq > (max_freq + FREQUENCY_REQ_UNIT)) {
64 pr_err("SWReq is %d, should be at most %d\n", req_freq,
65 max_freq + FREQUENCY_REQ_UNIT);
66 err = -EINVAL;
67 }
68
69 act_freq = intel_rps_read_actual_frequency(rps);
70 if (act_freq > *max_act_freq)
71 *max_act_freq = act_freq;
72
73 if (err)
74 break;
75 }
76
77 return err;
78 }
79
vary_min_freq(struct intel_guc_slpc * slpc,struct intel_rps * rps,u32 * max_act_freq)80 static int vary_min_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps,
81 u32 *max_act_freq)
82 {
83 u32 step, min_freq, req_freq;
84 u32 act_freq;
85 int err = 0;
86
87 /* Go from min to max in 5 steps */
88 step = (slpc->rp0_freq - slpc->min_freq) / NUM_STEPS;
89 *max_act_freq = slpc->min_freq;
90 for (min_freq = slpc->min_freq; min_freq < slpc->rp0_freq;
91 min_freq += step) {
92 err = slpc_set_min_freq(slpc, min_freq);
93 if (err)
94 break;
95
96 req_freq = intel_rps_read_punit_req_frequency(rps);
97
98 /* GuC requests freq in multiples of 50/3 MHz */
99 if (req_freq < (min_freq - FREQUENCY_REQ_UNIT)) {
100 pr_err("SWReq is %d, should be at least %d\n", req_freq,
101 min_freq - FREQUENCY_REQ_UNIT);
102 err = -EINVAL;
103 }
104
105 act_freq = intel_rps_read_actual_frequency(rps);
106 if (act_freq > *max_act_freq)
107 *max_act_freq = act_freq;
108
109 if (err)
110 break;
111 }
112
113 return err;
114 }
115
max_granted_freq(struct intel_guc_slpc * slpc,struct intel_rps * rps,u32 * max_act_freq)116 static int max_granted_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps, u32 *max_act_freq)
117 {
118 struct intel_gt *gt = rps_to_gt(rps);
119 u32 perf_limit_reasons;
120 int err = 0;
121
122 err = slpc_set_min_freq(slpc, slpc->rp0_freq);
123 if (err)
124 return err;
125
126 *max_act_freq = intel_rps_read_actual_frequency(rps);
127 if (*max_act_freq != slpc->rp0_freq) {
128 /* Check if there was some throttling by pcode */
129 perf_limit_reasons = intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS);
130
131 /* If not, this is an error */
132 if (!(perf_limit_reasons & GT0_PERF_LIMIT_REASONS_MASK)) {
133 pr_err("Pcode did not grant max freq\n");
134 err = -EINVAL;
135 } else {
136 pr_info("Pcode throttled frequency 0x%x\n", perf_limit_reasons);
137 }
138 }
139
140 return err;
141 }
142
run_test(struct intel_gt * gt,int test_type)143 static int run_test(struct intel_gt *gt, int test_type)
144 {
145 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
146 struct intel_rps *rps = >->rps;
147 struct intel_engine_cs *engine;
148 enum intel_engine_id id;
149 struct igt_spinner spin;
150 u32 slpc_min_freq, slpc_max_freq;
151 int err = 0;
152
153 if (!intel_uc_uses_guc_slpc(>->uc))
154 return 0;
155
156 if (igt_spinner_init(&spin, gt))
157 return -ENOMEM;
158
159 if (intel_guc_slpc_get_max_freq(slpc, &slpc_max_freq)) {
160 pr_err("Could not get SLPC max freq\n");
161 return -EIO;
162 }
163
164 if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq)) {
165 pr_err("Could not get SLPC min freq\n");
166 return -EIO;
167 }
168
169 /*
170 * FIXME: With efficient frequency enabled, GuC can request
171 * frequencies higher than the SLPC max. While this is fixed
172 * in GuC, we level set these tests with RPn as min.
173 */
174 err = slpc_set_min_freq(slpc, slpc->min_freq);
175 if (err)
176 return err;
177
178 if (slpc->min_freq == slpc->rp0_freq) {
179 pr_err("Min/Max are fused to the same value\n");
180 return -EINVAL;
181 }
182
183 intel_gt_pm_wait_for_idle(gt);
184 intel_gt_pm_get(gt);
185 for_each_engine(engine, gt, id) {
186 struct i915_request *rq;
187 u32 max_act_freq;
188
189 if (!intel_engine_can_store_dword(engine))
190 continue;
191
192 st_engine_heartbeat_disable(engine);
193
194 rq = igt_spinner_create_request(&spin,
195 engine->kernel_context,
196 MI_NOOP);
197 if (IS_ERR(rq)) {
198 err = PTR_ERR(rq);
199 st_engine_heartbeat_enable(engine);
200 break;
201 }
202
203 i915_request_add(rq);
204
205 if (!igt_wait_for_spinner(&spin, rq)) {
206 pr_err("%s: Spinner did not start\n",
207 engine->name);
208 igt_spinner_end(&spin);
209 st_engine_heartbeat_enable(engine);
210 intel_gt_set_wedged(engine->gt);
211 err = -EIO;
212 break;
213 }
214
215 switch (test_type) {
216 case VARY_MIN:
217 err = vary_min_freq(slpc, rps, &max_act_freq);
218 break;
219
220 case VARY_MAX:
221 err = vary_max_freq(slpc, rps, &max_act_freq);
222 break;
223
224 case MAX_GRANTED:
225 /* Media engines have a different RP0 */
226 if (engine->class == VIDEO_DECODE_CLASS ||
227 engine->class == VIDEO_ENHANCEMENT_CLASS) {
228 igt_spinner_end(&spin);
229 st_engine_heartbeat_enable(engine);
230 err = 0;
231 continue;
232 }
233
234 err = max_granted_freq(slpc, rps, &max_act_freq);
235 break;
236 }
237
238 pr_info("Max actual frequency for %s was %d\n",
239 engine->name, max_act_freq);
240
241 /* Actual frequency should rise above min */
242 if (max_act_freq <= slpc_min_freq) {
243 pr_err("Actual freq did not rise above min\n");
244 pr_err("Perf Limit Reasons: 0x%x\n",
245 intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS));
246 err = -EINVAL;
247 }
248
249 igt_spinner_end(&spin);
250 st_engine_heartbeat_enable(engine);
251
252 if (err)
253 break;
254 }
255
256 /* Restore min/max frequencies */
257 slpc_set_max_freq(slpc, slpc_max_freq);
258 slpc_set_min_freq(slpc, slpc_min_freq);
259
260 if (igt_flush_test(gt->i915))
261 err = -EIO;
262
263 intel_gt_pm_put(gt);
264 igt_spinner_fini(&spin);
265 intel_gt_pm_wait_for_idle(gt);
266
267 return err;
268 }
269
live_slpc_vary_min(void * arg)270 static int live_slpc_vary_min(void *arg)
271 {
272 struct drm_i915_private *i915 = arg;
273 struct intel_gt *gt = to_gt(i915);
274
275 return run_test(gt, VARY_MIN);
276 }
277
live_slpc_vary_max(void * arg)278 static int live_slpc_vary_max(void *arg)
279 {
280 struct drm_i915_private *i915 = arg;
281 struct intel_gt *gt = to_gt(i915);
282
283 return run_test(gt, VARY_MAX);
284 }
285
286 /* check if pcode can grant RP0 */
live_slpc_max_granted(void * arg)287 static int live_slpc_max_granted(void *arg)
288 {
289 struct drm_i915_private *i915 = arg;
290 struct intel_gt *gt = to_gt(i915);
291
292 return run_test(gt, MAX_GRANTED);
293 }
294
intel_slpc_live_selftests(struct drm_i915_private * i915)295 int intel_slpc_live_selftests(struct drm_i915_private *i915)
296 {
297 static const struct i915_subtest tests[] = {
298 SUBTEST(live_slpc_vary_max),
299 SUBTEST(live_slpc_vary_min),
300 SUBTEST(live_slpc_max_granted),
301 };
302
303 if (intel_gt_is_wedged(to_gt(i915)))
304 return 0;
305
306 return i915_live_subtests(tests, i915);
307 }
308
