1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Hisilicon Hibmc SoC drm driver
3  *
4  * Based on the bochs drm driver.
5  *
6  * Copyright (c) 2016 Huawei Limited.
7  *
8  * Author:
9  *	Rongrong Zou <zourongrong@huawei.com>
10  *	Rongrong Zou <zourongrong@gmail.com>
11  *	Jianhua Li <lijianhua@huawei.com>
12  */
13 
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 
17 #include <drm/drm_aperture.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_drv.h>
20 #include <drm/drm_gem_framebuffer_helper.h>
21 #include <drm/drm_gem_vram_helper.h>
22 #include <drm/drm_managed.h>
23 #include <drm/drm_module.h>
24 #include <drm/drm_vblank.h>
25 
26 #include "hibmc_drm_drv.h"
27 #include "hibmc_drm_regs.h"
28 
29 DEFINE_DRM_GEM_FOPS(hibmc_fops);
30 
hibmc_interrupt(int irq,void * arg)31 static irqreturn_t hibmc_interrupt(int irq, void *arg)
32 {
33 	struct drm_device *dev = (struct drm_device *)arg;
34 	struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
35 	u32 status;
36 
37 	status = readl(priv->mmio + HIBMC_RAW_INTERRUPT);
38 
39 	if (status & HIBMC_RAW_INTERRUPT_VBLANK(1)) {
40 		writel(HIBMC_RAW_INTERRUPT_VBLANK(1),
41 		       priv->mmio + HIBMC_RAW_INTERRUPT);
42 		drm_handle_vblank(dev, 0);
43 	}
44 
45 	return IRQ_HANDLED;
46 }
47 
hibmc_dumb_create(struct drm_file * file,struct drm_device * dev,struct drm_mode_create_dumb * args)48 static int hibmc_dumb_create(struct drm_file *file, struct drm_device *dev,
49 			     struct drm_mode_create_dumb *args)
50 {
51 	return drm_gem_vram_fill_create_dumb(file, dev, 0, 128, args);
52 }
53 
54 static const struct drm_driver hibmc_driver = {
55 	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
56 	.fops			= &hibmc_fops,
57 	.name			= "hibmc",
58 	.date			= "20160828",
59 	.desc			= "hibmc drm driver",
60 	.major			= 1,
61 	.minor			= 0,
62 	.debugfs_init		= drm_vram_mm_debugfs_init,
63 	.dumb_create            = hibmc_dumb_create,
64 	.dumb_map_offset        = drm_gem_ttm_dumb_map_offset,
65 	.gem_prime_mmap		= drm_gem_prime_mmap,
66 };
67 
hibmc_pm_suspend(struct device * dev)68 static int __maybe_unused hibmc_pm_suspend(struct device *dev)
69 {
70 	struct drm_device *drm_dev = dev_get_drvdata(dev);
71 
72 	return drm_mode_config_helper_suspend(drm_dev);
73 }
74 
hibmc_pm_resume(struct device * dev)75 static int  __maybe_unused hibmc_pm_resume(struct device *dev)
76 {
77 	struct drm_device *drm_dev = dev_get_drvdata(dev);
78 
79 	return drm_mode_config_helper_resume(drm_dev);
80 }
81 
82 static const struct dev_pm_ops hibmc_pm_ops = {
83 	SET_SYSTEM_SLEEP_PM_OPS(hibmc_pm_suspend,
84 				hibmc_pm_resume)
85 };
86 
87 static const struct drm_mode_config_funcs hibmc_mode_funcs = {
88 	.mode_valid = drm_vram_helper_mode_valid,
89 	.atomic_check = drm_atomic_helper_check,
90 	.atomic_commit = drm_atomic_helper_commit,
91 	.fb_create = drm_gem_fb_create,
92 };
93 
hibmc_kms_init(struct hibmc_drm_private * priv)94 static int hibmc_kms_init(struct hibmc_drm_private *priv)
95 {
96 	struct drm_device *dev = &priv->dev;
97 	int ret;
98 
99 	ret = drmm_mode_config_init(dev);
100 	if (ret)
101 		return ret;
102 
103 	dev->mode_config.min_width = 0;
104 	dev->mode_config.min_height = 0;
105 	dev->mode_config.max_width = 1920;
106 	dev->mode_config.max_height = 1200;
107 
108 	dev->mode_config.fb_base = priv->fb_base;
109 	dev->mode_config.preferred_depth = 32;
110 	dev->mode_config.prefer_shadow = 1;
111 
112 	dev->mode_config.funcs = (void *)&hibmc_mode_funcs;
113 
114 	ret = hibmc_de_init(priv);
115 	if (ret) {
116 		drm_err(dev, "failed to init de: %d\n", ret);
117 		return ret;
118 	}
119 
120 	ret = hibmc_vdac_init(priv);
121 	if (ret) {
122 		drm_err(dev, "failed to init vdac: %d\n", ret);
123 		return ret;
124 	}
125 
126 	return 0;
127 }
128 
129 /*
130  * It can operate in one of three modes: 0, 1 or Sleep.
131  */
hibmc_set_power_mode(struct hibmc_drm_private * priv,u32 power_mode)132 void hibmc_set_power_mode(struct hibmc_drm_private *priv, u32 power_mode)
133 {
134 	u32 control_value = 0;
135 	void __iomem   *mmio = priv->mmio;
136 	u32 input = 1;
137 
138 	if (power_mode > HIBMC_PW_MODE_CTL_MODE_SLEEP)
139 		return;
140 
141 	if (power_mode == HIBMC_PW_MODE_CTL_MODE_SLEEP)
142 		input = 0;
143 
144 	control_value = readl(mmio + HIBMC_POWER_MODE_CTRL);
145 	control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK |
146 			   HIBMC_PW_MODE_CTL_OSC_INPUT_MASK);
147 	control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode);
148 	control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input);
149 	writel(control_value, mmio + HIBMC_POWER_MODE_CTRL);
150 }
151 
hibmc_set_current_gate(struct hibmc_drm_private * priv,unsigned int gate)152 void hibmc_set_current_gate(struct hibmc_drm_private *priv, unsigned int gate)
153 {
154 	u32 gate_reg;
155 	u32 mode;
156 	void __iomem   *mmio = priv->mmio;
157 
158 	/* Get current power mode. */
159 	mode = (readl(mmio + HIBMC_POWER_MODE_CTRL) &
160 		HIBMC_PW_MODE_CTL_MODE_MASK) >> HIBMC_PW_MODE_CTL_MODE_SHIFT;
161 
162 	switch (mode) {
163 	case HIBMC_PW_MODE_CTL_MODE_MODE0:
164 		gate_reg = HIBMC_MODE0_GATE;
165 		break;
166 
167 	case HIBMC_PW_MODE_CTL_MODE_MODE1:
168 		gate_reg = HIBMC_MODE1_GATE;
169 		break;
170 
171 	default:
172 		gate_reg = HIBMC_MODE0_GATE;
173 		break;
174 	}
175 	writel(gate, mmio + gate_reg);
176 }
177 
hibmc_hw_config(struct hibmc_drm_private * priv)178 static void hibmc_hw_config(struct hibmc_drm_private *priv)
179 {
180 	u32 reg;
181 
182 	/* On hardware reset, power mode 0 is default. */
183 	hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
184 
185 	/* Enable display power gate & LOCALMEM power gate*/
186 	reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
187 	reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
188 	reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
189 	reg |= HIBMC_CURR_GATE_DISPLAY(1);
190 	reg |= HIBMC_CURR_GATE_LOCALMEM(1);
191 
192 	hibmc_set_current_gate(priv, reg);
193 
194 	/*
195 	 * Reset the memory controller. If the memory controller
196 	 * is not reset in chip,the system might hang when sw accesses
197 	 * the memory.The memory should be resetted after
198 	 * changing the MXCLK.
199 	 */
200 	reg = readl(priv->mmio + HIBMC_MISC_CTRL);
201 	reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK;
202 	reg |= HIBMC_MSCCTL_LOCALMEM_RESET(0);
203 	writel(reg, priv->mmio + HIBMC_MISC_CTRL);
204 
205 	reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK;
206 	reg |= HIBMC_MSCCTL_LOCALMEM_RESET(1);
207 
208 	writel(reg, priv->mmio + HIBMC_MISC_CTRL);
209 }
210 
hibmc_hw_map(struct hibmc_drm_private * priv)211 static int hibmc_hw_map(struct hibmc_drm_private *priv)
212 {
213 	struct drm_device *dev = &priv->dev;
214 	struct pci_dev *pdev = to_pci_dev(dev->dev);
215 	resource_size_t addr, size, ioaddr, iosize;
216 
217 	ioaddr = pci_resource_start(pdev, 1);
218 	iosize = pci_resource_len(pdev, 1);
219 	priv->mmio = devm_ioremap(dev->dev, ioaddr, iosize);
220 	if (!priv->mmio) {
221 		drm_err(dev, "Cannot map mmio region\n");
222 		return -ENOMEM;
223 	}
224 
225 	addr = pci_resource_start(pdev, 0);
226 	size = pci_resource_len(pdev, 0);
227 	priv->fb_map = devm_ioremap(dev->dev, addr, size);
228 	if (!priv->fb_map) {
229 		drm_err(dev, "Cannot map framebuffer\n");
230 		return -ENOMEM;
231 	}
232 	priv->fb_base = addr;
233 	priv->fb_size = size;
234 
235 	return 0;
236 }
237 
hibmc_hw_init(struct hibmc_drm_private * priv)238 static int hibmc_hw_init(struct hibmc_drm_private *priv)
239 {
240 	int ret;
241 
242 	ret = hibmc_hw_map(priv);
243 	if (ret)
244 		return ret;
245 
246 	hibmc_hw_config(priv);
247 
248 	return 0;
249 }
250 
hibmc_unload(struct drm_device * dev)251 static int hibmc_unload(struct drm_device *dev)
252 {
253 	struct pci_dev *pdev = to_pci_dev(dev->dev);
254 
255 	drm_atomic_helper_shutdown(dev);
256 
257 	free_irq(pdev->irq, dev);
258 
259 	pci_disable_msi(to_pci_dev(dev->dev));
260 
261 	return 0;
262 }
263 
hibmc_load(struct drm_device * dev)264 static int hibmc_load(struct drm_device *dev)
265 {
266 	struct pci_dev *pdev = to_pci_dev(dev->dev);
267 	struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
268 	int ret;
269 
270 	ret = hibmc_hw_init(priv);
271 	if (ret)
272 		goto err;
273 
274 	ret = drmm_vram_helper_init(dev, pci_resource_start(pdev, 0), priv->fb_size);
275 	if (ret) {
276 		drm_err(dev, "Error initializing VRAM MM; %d\n", ret);
277 		goto err;
278 	}
279 
280 	ret = hibmc_kms_init(priv);
281 	if (ret)
282 		goto err;
283 
284 	ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
285 	if (ret) {
286 		drm_err(dev, "failed to initialize vblank: %d\n", ret);
287 		goto err;
288 	}
289 
290 	ret = pci_enable_msi(pdev);
291 	if (ret) {
292 		drm_warn(dev, "enabling MSI failed: %d\n", ret);
293 	} else {
294 		/* PCI devices require shared interrupts. */
295 		ret = request_irq(pdev->irq, hibmc_interrupt, IRQF_SHARED,
296 				  dev->driver->name, dev);
297 		if (ret)
298 			drm_warn(dev, "install irq failed: %d\n", ret);
299 	}
300 
301 	/* reset all the states of crtc/plane/encoder/connector */
302 	drm_mode_config_reset(dev);
303 
304 	return 0;
305 
306 err:
307 	hibmc_unload(dev);
308 	drm_err(dev, "failed to initialize drm driver: %d\n", ret);
309 	return ret;
310 }
311 
hibmc_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)312 static int hibmc_pci_probe(struct pci_dev *pdev,
313 			   const struct pci_device_id *ent)
314 {
315 	struct hibmc_drm_private *priv;
316 	struct drm_device *dev;
317 	int ret;
318 
319 	ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &hibmc_driver);
320 	if (ret)
321 		return ret;
322 
323 	priv = devm_drm_dev_alloc(&pdev->dev, &hibmc_driver,
324 				  struct hibmc_drm_private, dev);
325 	if (IS_ERR(priv)) {
326 		DRM_ERROR("failed to allocate drm_device\n");
327 		return PTR_ERR(priv);
328 	}
329 
330 	dev = &priv->dev;
331 	pci_set_drvdata(pdev, dev);
332 
333 	ret = pcim_enable_device(pdev);
334 	if (ret) {
335 		drm_err(dev, "failed to enable pci device: %d\n", ret);
336 		goto err_return;
337 	}
338 
339 	ret = hibmc_load(dev);
340 	if (ret) {
341 		drm_err(dev, "failed to load hibmc: %d\n", ret);
342 		goto err_return;
343 	}
344 
345 	ret = drm_dev_register(dev, 0);
346 	if (ret) {
347 		drm_err(dev, "failed to register drv for userspace access: %d\n",
348 			  ret);
349 		goto err_unload;
350 	}
351 
352 	drm_fbdev_generic_setup(dev, dev->mode_config.preferred_depth);
353 
354 	return 0;
355 
356 err_unload:
357 	hibmc_unload(dev);
358 err_return:
359 	return ret;
360 }
361 
hibmc_pci_remove(struct pci_dev * pdev)362 static void hibmc_pci_remove(struct pci_dev *pdev)
363 {
364 	struct drm_device *dev = pci_get_drvdata(pdev);
365 
366 	drm_dev_unregister(dev);
367 	hibmc_unload(dev);
368 }
369 
370 static const struct pci_device_id hibmc_pci_table[] = {
371 	{ PCI_VDEVICE(HUAWEI, 0x1711) },
372 	{0,}
373 };
374 
375 static struct pci_driver hibmc_pci_driver = {
376 	.name =		"hibmc-drm",
377 	.id_table =	hibmc_pci_table,
378 	.probe =	hibmc_pci_probe,
379 	.remove =	hibmc_pci_remove,
380 	.driver.pm =    &hibmc_pm_ops,
381 };
382 
383 drm_module_pci_driver(hibmc_pci_driver);
384 
385 MODULE_DEVICE_TABLE(pci, hibmc_pci_table);
386 MODULE_AUTHOR("RongrongZou <zourongrong@huawei.com>");
387 MODULE_DESCRIPTION("DRM Driver for Hisilicon Hibmc");
388 MODULE_LICENSE("GPL v2");
389