1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <drm/drm_drv.h>
24 #include <linux/vmalloc.h>
25 #include "amdgpu.h"
26 #include "amdgpu_psp.h"
27 #include "amdgpu_ucode.h"
28 #include "soc15_common.h"
29 #include "psp_v13_0.h"
30
31 #include "mp/mp_13_0_2_offset.h"
32 #include "mp/mp_13_0_2_sh_mask.h"
33
34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
47 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
49
50 /* For large FW files the time to complete can be very long */
51 #define USBC_PD_POLLING_LIMIT_S 240
52
53 /* Read USB-PD from LFB */
54 #define GFX_CMD_USB_PD_USE_LFB 0x480
55
56 /* VBIOS gfl defines */
57 #define MBOX_READY_MASK 0x80000000
58 #define MBOX_STATUS_MASK 0x0000FFFF
59 #define MBOX_COMMAND_MASK 0x00FF0000
60 #define MBOX_READY_FLAG 0x80000000
61 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
62 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
63 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
64
65 /* memory training timeout define */
66 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
67
psp_v13_0_init_microcode(struct psp_context * psp)68 static int psp_v13_0_init_microcode(struct psp_context *psp)
69 {
70 struct amdgpu_device *adev = psp->adev;
71 const char *chip_name;
72 char ucode_prefix[30];
73 int err = 0;
74
75 switch (adev->ip_versions[MP0_HWIP][0]) {
76 case IP_VERSION(13, 0, 2):
77 chip_name = "aldebaran";
78 break;
79 case IP_VERSION(13, 0, 1):
80 case IP_VERSION(13, 0, 3):
81 chip_name = "yellow_carp";
82 break;
83 default:
84 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
85 chip_name = ucode_prefix;
86 break;
87 }
88
89 switch (adev->ip_versions[MP0_HWIP][0]) {
90 case IP_VERSION(13, 0, 2):
91 err = psp_init_sos_microcode(psp, chip_name);
92 if (err)
93 return err;
94 /* It's not necessary to load ras ta on Guest side */
95 if (!amdgpu_sriov_vf(adev)) {
96 err = psp_init_ta_microcode(&adev->psp, chip_name);
97 if (err)
98 return err;
99 }
100 break;
101 case IP_VERSION(13, 0, 1):
102 case IP_VERSION(13, 0, 3):
103 case IP_VERSION(13, 0, 5):
104 case IP_VERSION(13, 0, 8):
105 err = psp_init_toc_microcode(psp, chip_name);
106 if (err)
107 return err;
108 err = psp_init_ta_microcode(psp, chip_name);
109 if (err)
110 return err;
111 break;
112 case IP_VERSION(13, 0, 0):
113 case IP_VERSION(13, 0, 7):
114 case IP_VERSION(13, 0, 10):
115 err = psp_init_sos_microcode(psp, chip_name);
116 if (err)
117 return err;
118 /* It's not necessary to load ras ta on Guest side */
119 err = psp_init_ta_microcode(psp, chip_name);
120 if (err)
121 return err;
122 break;
123 default:
124 BUG();
125 }
126
127 return 0;
128 }
129
psp_v13_0_is_sos_alive(struct psp_context * psp)130 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
131 {
132 struct amdgpu_device *adev = psp->adev;
133 uint32_t sol_reg;
134
135 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
136
137 return sol_reg != 0x0;
138 }
139
psp_v13_0_wait_for_bootloader(struct psp_context * psp)140 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
141 {
142 struct amdgpu_device *adev = psp->adev;
143
144 int ret;
145 int retry_loop;
146
147 for (retry_loop = 0; retry_loop < 10; retry_loop++) {
148 /* Wait for bootloader to signify that is
149 ready having bit 31 of C2PMSG_35 set to 1 */
150 ret = psp_wait_for(psp,
151 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
152 0x80000000,
153 0x80000000,
154 false);
155
156 if (ret == 0)
157 return 0;
158 }
159
160 return ret;
161 }
162
psp_v13_0_bootloader_load_component(struct psp_context * psp,struct psp_bin_desc * bin_desc,enum psp_bootloader_cmd bl_cmd)163 static int psp_v13_0_bootloader_load_component(struct psp_context *psp,
164 struct psp_bin_desc *bin_desc,
165 enum psp_bootloader_cmd bl_cmd)
166 {
167 int ret;
168 uint32_t psp_gfxdrv_command_reg = 0;
169 struct amdgpu_device *adev = psp->adev;
170
171 /* Check tOS sign of life register to confirm sys driver and sOS
172 * are already been loaded.
173 */
174 if (psp_v13_0_is_sos_alive(psp))
175 return 0;
176
177 ret = psp_v13_0_wait_for_bootloader(psp);
178 if (ret)
179 return ret;
180
181 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
182
183 /* Copy PSP KDB binary to memory */
184 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
185
186 /* Provide the PSP KDB to bootloader */
187 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
188 (uint32_t)(psp->fw_pri_mc_addr >> 20));
189 psp_gfxdrv_command_reg = bl_cmd;
190 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
191 psp_gfxdrv_command_reg);
192
193 ret = psp_v13_0_wait_for_bootloader(psp);
194
195 return ret;
196 }
197
psp_v13_0_bootloader_load_kdb(struct psp_context * psp)198 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
199 {
200 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
201 }
202
psp_v13_0_bootloader_load_spl(struct psp_context * psp)203 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
204 {
205 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
206 }
207
psp_v13_0_bootloader_load_sysdrv(struct psp_context * psp)208 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
209 {
210 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
211 }
212
psp_v13_0_bootloader_load_soc_drv(struct psp_context * psp)213 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
214 {
215 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
216 }
217
psp_v13_0_bootloader_load_intf_drv(struct psp_context * psp)218 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
219 {
220 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
221 }
222
psp_v13_0_bootloader_load_dbg_drv(struct psp_context * psp)223 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
224 {
225 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
226 }
227
psp_v13_0_bootloader_load_ras_drv(struct psp_context * psp)228 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)
229 {
230 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
231 }
232
233
psp_v13_0_bootloader_load_sos(struct psp_context * psp)234 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
235 {
236 int ret;
237 unsigned int psp_gfxdrv_command_reg = 0;
238 struct amdgpu_device *adev = psp->adev;
239
240 /* Check sOS sign of life register to confirm sys driver and sOS
241 * are already been loaded.
242 */
243 if (psp_v13_0_is_sos_alive(psp))
244 return 0;
245
246 ret = psp_v13_0_wait_for_bootloader(psp);
247 if (ret)
248 return ret;
249
250 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
251
252 /* Copy Secure OS binary to PSP memory */
253 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
254
255 /* Provide the PSP secure OS to bootloader */
256 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
257 (uint32_t)(psp->fw_pri_mc_addr >> 20));
258 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
259 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
260 psp_gfxdrv_command_reg);
261
262 /* there might be handshake issue with hardware which needs delay */
263 mdelay(20);
264 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
265 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
266 0, true);
267
268 return ret;
269 }
270
psp_v13_0_ring_init(struct psp_context * psp,enum psp_ring_type ring_type)271 static int psp_v13_0_ring_init(struct psp_context *psp,
272 enum psp_ring_type ring_type)
273 {
274 int ret = 0;
275 struct psp_ring *ring;
276 struct amdgpu_device *adev = psp->adev;
277
278 ring = &psp->km_ring;
279
280 ring->ring_type = ring_type;
281
282 /* allocate 4k Page of Local Frame Buffer memory for ring */
283 ring->ring_size = 0x1000;
284 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
285 AMDGPU_GEM_DOMAIN_VRAM,
286 &adev->firmware.rbuf,
287 &ring->ring_mem_mc_addr,
288 (void **)&ring->ring_mem);
289 if (ret) {
290 ring->ring_size = 0;
291 return ret;
292 }
293
294 return 0;
295 }
296
psp_v13_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)297 static int psp_v13_0_ring_stop(struct psp_context *psp,
298 enum psp_ring_type ring_type)
299 {
300 int ret = 0;
301 struct amdgpu_device *adev = psp->adev;
302
303 if (amdgpu_sriov_vf(adev)) {
304 /* Write the ring destroy command*/
305 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
306 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
307 /* there might be handshake issue with hardware which needs delay */
308 mdelay(20);
309 /* Wait for response flag (bit 31) */
310 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
311 0x80000000, 0x80000000, false);
312 } else {
313 /* Write the ring destroy command*/
314 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
315 GFX_CTRL_CMD_ID_DESTROY_RINGS);
316 /* there might be handshake issue with hardware which needs delay */
317 mdelay(20);
318 /* Wait for response flag (bit 31) */
319 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
320 0x80000000, 0x80000000, false);
321 }
322
323 return ret;
324 }
325
psp_v13_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)326 static int psp_v13_0_ring_create(struct psp_context *psp,
327 enum psp_ring_type ring_type)
328 {
329 int ret = 0;
330 unsigned int psp_ring_reg = 0;
331 struct psp_ring *ring = &psp->km_ring;
332 struct amdgpu_device *adev = psp->adev;
333
334 if (amdgpu_sriov_vf(adev)) {
335 ret = psp_v13_0_ring_stop(psp, ring_type);
336 if (ret) {
337 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
338 return ret;
339 }
340
341 /* Write low address of the ring to C2PMSG_102 */
342 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
343 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
344 /* Write high address of the ring to C2PMSG_103 */
345 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
346 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
347
348 /* Write the ring initialization command to C2PMSG_101 */
349 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
350 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
351
352 /* there might be handshake issue with hardware which needs delay */
353 mdelay(20);
354
355 /* Wait for response flag (bit 31) in C2PMSG_101 */
356 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
357 0x80000000, 0x8000FFFF, false);
358
359 } else {
360 /* Wait for sOS ready for ring creation */
361 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
362 0x80000000, 0x80000000, false);
363 if (ret) {
364 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
365 return ret;
366 }
367
368 /* Write low address of the ring to C2PMSG_69 */
369 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
370 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
371 /* Write high address of the ring to C2PMSG_70 */
372 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
373 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
374 /* Write size of ring to C2PMSG_71 */
375 psp_ring_reg = ring->ring_size;
376 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
377 /* Write the ring initialization command to C2PMSG_64 */
378 psp_ring_reg = ring_type;
379 psp_ring_reg = psp_ring_reg << 16;
380 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
381
382 /* there might be handshake issue with hardware which needs delay */
383 mdelay(20);
384
385 /* Wait for response flag (bit 31) in C2PMSG_64 */
386 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
387 0x80000000, 0x8000FFFF, false);
388 }
389
390 return ret;
391 }
392
psp_v13_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)393 static int psp_v13_0_ring_destroy(struct psp_context *psp,
394 enum psp_ring_type ring_type)
395 {
396 int ret = 0;
397 struct psp_ring *ring = &psp->km_ring;
398 struct amdgpu_device *adev = psp->adev;
399
400 ret = psp_v13_0_ring_stop(psp, ring_type);
401 if (ret)
402 DRM_ERROR("Fail to stop psp ring\n");
403
404 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
405 &ring->ring_mem_mc_addr,
406 (void **)&ring->ring_mem);
407
408 return ret;
409 }
410
psp_v13_0_ring_get_wptr(struct psp_context * psp)411 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
412 {
413 uint32_t data;
414 struct amdgpu_device *adev = psp->adev;
415
416 if (amdgpu_sriov_vf(adev))
417 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
418 else
419 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
420
421 return data;
422 }
423
psp_v13_0_ring_set_wptr(struct psp_context * psp,uint32_t value)424 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
425 {
426 struct amdgpu_device *adev = psp->adev;
427
428 if (amdgpu_sriov_vf(adev)) {
429 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
430 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
431 GFX_CTRL_CMD_ID_CONSUME_CMD);
432 } else
433 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
434 }
435
psp_v13_0_memory_training_send_msg(struct psp_context * psp,int msg)436 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
437 {
438 int ret;
439 int i;
440 uint32_t data_32;
441 int max_wait;
442 struct amdgpu_device *adev = psp->adev;
443
444 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
445 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
446 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
447
448 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
449 for (i = 0; i < max_wait; i++) {
450 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
451 0x80000000, 0x80000000, false);
452 if (ret == 0)
453 break;
454 }
455 if (i < max_wait)
456 ret = 0;
457 else
458 ret = -ETIME;
459
460 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
461 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
462 (ret == 0) ? "succeed" : "failed",
463 i, adev->usec_timeout/1000);
464 return ret;
465 }
466
467
psp_v13_0_memory_training(struct psp_context * psp,uint32_t ops)468 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
469 {
470 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
471 uint32_t *pcache = (uint32_t *)ctx->sys_cache;
472 struct amdgpu_device *adev = psp->adev;
473 uint32_t p2c_header[4];
474 uint32_t sz;
475 void *buf;
476 int ret, idx;
477
478 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
479 dev_dbg(adev->dev, "Memory training is not supported.\n");
480 return 0;
481 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
482 dev_err(adev->dev, "Memory training initialization failure.\n");
483 return -EINVAL;
484 }
485
486 if (psp_v13_0_is_sos_alive(psp)) {
487 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
488 return 0;
489 }
490
491 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
492 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
493 pcache[0], pcache[1], pcache[2], pcache[3],
494 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
495
496 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
497 dev_dbg(adev->dev, "Short training depends on restore.\n");
498 ops |= PSP_MEM_TRAIN_RESTORE;
499 }
500
501 if ((ops & PSP_MEM_TRAIN_RESTORE) &&
502 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
503 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
504 ops |= PSP_MEM_TRAIN_SAVE;
505 }
506
507 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
508 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
509 pcache[3] == p2c_header[3])) {
510 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
511 ops |= PSP_MEM_TRAIN_SAVE;
512 }
513
514 if ((ops & PSP_MEM_TRAIN_SAVE) &&
515 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
516 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
517 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
518 }
519
520 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
521 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
522 ops |= PSP_MEM_TRAIN_SAVE;
523 }
524
525 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
526
527 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
528 /*
529 * Long training will encroach a certain amount on the bottom of VRAM;
530 * save the content from the bottom of VRAM to system memory
531 * before training, and restore it after training to avoid
532 * VRAM corruption.
533 */
534 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
535
536 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
537 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
538 adev->gmc.visible_vram_size,
539 adev->mman.aper_base_kaddr);
540 return -EINVAL;
541 }
542
543 buf = vmalloc(sz);
544 if (!buf) {
545 dev_err(adev->dev, "failed to allocate system memory.\n");
546 return -ENOMEM;
547 }
548
549 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
550 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
551 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
552 if (ret) {
553 DRM_ERROR("Send long training msg failed.\n");
554 vfree(buf);
555 drm_dev_exit(idx);
556 return ret;
557 }
558
559 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
560 adev->hdp.funcs->flush_hdp(adev, NULL);
561 vfree(buf);
562 drm_dev_exit(idx);
563 } else {
564 vfree(buf);
565 return -ENODEV;
566 }
567 }
568
569 if (ops & PSP_MEM_TRAIN_SAVE) {
570 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
571 }
572
573 if (ops & PSP_MEM_TRAIN_RESTORE) {
574 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
575 }
576
577 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
578 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
579 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
580 if (ret) {
581 dev_err(adev->dev, "send training msg failed.\n");
582 return ret;
583 }
584 }
585 ctx->training_cnt++;
586 return 0;
587 }
588
psp_v13_0_load_usbc_pd_fw(struct psp_context * psp,uint64_t fw_pri_mc_addr)589 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
590 {
591 struct amdgpu_device *adev = psp->adev;
592 uint32_t reg_status;
593 int ret, i = 0;
594
595 /*
596 * LFB address which is aligned to 1MB address and has to be
597 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
598 * register
599 */
600 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
601
602 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
603 0x80000000, 0x80000000, false);
604 if (ret)
605 return ret;
606
607 /* Fireup interrupt so PSP can pick up the address */
608 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
609
610 /* FW load takes very long time */
611 do {
612 msleep(1000);
613 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
614
615 if (reg_status & 0x80000000)
616 goto done;
617
618 } while (++i < USBC_PD_POLLING_LIMIT_S);
619
620 return -ETIME;
621 done:
622
623 if ((reg_status & 0xFFFF) != 0) {
624 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
625 reg_status & 0xFFFF);
626 return -EIO;
627 }
628
629 return 0;
630 }
631
psp_v13_0_read_usbc_pd_fw(struct psp_context * psp,uint32_t * fw_ver)632 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
633 {
634 struct amdgpu_device *adev = psp->adev;
635 int ret;
636
637 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
638
639 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
640 0x80000000, 0x80000000, false);
641 if (!ret)
642 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
643
644 return ret;
645 }
646
psp_v13_0_exec_spi_cmd(struct psp_context * psp,int cmd)647 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
648 {
649 uint32_t reg_status = 0, reg_val = 0;
650 struct amdgpu_device *adev = psp->adev;
651 int ret;
652
653 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
654 reg_val |= (cmd << 16);
655 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val);
656
657 /* Ring the doorbell */
658 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
659
660 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
661 return 0;
662
663 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
664 MBOX_READY_FLAG, MBOX_READY_MASK, false);
665 if (ret) {
666 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
667 return ret;
668 }
669
670 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
671 if ((reg_status & 0xFFFF) != 0) {
672 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
673 cmd, reg_status & 0xFFFF);
674 return -EIO;
675 }
676
677 return 0;
678 }
679
psp_v13_0_update_spirom(struct psp_context * psp,uint64_t fw_pri_mc_addr)680 static int psp_v13_0_update_spirom(struct psp_context *psp,
681 uint64_t fw_pri_mc_addr)
682 {
683 struct amdgpu_device *adev = psp->adev;
684 int ret;
685
686 /* Confirm PSP is ready to start */
687 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
688 MBOX_READY_FLAG, MBOX_READY_MASK, false);
689 if (ret) {
690 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
691 return ret;
692 }
693
694 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
695
696 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
697 if (ret)
698 return ret;
699
700 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
701
702 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
703 if (ret)
704 return ret;
705
706 psp->vbflash_done = true;
707
708 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
709 if (ret)
710 return ret;
711
712 return 0;
713 }
714
psp_v13_0_vbflash_status(struct psp_context * psp)715 static int psp_v13_0_vbflash_status(struct psp_context *psp)
716 {
717 struct amdgpu_device *adev = psp->adev;
718
719 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
720 }
721
722 static const struct psp_funcs psp_v13_0_funcs = {
723 .init_microcode = psp_v13_0_init_microcode,
724 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
725 .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
726 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
727 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
728 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
729 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
730 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv,
731 .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
732 .ring_init = psp_v13_0_ring_init,
733 .ring_create = psp_v13_0_ring_create,
734 .ring_stop = psp_v13_0_ring_stop,
735 .ring_destroy = psp_v13_0_ring_destroy,
736 .ring_get_wptr = psp_v13_0_ring_get_wptr,
737 .ring_set_wptr = psp_v13_0_ring_set_wptr,
738 .mem_training = psp_v13_0_memory_training,
739 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
740 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
741 .update_spirom = psp_v13_0_update_spirom,
742 .vbflash_stat = psp_v13_0_vbflash_status
743 };
744
psp_v13_0_set_psp_funcs(struct psp_context * psp)745 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
746 {
747 psp->funcs = &psp_v13_0_funcs;
748 }
749
