1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016-2022 NVIDIA Corporation
4 *
5 * Author: Thierry Reding <treding@nvidia.com>
6 * Dipen Patel <dpatel@nvidia.com>
7 */
8
9 #include <linux/gpio/driver.h>
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include <linux/hte.h>
16
17 #include <dt-bindings/gpio/tegra186-gpio.h>
18 #include <dt-bindings/gpio/tegra194-gpio.h>
19 #include <dt-bindings/gpio/tegra234-gpio.h>
20 #include <dt-bindings/gpio/tegra241-gpio.h>
21
22 /* security registers */
23 #define TEGRA186_GPIO_CTL_SCR 0x0c
24 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
25 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
26
27 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
28
29 /* control registers */
30 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
31 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
32 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
33 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
34 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
35 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
36 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
37 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
38 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
39 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
40 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
41 #define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7)
42
43 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
44 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
45
46 #define TEGRA186_GPIO_INPUT 0x08
47 #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
48
49 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
50 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
51
52 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
53 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
54
55 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
56
57 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
58
59 struct tegra_gpio_port {
60 const char *name;
61 unsigned int bank;
62 unsigned int port;
63 unsigned int pins;
64 };
65
66 struct tegra186_pin_range {
67 unsigned int offset;
68 const char *group;
69 };
70
71 struct tegra_gpio_soc {
72 const struct tegra_gpio_port *ports;
73 unsigned int num_ports;
74 const char *name;
75 unsigned int instance;
76
77 unsigned int num_irqs_per_bank;
78
79 const struct tegra186_pin_range *pin_ranges;
80 unsigned int num_pin_ranges;
81 const char *pinmux;
82 bool has_gte;
83 };
84
85 struct tegra_gpio {
86 struct gpio_chip gpio;
87 unsigned int num_irq;
88 unsigned int *irq;
89
90 const struct tegra_gpio_soc *soc;
91 unsigned int num_irqs_per_bank;
92 unsigned int num_banks;
93
94 void __iomem *secure;
95 void __iomem *base;
96 };
97
98 static const struct tegra_gpio_port *
tegra186_gpio_get_port(struct tegra_gpio * gpio,unsigned int * pin)99 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
100 {
101 unsigned int start = 0, i;
102
103 for (i = 0; i < gpio->soc->num_ports; i++) {
104 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
105
106 if (*pin >= start && *pin < start + port->pins) {
107 *pin -= start;
108 return port;
109 }
110
111 start += port->pins;
112 }
113
114 return NULL;
115 }
116
tegra186_gpio_get_base(struct tegra_gpio * gpio,unsigned int pin)117 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
118 unsigned int pin)
119 {
120 const struct tegra_gpio_port *port;
121 unsigned int offset;
122
123 port = tegra186_gpio_get_port(gpio, &pin);
124 if (!port)
125 return NULL;
126
127 offset = port->bank * 0x1000 + port->port * 0x200;
128
129 return gpio->base + offset + pin * 0x20;
130 }
131
tegra186_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)132 static int tegra186_gpio_get_direction(struct gpio_chip *chip,
133 unsigned int offset)
134 {
135 struct tegra_gpio *gpio = gpiochip_get_data(chip);
136 void __iomem *base;
137 u32 value;
138
139 base = tegra186_gpio_get_base(gpio, offset);
140 if (WARN_ON(base == NULL))
141 return -ENODEV;
142
143 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
144 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
145 return GPIO_LINE_DIRECTION_OUT;
146
147 return GPIO_LINE_DIRECTION_IN;
148 }
149
tegra186_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)150 static int tegra186_gpio_direction_input(struct gpio_chip *chip,
151 unsigned int offset)
152 {
153 struct tegra_gpio *gpio = gpiochip_get_data(chip);
154 void __iomem *base;
155 u32 value;
156
157 base = tegra186_gpio_get_base(gpio, offset);
158 if (WARN_ON(base == NULL))
159 return -ENODEV;
160
161 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
162 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
163 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
164
165 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
166 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
167 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
168 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
169
170 return 0;
171 }
172
tegra186_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int level)173 static int tegra186_gpio_direction_output(struct gpio_chip *chip,
174 unsigned int offset, int level)
175 {
176 struct tegra_gpio *gpio = gpiochip_get_data(chip);
177 void __iomem *base;
178 u32 value;
179
180 /* configure output level first */
181 chip->set(chip, offset, level);
182
183 base = tegra186_gpio_get_base(gpio, offset);
184 if (WARN_ON(base == NULL))
185 return -EINVAL;
186
187 /* set the direction */
188 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
189 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
190 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
191
192 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
193 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
194 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
195 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
196
197 return 0;
198 }
199
200 #define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS)
201
tegra186_gpio_en_hw_ts(struct gpio_chip * gc,u32 offset,unsigned long flags)202 static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset,
203 unsigned long flags)
204 {
205 struct tegra_gpio *gpio;
206 void __iomem *base;
207 int value;
208
209 if (!gc)
210 return -EINVAL;
211
212 gpio = gpiochip_get_data(gc);
213 if (!gpio)
214 return -ENODEV;
215
216 base = tegra186_gpio_get_base(gpio, offset);
217 if (WARN_ON(base == NULL))
218 return -EINVAL;
219
220 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
221 value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
222
223 if (flags == HTE_BOTH_EDGES) {
224 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
225 } else if (flags == HTE_RISING_EDGE_TS) {
226 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
227 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
228 } else if (flags == HTE_FALLING_EDGE_TS) {
229 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
230 }
231
232 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
233
234 return 0;
235 }
236
tegra186_gpio_dis_hw_ts(struct gpio_chip * gc,u32 offset,unsigned long flags)237 static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset,
238 unsigned long flags)
239 {
240 struct tegra_gpio *gpio;
241 void __iomem *base;
242 int value;
243
244 if (!gc)
245 return -EINVAL;
246
247 gpio = gpiochip_get_data(gc);
248 if (!gpio)
249 return -ENODEV;
250
251 base = tegra186_gpio_get_base(gpio, offset);
252 if (WARN_ON(base == NULL))
253 return -EINVAL;
254
255 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
256 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
257 if (flags == HTE_BOTH_EDGES) {
258 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
259 } else if (flags == HTE_RISING_EDGE_TS) {
260 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
261 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
262 } else if (flags == HTE_FALLING_EDGE_TS) {
263 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
264 }
265 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
266
267 return 0;
268 }
269
tegra186_gpio_get(struct gpio_chip * chip,unsigned int offset)270 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
271 {
272 struct tegra_gpio *gpio = gpiochip_get_data(chip);
273 void __iomem *base;
274 u32 value;
275
276 base = tegra186_gpio_get_base(gpio, offset);
277 if (WARN_ON(base == NULL))
278 return -ENODEV;
279
280 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
281 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
282 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
283 else
284 value = readl(base + TEGRA186_GPIO_INPUT);
285
286 return value & BIT(0);
287 }
288
tegra186_gpio_set(struct gpio_chip * chip,unsigned int offset,int level)289 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
290 int level)
291 {
292 struct tegra_gpio *gpio = gpiochip_get_data(chip);
293 void __iomem *base;
294 u32 value;
295
296 base = tegra186_gpio_get_base(gpio, offset);
297 if (WARN_ON(base == NULL))
298 return;
299
300 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
301 if (level == 0)
302 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
303 else
304 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
305
306 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
307 }
308
tegra186_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)309 static int tegra186_gpio_set_config(struct gpio_chip *chip,
310 unsigned int offset,
311 unsigned long config)
312 {
313 struct tegra_gpio *gpio = gpiochip_get_data(chip);
314 u32 debounce, value;
315 void __iomem *base;
316
317 base = tegra186_gpio_get_base(gpio, offset);
318 if (base == NULL)
319 return -ENXIO;
320
321 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
322 return -ENOTSUPP;
323
324 debounce = pinconf_to_config_argument(config);
325
326 /*
327 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
328 * time.
329 */
330 if (debounce > 255000)
331 return -EINVAL;
332
333 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
334
335 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
336 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
337
338 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
339 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
340 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
341
342 return 0;
343 }
344
tegra186_gpio_add_pin_ranges(struct gpio_chip * chip)345 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
346 {
347 struct tegra_gpio *gpio = gpiochip_get_data(chip);
348 struct pinctrl_dev *pctldev;
349 struct device_node *np;
350 unsigned int i, j;
351 int err;
352
353 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
354 return 0;
355
356 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
357 if (!np)
358 return -ENODEV;
359
360 pctldev = of_pinctrl_get(np);
361 of_node_put(np);
362 if (!pctldev)
363 return -EPROBE_DEFER;
364
365 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
366 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
367 const char *group = gpio->soc->pin_ranges[i].group;
368
369 port = pin / 8;
370 pin = pin % 8;
371
372 if (port >= gpio->soc->num_ports) {
373 dev_warn(chip->parent, "invalid port %u for %s\n",
374 port, group);
375 continue;
376 }
377
378 for (j = 0; j < port; j++)
379 pin += gpio->soc->ports[j].pins;
380
381 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
382 if (err < 0)
383 return err;
384 }
385
386 return 0;
387 }
388
tegra186_gpio_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * spec,u32 * flags)389 static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
390 const struct of_phandle_args *spec,
391 u32 *flags)
392 {
393 struct tegra_gpio *gpio = gpiochip_get_data(chip);
394 unsigned int port, pin, i, offset = 0;
395
396 if (WARN_ON(chip->of_gpio_n_cells < 2))
397 return -EINVAL;
398
399 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
400 return -EINVAL;
401
402 port = spec->args[0] / 8;
403 pin = spec->args[0] % 8;
404
405 if (port >= gpio->soc->num_ports) {
406 dev_err(chip->parent, "invalid port number: %u\n", port);
407 return -EINVAL;
408 }
409
410 for (i = 0; i < port; i++)
411 offset += gpio->soc->ports[i].pins;
412
413 if (flags)
414 *flags = spec->args[1];
415
416 return offset + pin;
417 }
418
419 #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
420
tegra186_irq_ack(struct irq_data * data)421 static void tegra186_irq_ack(struct irq_data *data)
422 {
423 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
424 struct tegra_gpio *gpio = to_tegra_gpio(gc);
425 void __iomem *base;
426
427 base = tegra186_gpio_get_base(gpio, data->hwirq);
428 if (WARN_ON(base == NULL))
429 return;
430
431 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
432 }
433
tegra186_irq_mask(struct irq_data * data)434 static void tegra186_irq_mask(struct irq_data *data)
435 {
436 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
437 struct tegra_gpio *gpio = to_tegra_gpio(gc);
438 void __iomem *base;
439 u32 value;
440
441 base = tegra186_gpio_get_base(gpio, data->hwirq);
442 if (WARN_ON(base == NULL))
443 return;
444
445 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
446 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
447 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
448
449 gpiochip_disable_irq(&gpio->gpio, data->hwirq);
450 }
451
tegra186_irq_unmask(struct irq_data * data)452 static void tegra186_irq_unmask(struct irq_data *data)
453 {
454 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
455 struct tegra_gpio *gpio = to_tegra_gpio(gc);
456 void __iomem *base;
457 u32 value;
458
459 base = tegra186_gpio_get_base(gpio, data->hwirq);
460 if (WARN_ON(base == NULL))
461 return;
462
463 gpiochip_enable_irq(&gpio->gpio, data->hwirq);
464
465 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
466 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
467 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
468 }
469
tegra186_irq_set_type(struct irq_data * data,unsigned int type)470 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
471 {
472 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
473 struct tegra_gpio *gpio = to_tegra_gpio(gc);
474 void __iomem *base;
475 u32 value;
476
477 base = tegra186_gpio_get_base(gpio, data->hwirq);
478 if (WARN_ON(base == NULL))
479 return -ENODEV;
480
481 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
482 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
483 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
484
485 switch (type & IRQ_TYPE_SENSE_MASK) {
486 case IRQ_TYPE_NONE:
487 break;
488
489 case IRQ_TYPE_EDGE_RISING:
490 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
491 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
492 break;
493
494 case IRQ_TYPE_EDGE_FALLING:
495 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
496 break;
497
498 case IRQ_TYPE_EDGE_BOTH:
499 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
500 break;
501
502 case IRQ_TYPE_LEVEL_HIGH:
503 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
504 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
505 break;
506
507 case IRQ_TYPE_LEVEL_LOW:
508 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
509 break;
510
511 default:
512 return -EINVAL;
513 }
514
515 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
516
517 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
518 irq_set_handler_locked(data, handle_level_irq);
519 else
520 irq_set_handler_locked(data, handle_edge_irq);
521
522 if (data->parent_data)
523 return irq_chip_set_type_parent(data, type);
524
525 return 0;
526 }
527
tegra186_irq_set_wake(struct irq_data * data,unsigned int on)528 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
529 {
530 if (data->parent_data)
531 return irq_chip_set_wake_parent(data, on);
532
533 return 0;
534 }
535
tegra186_irq_print_chip(struct irq_data * data,struct seq_file * p)536 static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p)
537 {
538 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
539
540 seq_printf(p, dev_name(gc->parent));
541 }
542
543 static const struct irq_chip tegra186_gpio_irq_chip = {
544 .irq_ack = tegra186_irq_ack,
545 .irq_mask = tegra186_irq_mask,
546 .irq_unmask = tegra186_irq_unmask,
547 .irq_set_type = tegra186_irq_set_type,
548 .irq_set_wake = tegra186_irq_set_wake,
549 .irq_print_chip = tegra186_irq_print_chip,
550 .flags = IRQCHIP_IMMUTABLE,
551 GPIOCHIP_IRQ_RESOURCE_HELPERS,
552 };
553
tegra186_gpio_irq(struct irq_desc * desc)554 static void tegra186_gpio_irq(struct irq_desc *desc)
555 {
556 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
557 struct irq_domain *domain = gpio->gpio.irq.domain;
558 struct irq_chip *chip = irq_desc_get_chip(desc);
559 unsigned int parent = irq_desc_get_irq(desc);
560 unsigned int i, j, offset = 0;
561
562 chained_irq_enter(chip, desc);
563
564 for (i = 0; i < gpio->soc->num_ports; i++) {
565 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
566 unsigned int pin;
567 unsigned long value;
568 void __iomem *base;
569
570 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
571
572 /* skip ports that are not associated with this bank */
573 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
574 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
575 break;
576 }
577
578 if (j == gpio->num_irqs_per_bank)
579 goto skip;
580
581 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
582
583 for_each_set_bit(pin, &value, port->pins) {
584 int ret = generic_handle_domain_irq(domain, offset + pin);
585 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
586 }
587
588 skip:
589 offset += port->pins;
590 }
591
592 chained_irq_exit(chip, desc);
593 }
594
tegra186_gpio_irq_domain_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)595 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
596 struct irq_fwspec *fwspec,
597 unsigned long *hwirq,
598 unsigned int *type)
599 {
600 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
601 unsigned int port, pin, i, offset = 0;
602
603 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
604 return -EINVAL;
605
606 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
607 return -EINVAL;
608
609 port = fwspec->param[0] / 8;
610 pin = fwspec->param[0] % 8;
611
612 if (port >= gpio->soc->num_ports)
613 return -EINVAL;
614
615 for (i = 0; i < port; i++)
616 offset += gpio->soc->ports[i].pins;
617
618 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
619 *hwirq = offset + pin;
620
621 return 0;
622 }
623
tegra186_gpio_populate_parent_fwspec(struct gpio_chip * chip,union gpio_irq_fwspec * gfwspec,unsigned int parent_hwirq,unsigned int parent_type)624 static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
625 union gpio_irq_fwspec *gfwspec,
626 unsigned int parent_hwirq,
627 unsigned int parent_type)
628 {
629 struct tegra_gpio *gpio = gpiochip_get_data(chip);
630 struct irq_fwspec *fwspec = &gfwspec->fwspec;
631
632 fwspec->fwnode = chip->irq.parent_domain->fwnode;
633 fwspec->param_count = 3;
634 fwspec->param[0] = gpio->soc->instance;
635 fwspec->param[1] = parent_hwirq;
636 fwspec->param[2] = parent_type;
637
638 return 0;
639 }
640
tegra186_gpio_child_to_parent_hwirq(struct gpio_chip * chip,unsigned int hwirq,unsigned int type,unsigned int * parent_hwirq,unsigned int * parent_type)641 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
642 unsigned int hwirq,
643 unsigned int type,
644 unsigned int *parent_hwirq,
645 unsigned int *parent_type)
646 {
647 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
648 *parent_type = type;
649
650 return 0;
651 }
652
tegra186_gpio_child_offset_to_irq(struct gpio_chip * chip,unsigned int offset)653 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
654 unsigned int offset)
655 {
656 struct tegra_gpio *gpio = gpiochip_get_data(chip);
657 unsigned int i;
658
659 for (i = 0; i < gpio->soc->num_ports; i++) {
660 if (offset < gpio->soc->ports[i].pins)
661 break;
662
663 offset -= gpio->soc->ports[i].pins;
664 }
665
666 return offset + i * 8;
667 }
668
669 static const struct of_device_id tegra186_pmc_of_match[] = {
670 { .compatible = "nvidia,tegra186-pmc" },
671 { .compatible = "nvidia,tegra194-pmc" },
672 { /* sentinel */ }
673 };
674
tegra186_gpio_init_route_mapping(struct tegra_gpio * gpio)675 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
676 {
677 struct device *dev = gpio->gpio.parent;
678 unsigned int i, j;
679 u32 value;
680
681 for (i = 0; i < gpio->soc->num_ports; i++) {
682 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
683 unsigned int offset, p = port->port;
684 void __iomem *base;
685
686 base = gpio->secure + port->bank * 0x1000 + 0x800;
687
688 value = readl(base + TEGRA186_GPIO_CTL_SCR);
689
690 /*
691 * For controllers that haven't been locked down yet, make
692 * sure to program the default interrupt route mapping.
693 */
694 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
695 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
696 /*
697 * On Tegra194 and later, each pin can be routed to one or more
698 * interrupts.
699 */
700 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
701 dev_dbg(dev, "programming default interrupt routing for port %s\n",
702 port->name);
703
704 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
705
706 /*
707 * By default we only want to route GPIO pins to IRQ 0. This works
708 * only under the assumption that we're running as the host kernel
709 * and hence all GPIO pins are owned by Linux.
710 *
711 * For cases where Linux is the guest OS, the hypervisor will have
712 * to configure the interrupt routing and pass only the valid
713 * interrupts via device tree.
714 */
715 if (j == 0) {
716 value = readl(base + offset);
717 value = BIT(port->pins) - 1;
718 writel(value, base + offset);
719 }
720 }
721 }
722 }
723 }
724
tegra186_gpio_irqs_per_bank(struct tegra_gpio * gpio)725 static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio)
726 {
727 struct device *dev = gpio->gpio.parent;
728
729 if (gpio->num_irq > gpio->num_banks) {
730 if (gpio->num_irq % gpio->num_banks != 0)
731 goto error;
732 }
733
734 if (gpio->num_irq < gpio->num_banks)
735 goto error;
736
737 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
738
739 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank)
740 goto error;
741
742 return 0;
743
744 error:
745 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n",
746 gpio->num_irq, gpio->num_banks);
747 return -EINVAL;
748 }
749
tegra186_gpio_probe(struct platform_device * pdev)750 static int tegra186_gpio_probe(struct platform_device *pdev)
751 {
752 unsigned int i, j, offset;
753 struct gpio_irq_chip *irq;
754 struct tegra_gpio *gpio;
755 struct device_node *np;
756 char **names;
757 int err;
758
759 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
760 if (!gpio)
761 return -ENOMEM;
762
763 gpio->soc = device_get_match_data(&pdev->dev);
764 gpio->gpio.label = gpio->soc->name;
765 gpio->gpio.parent = &pdev->dev;
766
767 /* count the number of banks in the controller */
768 for (i = 0; i < gpio->soc->num_ports; i++)
769 if (gpio->soc->ports[i].bank > gpio->num_banks)
770 gpio->num_banks = gpio->soc->ports[i].bank;
771
772 gpio->num_banks++;
773
774 /* get register apertures */
775 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
776 if (IS_ERR(gpio->secure)) {
777 gpio->secure = devm_platform_ioremap_resource(pdev, 0);
778 if (IS_ERR(gpio->secure))
779 return PTR_ERR(gpio->secure);
780 }
781
782 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
783 if (IS_ERR(gpio->base)) {
784 gpio->base = devm_platform_ioremap_resource(pdev, 1);
785 if (IS_ERR(gpio->base))
786 return PTR_ERR(gpio->base);
787 }
788
789 err = platform_irq_count(pdev);
790 if (err < 0)
791 return err;
792
793 gpio->num_irq = err;
794
795 err = tegra186_gpio_irqs_per_bank(gpio);
796 if (err < 0)
797 return err;
798
799 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
800 GFP_KERNEL);
801 if (!gpio->irq)
802 return -ENOMEM;
803
804 for (i = 0; i < gpio->num_irq; i++) {
805 err = platform_get_irq(pdev, i);
806 if (err < 0)
807 return err;
808
809 gpio->irq[i] = err;
810 }
811
812 gpio->gpio.request = gpiochip_generic_request;
813 gpio->gpio.free = gpiochip_generic_free;
814 gpio->gpio.get_direction = tegra186_gpio_get_direction;
815 gpio->gpio.direction_input = tegra186_gpio_direction_input;
816 gpio->gpio.direction_output = tegra186_gpio_direction_output;
817 gpio->gpio.get = tegra186_gpio_get;
818 gpio->gpio.set = tegra186_gpio_set;
819 gpio->gpio.set_config = tegra186_gpio_set_config;
820 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
821 if (gpio->soc->has_gte) {
822 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts;
823 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts;
824 }
825
826 gpio->gpio.base = -1;
827
828 for (i = 0; i < gpio->soc->num_ports; i++)
829 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
830
831 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
832 sizeof(*names), GFP_KERNEL);
833 if (!names)
834 return -ENOMEM;
835
836 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
837 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
838 char *name;
839
840 for (j = 0; j < port->pins; j++) {
841 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
842 "P%s.%02x", port->name, j);
843 if (!name)
844 return -ENOMEM;
845
846 names[offset + j] = name;
847 }
848
849 offset += port->pins;
850 }
851
852 gpio->gpio.names = (const char * const *)names;
853
854 #if defined(CONFIG_OF_GPIO)
855 gpio->gpio.of_gpio_n_cells = 2;
856 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
857 #endif /* CONFIG_OF_GPIO */
858
859 irq = &gpio->gpio.irq;
860 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip);
861 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
862 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
863 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
864 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
865 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
866 irq->handler = handle_simple_irq;
867 irq->default_type = IRQ_TYPE_NONE;
868 irq->parent_handler = tegra186_gpio_irq;
869 irq->parent_handler_data = gpio;
870 irq->num_parents = gpio->num_irq;
871
872 /*
873 * To simplify things, use a single interrupt per bank for now. Some
874 * chips support up to 8 interrupts per bank, which can be useful to
875 * distribute the load and decrease the processing latency for GPIOs
876 * but it also requires a more complicated interrupt routing than we
877 * currently program.
878 */
879 if (gpio->num_irqs_per_bank > 1) {
880 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,
881 sizeof(*irq->parents), GFP_KERNEL);
882 if (!irq->parents)
883 return -ENOMEM;
884
885 for (i = 0; i < gpio->num_banks; i++)
886 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank];
887
888 irq->num_parents = gpio->num_banks;
889 } else {
890 irq->num_parents = gpio->num_irq;
891 irq->parents = gpio->irq;
892 }
893
894 if (gpio->soc->num_irqs_per_bank > 1)
895 tegra186_gpio_init_route_mapping(gpio);
896
897 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
898 if (np) {
899 irq->parent_domain = irq_find_host(np);
900 of_node_put(np);
901
902 if (!irq->parent_domain)
903 return -EPROBE_DEFER;
904 }
905
906 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
907 sizeof(*irq->map), GFP_KERNEL);
908 if (!irq->map)
909 return -ENOMEM;
910
911 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
912 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
913
914 for (j = 0; j < port->pins; j++)
915 irq->map[offset + j] = irq->parents[port->bank];
916
917 offset += port->pins;
918 }
919
920 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
921 }
922
923 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
924 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
925 .name = #_name, \
926 .bank = _bank, \
927 .port = _port, \
928 .pins = _pins, \
929 }
930
931 static const struct tegra_gpio_port tegra186_main_ports[] = {
932 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
933 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
934 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
935 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
936 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
937 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
938 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
939 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
940 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
941 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
942 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
943 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
944 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
945 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
946 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
947 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
948 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
949 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
950 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
951 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
952 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
953 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
954 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
955 };
956
957 static const struct tegra_gpio_soc tegra186_main_soc = {
958 .num_ports = ARRAY_SIZE(tegra186_main_ports),
959 .ports = tegra186_main_ports,
960 .name = "tegra186-gpio",
961 .instance = 0,
962 .num_irqs_per_bank = 1,
963 };
964
965 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
966 [TEGRA186_AON_GPIO_PORT_##_name] = { \
967 .name = #_name, \
968 .bank = _bank, \
969 .port = _port, \
970 .pins = _pins, \
971 }
972
973 static const struct tegra_gpio_port tegra186_aon_ports[] = {
974 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
975 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
976 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
977 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
978 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
979 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
980 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
981 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
982 };
983
984 static const struct tegra_gpio_soc tegra186_aon_soc = {
985 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
986 .ports = tegra186_aon_ports,
987 .name = "tegra186-gpio-aon",
988 .instance = 1,
989 .num_irqs_per_bank = 1,
990 };
991
992 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
993 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
994 .name = #_name, \
995 .bank = _bank, \
996 .port = _port, \
997 .pins = _pins, \
998 }
999
1000 static const struct tegra_gpio_port tegra194_main_ports[] = {
1001 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
1002 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
1003 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
1004 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
1005 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
1006 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
1007 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
1008 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
1009 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
1010 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
1011 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
1012 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
1013 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
1014 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
1015 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
1016 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
1017 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
1018 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
1019 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
1020 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
1021 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
1022 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
1023 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
1024 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
1025 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
1026 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
1027 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
1028 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
1029 };
1030
1031 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
1032 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
1033 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
1034 };
1035
1036 static const struct tegra_gpio_soc tegra194_main_soc = {
1037 .num_ports = ARRAY_SIZE(tegra194_main_ports),
1038 .ports = tegra194_main_ports,
1039 .name = "tegra194-gpio",
1040 .instance = 0,
1041 .num_irqs_per_bank = 8,
1042 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
1043 .pin_ranges = tegra194_main_pin_ranges,
1044 .pinmux = "nvidia,tegra194-pinmux",
1045 };
1046
1047 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1048 [TEGRA194_AON_GPIO_PORT_##_name] = { \
1049 .name = #_name, \
1050 .bank = _bank, \
1051 .port = _port, \
1052 .pins = _pins, \
1053 }
1054
1055 static const struct tegra_gpio_port tegra194_aon_ports[] = {
1056 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
1057 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
1058 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
1059 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
1060 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
1061 };
1062
1063 static const struct tegra_gpio_soc tegra194_aon_soc = {
1064 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
1065 .ports = tegra194_aon_ports,
1066 .name = "tegra194-gpio-aon",
1067 .instance = 1,
1068 .num_irqs_per_bank = 8,
1069 .has_gte = true,
1070 };
1071
1072 #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1073 [TEGRA234_MAIN_GPIO_PORT_##_name] = { \
1074 .name = #_name, \
1075 .bank = _bank, \
1076 .port = _port, \
1077 .pins = _pins, \
1078 }
1079
1080 static const struct tegra_gpio_port tegra234_main_ports[] = {
1081 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),
1082 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1),
1083 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8),
1084 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4),
1085 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8),
1086 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6),
1087 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8),
1088 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8),
1089 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7),
1090 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6),
1091 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8),
1092 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4),
1093 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8),
1094 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8),
1095 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8),
1096 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8),
1097 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6),
1098 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8),
1099 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8),
1100 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8),
1101 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8),
1102 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4),
1103 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2),
1104 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4),
1105 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8),
1106 };
1107
1108 static const struct tegra_gpio_soc tegra234_main_soc = {
1109 .num_ports = ARRAY_SIZE(tegra234_main_ports),
1110 .ports = tegra234_main_ports,
1111 .name = "tegra234-gpio",
1112 .instance = 0,
1113 .num_irqs_per_bank = 8,
1114 };
1115
1116 #define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1117 [TEGRA234_AON_GPIO_PORT_##_name] = { \
1118 .name = #_name, \
1119 .bank = _bank, \
1120 .port = _port, \
1121 .pins = _pins, \
1122 }
1123
1124 static const struct tegra_gpio_port tegra234_aon_ports[] = {
1125 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),
1126 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),
1127 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),
1128 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3),
1129 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8),
1130 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1),
1131 };
1132
1133 static const struct tegra_gpio_soc tegra234_aon_soc = {
1134 .num_ports = ARRAY_SIZE(tegra234_aon_ports),
1135 .ports = tegra234_aon_ports,
1136 .name = "tegra234-gpio-aon",
1137 .instance = 1,
1138 .num_irqs_per_bank = 8,
1139 };
1140
1141 #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1142 [TEGRA241_MAIN_GPIO_PORT_##_name] = { \
1143 .name = #_name, \
1144 .bank = _bank, \
1145 .port = _port, \
1146 .pins = _pins, \
1147 }
1148
1149 static const struct tegra_gpio_port tegra241_main_ports[] = {
1150 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),
1151 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8),
1152 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2),
1153 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6),
1154 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8),
1155 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8),
1156 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8),
1157 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8),
1158 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8),
1159 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4),
1160 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6),
1161 };
1162
1163 static const struct tegra_gpio_soc tegra241_main_soc = {
1164 .num_ports = ARRAY_SIZE(tegra241_main_ports),
1165 .ports = tegra241_main_ports,
1166 .name = "tegra241-gpio",
1167 .instance = 0,
1168 .num_irqs_per_bank = 8,
1169 };
1170
1171 #define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1172 [TEGRA241_AON_GPIO_PORT_##_name] = { \
1173 .name = #_name, \
1174 .bank = _bank, \
1175 .port = _port, \
1176 .pins = _pins, \
1177 }
1178
1179 static const struct tegra_gpio_port tegra241_aon_ports[] = {
1180 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),
1181 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4),
1182 };
1183
1184 static const struct tegra_gpio_soc tegra241_aon_soc = {
1185 .num_ports = ARRAY_SIZE(tegra241_aon_ports),
1186 .ports = tegra241_aon_ports,
1187 .name = "tegra241-gpio-aon",
1188 .instance = 1,
1189 .num_irqs_per_bank = 8,
1190 };
1191
1192 static const struct of_device_id tegra186_gpio_of_match[] = {
1193 {
1194 .compatible = "nvidia,tegra186-gpio",
1195 .data = &tegra186_main_soc
1196 }, {
1197 .compatible = "nvidia,tegra186-gpio-aon",
1198 .data = &tegra186_aon_soc
1199 }, {
1200 .compatible = "nvidia,tegra194-gpio",
1201 .data = &tegra194_main_soc
1202 }, {
1203 .compatible = "nvidia,tegra194-gpio-aon",
1204 .data = &tegra194_aon_soc
1205 }, {
1206 .compatible = "nvidia,tegra234-gpio",
1207 .data = &tegra234_main_soc
1208 }, {
1209 .compatible = "nvidia,tegra234-gpio-aon",
1210 .data = &tegra234_aon_soc
1211 }, {
1212 /* sentinel */
1213 }
1214 };
1215 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
1216
1217 static const struct acpi_device_id tegra186_gpio_acpi_match[] = {
1218 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc },
1219 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },
1220 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },
1221 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
1222 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },
1223 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },
1224 {}
1225 };
1226 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
1227
1228 static struct platform_driver tegra186_gpio_driver = {
1229 .driver = {
1230 .name = "tegra186-gpio",
1231 .of_match_table = tegra186_gpio_of_match,
1232 .acpi_match_table = tegra186_gpio_acpi_match,
1233 },
1234 .probe = tegra186_gpio_probe,
1235 };
1236 module_platform_driver(tegra186_gpio_driver);
1237
1238 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
1239 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1240 MODULE_LICENSE("GPL v2");
1241
