1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/cpufreq.h>
8 #include <linux/init.h>
9 #include <linux/interconnect.h>
10 #include <linux/interrupt.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of_address.h>
14 #include <linux/of_platform.h>
15 #include <linux/pm_opp.h>
16 #include <linux/pm_qos.h>
17 #include <linux/slab.h>
18 #include <linux/spinlock.h>
19 #include <linux/units.h>
20
21 #define LUT_MAX_ENTRIES 40U
22 #define LUT_SRC GENMASK(31, 30)
23 #define LUT_L_VAL GENMASK(7, 0)
24 #define LUT_CORE_COUNT GENMASK(18, 16)
25 #define LUT_VOLT GENMASK(11, 0)
26 #define CLK_HW_DIV 2
27 #define LUT_TURBO_IND 1
28
29 #define GT_IRQ_STATUS BIT(2)
30
31 struct qcom_cpufreq_soc_data {
32 u32 reg_enable;
33 u32 reg_domain_state;
34 u32 reg_dcvs_ctrl;
35 u32 reg_freq_lut;
36 u32 reg_volt_lut;
37 u32 reg_intr_clr;
38 u32 reg_current_vote;
39 u32 reg_perf_state;
40 u8 lut_row_size;
41 };
42
43 struct qcom_cpufreq_data {
44 void __iomem *base;
45 struct resource *res;
46 const struct qcom_cpufreq_soc_data *soc_data;
47
48 /*
49 * Mutex to synchronize between de-init sequence and re-starting LMh
50 * polling/interrupts
51 */
52 struct mutex throttle_lock;
53 int throttle_irq;
54 char irq_name[15];
55 bool cancel_throttle;
56 struct delayed_work throttle_work;
57 struct cpufreq_policy *policy;
58
59 bool per_core_dcvs;
60
61 struct freq_qos_request throttle_freq_req;
62 };
63
64 static unsigned long cpu_hw_rate, xo_rate;
65 static bool icc_scaling_enabled;
66
qcom_cpufreq_set_bw(struct cpufreq_policy * policy,unsigned long freq_khz)67 static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
68 unsigned long freq_khz)
69 {
70 unsigned long freq_hz = freq_khz * 1000;
71 struct dev_pm_opp *opp;
72 struct device *dev;
73 int ret;
74
75 dev = get_cpu_device(policy->cpu);
76 if (!dev)
77 return -ENODEV;
78
79 opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
80 if (IS_ERR(opp))
81 return PTR_ERR(opp);
82
83 ret = dev_pm_opp_set_opp(dev, opp);
84 dev_pm_opp_put(opp);
85 return ret;
86 }
87
qcom_cpufreq_update_opp(struct device * cpu_dev,unsigned long freq_khz,unsigned long volt)88 static int qcom_cpufreq_update_opp(struct device *cpu_dev,
89 unsigned long freq_khz,
90 unsigned long volt)
91 {
92 unsigned long freq_hz = freq_khz * 1000;
93 int ret;
94
95 /* Skip voltage update if the opp table is not available */
96 if (!icc_scaling_enabled)
97 return dev_pm_opp_add(cpu_dev, freq_hz, volt);
98
99 ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
100 if (ret) {
101 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
102 return ret;
103 }
104
105 return dev_pm_opp_enable(cpu_dev, freq_hz);
106 }
107
qcom_cpufreq_hw_target_index(struct cpufreq_policy * policy,unsigned int index)108 static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
109 unsigned int index)
110 {
111 struct qcom_cpufreq_data *data = policy->driver_data;
112 const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
113 unsigned long freq = policy->freq_table[index].frequency;
114 unsigned int i;
115
116 writel_relaxed(index, data->base + soc_data->reg_perf_state);
117
118 if (data->per_core_dcvs)
119 for (i = 1; i < cpumask_weight(policy->related_cpus); i++)
120 writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4);
121
122 if (icc_scaling_enabled)
123 qcom_cpufreq_set_bw(policy, freq);
124
125 return 0;
126 }
127
qcom_cpufreq_hw_get(unsigned int cpu)128 static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
129 {
130 struct qcom_cpufreq_data *data;
131 const struct qcom_cpufreq_soc_data *soc_data;
132 struct cpufreq_policy *policy;
133 unsigned int index;
134
135 policy = cpufreq_cpu_get_raw(cpu);
136 if (!policy)
137 return 0;
138
139 data = policy->driver_data;
140 soc_data = data->soc_data;
141
142 index = readl_relaxed(data->base + soc_data->reg_perf_state);
143 index = min(index, LUT_MAX_ENTRIES - 1);
144
145 return policy->freq_table[index].frequency;
146 }
147
qcom_cpufreq_hw_fast_switch(struct cpufreq_policy * policy,unsigned int target_freq)148 static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
149 unsigned int target_freq)
150 {
151 struct qcom_cpufreq_data *data = policy->driver_data;
152 const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
153 unsigned int index;
154 unsigned int i;
155
156 index = policy->cached_resolved_idx;
157 writel_relaxed(index, data->base + soc_data->reg_perf_state);
158
159 if (data->per_core_dcvs)
160 for (i = 1; i < cpumask_weight(policy->related_cpus); i++)
161 writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4);
162
163 return policy->freq_table[index].frequency;
164 }
165
qcom_cpufreq_hw_read_lut(struct device * cpu_dev,struct cpufreq_policy * policy)166 static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
167 struct cpufreq_policy *policy)
168 {
169 u32 data, src, lval, i, core_count, prev_freq = 0, freq;
170 u32 volt;
171 struct cpufreq_frequency_table *table;
172 struct dev_pm_opp *opp;
173 unsigned long rate;
174 int ret;
175 struct qcom_cpufreq_data *drv_data = policy->driver_data;
176 const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data;
177
178 table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
179 if (!table)
180 return -ENOMEM;
181
182 ret = dev_pm_opp_of_add_table(cpu_dev);
183 if (!ret) {
184 /* Disable all opps and cross-validate against LUT later */
185 icc_scaling_enabled = true;
186 for (rate = 0; ; rate++) {
187 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
188 if (IS_ERR(opp))
189 break;
190
191 dev_pm_opp_put(opp);
192 dev_pm_opp_disable(cpu_dev, rate);
193 }
194 } else if (ret != -ENODEV) {
195 dev_err(cpu_dev, "Invalid opp table in device tree\n");
196 return ret;
197 } else {
198 policy->fast_switch_possible = true;
199 icc_scaling_enabled = false;
200 }
201
202 for (i = 0; i < LUT_MAX_ENTRIES; i++) {
203 data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut +
204 i * soc_data->lut_row_size);
205 src = FIELD_GET(LUT_SRC, data);
206 lval = FIELD_GET(LUT_L_VAL, data);
207 core_count = FIELD_GET(LUT_CORE_COUNT, data);
208
209 data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut +
210 i * soc_data->lut_row_size);
211 volt = FIELD_GET(LUT_VOLT, data) * 1000;
212
213 if (src)
214 freq = xo_rate * lval / 1000;
215 else
216 freq = cpu_hw_rate / 1000;
217
218 if (freq != prev_freq && core_count != LUT_TURBO_IND) {
219 if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) {
220 table[i].frequency = freq;
221 dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
222 freq, core_count);
223 } else {
224 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq);
225 table[i].frequency = CPUFREQ_ENTRY_INVALID;
226 }
227
228 } else if (core_count == LUT_TURBO_IND) {
229 table[i].frequency = CPUFREQ_ENTRY_INVALID;
230 }
231
232 /*
233 * Two of the same frequencies with the same core counts means
234 * end of table
235 */
236 if (i > 0 && prev_freq == freq) {
237 struct cpufreq_frequency_table *prev = &table[i - 1];
238
239 /*
240 * Only treat the last frequency that might be a boost
241 * as the boost frequency
242 */
243 if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
244 if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) {
245 prev->frequency = prev_freq;
246 prev->flags = CPUFREQ_BOOST_FREQ;
247 } else {
248 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n",
249 freq);
250 }
251 }
252
253 break;
254 }
255
256 prev_freq = freq;
257 }
258
259 table[i].frequency = CPUFREQ_TABLE_END;
260 policy->freq_table = table;
261 dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
262
263 return 0;
264 }
265
qcom_get_related_cpus(int index,struct cpumask * m)266 static void qcom_get_related_cpus(int index, struct cpumask *m)
267 {
268 struct device_node *cpu_np;
269 struct of_phandle_args args;
270 int cpu, ret;
271
272 for_each_possible_cpu(cpu) {
273 cpu_np = of_cpu_device_node_get(cpu);
274 if (!cpu_np)
275 continue;
276
277 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
278 "#freq-domain-cells", 0,
279 &args);
280 of_node_put(cpu_np);
281 if (ret < 0)
282 continue;
283
284 if (index == args.args[0])
285 cpumask_set_cpu(cpu, m);
286 }
287 }
288
qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data * data)289 static unsigned long qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data)
290 {
291 unsigned int lval;
292
293 if (data->soc_data->reg_current_vote)
294 lval = readl_relaxed(data->base + data->soc_data->reg_current_vote) & 0x3ff;
295 else
296 lval = readl_relaxed(data->base + data->soc_data->reg_domain_state) & 0xff;
297
298 return lval * xo_rate;
299 }
300
qcom_lmh_dcvs_notify(struct qcom_cpufreq_data * data)301 static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data)
302 {
303 struct cpufreq_policy *policy = data->policy;
304 int cpu = cpumask_first(policy->related_cpus);
305 struct device *dev = get_cpu_device(cpu);
306 unsigned long freq_hz, throttled_freq;
307 struct dev_pm_opp *opp;
308
309 /*
310 * Get the h/w throttled frequency, normalize it using the
311 * registered opp table and use it to calculate thermal pressure.
312 */
313 freq_hz = qcom_lmh_get_throttle_freq(data);
314
315 opp = dev_pm_opp_find_freq_floor(dev, &freq_hz);
316 if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE)
317 opp = dev_pm_opp_find_freq_ceil(dev, &freq_hz);
318
319 if (IS_ERR(opp)) {
320 dev_warn(dev, "Can't find the OPP for throttling: %pe!\n", opp);
321 } else {
322 dev_pm_opp_put(opp);
323 }
324
325 throttled_freq = freq_hz / HZ_PER_KHZ;
326
327 freq_qos_update_request(&data->throttle_freq_req, throttled_freq);
328
329 /* Update thermal pressure (the boost frequencies are accepted) */
330 arch_update_thermal_pressure(policy->related_cpus, throttled_freq);
331
332 /*
333 * In the unlikely case policy is unregistered do not enable
334 * polling or h/w interrupt
335 */
336 mutex_lock(&data->throttle_lock);
337 if (data->cancel_throttle)
338 goto out;
339
340 /*
341 * If h/w throttled frequency is higher than what cpufreq has requested
342 * for, then stop polling and switch back to interrupt mechanism.
343 */
344 if (throttled_freq >= qcom_cpufreq_hw_get(cpu))
345 enable_irq(data->throttle_irq);
346 else
347 mod_delayed_work(system_highpri_wq, &data->throttle_work,
348 msecs_to_jiffies(10));
349
350 out:
351 mutex_unlock(&data->throttle_lock);
352 }
353
qcom_lmh_dcvs_poll(struct work_struct * work)354 static void qcom_lmh_dcvs_poll(struct work_struct *work)
355 {
356 struct qcom_cpufreq_data *data;
357
358 data = container_of(work, struct qcom_cpufreq_data, throttle_work.work);
359 qcom_lmh_dcvs_notify(data);
360 }
361
qcom_lmh_dcvs_handle_irq(int irq,void * data)362 static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data)
363 {
364 struct qcom_cpufreq_data *c_data = data;
365
366 /* Disable interrupt and enable polling */
367 disable_irq_nosync(c_data->throttle_irq);
368 schedule_delayed_work(&c_data->throttle_work, 0);
369
370 if (c_data->soc_data->reg_intr_clr)
371 writel_relaxed(GT_IRQ_STATUS,
372 c_data->base + c_data->soc_data->reg_intr_clr);
373
374 return IRQ_HANDLED;
375 }
376
377 static const struct qcom_cpufreq_soc_data qcom_soc_data = {
378 .reg_enable = 0x0,
379 .reg_dcvs_ctrl = 0xbc,
380 .reg_freq_lut = 0x110,
381 .reg_volt_lut = 0x114,
382 .reg_current_vote = 0x704,
383 .reg_perf_state = 0x920,
384 .lut_row_size = 32,
385 };
386
387 static const struct qcom_cpufreq_soc_data epss_soc_data = {
388 .reg_enable = 0x0,
389 .reg_domain_state = 0x20,
390 .reg_dcvs_ctrl = 0xb0,
391 .reg_freq_lut = 0x100,
392 .reg_volt_lut = 0x200,
393 .reg_intr_clr = 0x308,
394 .reg_perf_state = 0x320,
395 .lut_row_size = 4,
396 };
397
398 static const struct of_device_id qcom_cpufreq_hw_match[] = {
399 { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
400 { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
401 {}
402 };
403 MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
404
qcom_cpufreq_hw_lmh_init(struct cpufreq_policy * policy,int index)405 static int qcom_cpufreq_hw_lmh_init(struct cpufreq_policy *policy, int index)
406 {
407 struct qcom_cpufreq_data *data = policy->driver_data;
408 struct platform_device *pdev = cpufreq_get_driver_data();
409 int ret;
410
411 /*
412 * Look for LMh interrupt. If no interrupt line is specified /
413 * if there is an error, allow cpufreq to be enabled as usual.
414 */
415 data->throttle_irq = platform_get_irq_optional(pdev, index);
416 if (data->throttle_irq == -ENXIO)
417 return 0;
418 if (data->throttle_irq < 0)
419 return data->throttle_irq;
420
421 ret = freq_qos_add_request(&policy->constraints,
422 &data->throttle_freq_req, FREQ_QOS_MAX,
423 FREQ_QOS_MAX_DEFAULT_VALUE);
424 if (ret < 0) {
425 dev_err(&pdev->dev, "Failed to add freq constraint (%d)\n", ret);
426 return ret;
427 }
428
429 data->cancel_throttle = false;
430 data->policy = policy;
431
432 mutex_init(&data->throttle_lock);
433 INIT_DEFERRABLE_WORK(&data->throttle_work, qcom_lmh_dcvs_poll);
434
435 snprintf(data->irq_name, sizeof(data->irq_name), "dcvsh-irq-%u", policy->cpu);
436 ret = request_threaded_irq(data->throttle_irq, NULL, qcom_lmh_dcvs_handle_irq,
437 IRQF_ONESHOT | IRQF_NO_AUTOEN, data->irq_name, data);
438 if (ret) {
439 dev_err(&pdev->dev, "Error registering %s: %d\n", data->irq_name, ret);
440 return 0;
441 }
442
443 ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus);
444 if (ret)
445 dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
446 data->irq_name, data->throttle_irq);
447
448 return 0;
449 }
450
qcom_cpufreq_hw_cpu_online(struct cpufreq_policy * policy)451 static int qcom_cpufreq_hw_cpu_online(struct cpufreq_policy *policy)
452 {
453 struct qcom_cpufreq_data *data = policy->driver_data;
454 struct platform_device *pdev = cpufreq_get_driver_data();
455 int ret;
456
457 if (data->throttle_irq <= 0)
458 return 0;
459
460 mutex_lock(&data->throttle_lock);
461 data->cancel_throttle = false;
462 mutex_unlock(&data->throttle_lock);
463
464 ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus);
465 if (ret)
466 dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
467 data->irq_name, data->throttle_irq);
468
469 return ret;
470 }
471
qcom_cpufreq_hw_cpu_offline(struct cpufreq_policy * policy)472 static int qcom_cpufreq_hw_cpu_offline(struct cpufreq_policy *policy)
473 {
474 struct qcom_cpufreq_data *data = policy->driver_data;
475
476 if (data->throttle_irq <= 0)
477 return 0;
478
479 mutex_lock(&data->throttle_lock);
480 data->cancel_throttle = true;
481 mutex_unlock(&data->throttle_lock);
482
483 cancel_delayed_work_sync(&data->throttle_work);
484 irq_set_affinity_and_hint(data->throttle_irq, NULL);
485 disable_irq_nosync(data->throttle_irq);
486
487 return 0;
488 }
489
qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data * data)490 static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data)
491 {
492 if (data->throttle_irq <= 0)
493 return;
494
495 freq_qos_remove_request(&data->throttle_freq_req);
496 free_irq(data->throttle_irq, data);
497 }
498
qcom_cpufreq_hw_cpu_init(struct cpufreq_policy * policy)499 static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
500 {
501 struct platform_device *pdev = cpufreq_get_driver_data();
502 struct device *dev = &pdev->dev;
503 struct of_phandle_args args;
504 struct device_node *cpu_np;
505 struct device *cpu_dev;
506 struct resource *res;
507 void __iomem *base;
508 struct qcom_cpufreq_data *data;
509 int ret, index;
510
511 cpu_dev = get_cpu_device(policy->cpu);
512 if (!cpu_dev) {
513 pr_err("%s: failed to get cpu%d device\n", __func__,
514 policy->cpu);
515 return -ENODEV;
516 }
517
518 cpu_np = of_cpu_device_node_get(policy->cpu);
519 if (!cpu_np)
520 return -EINVAL;
521
522 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
523 "#freq-domain-cells", 0, &args);
524 of_node_put(cpu_np);
525 if (ret)
526 return ret;
527
528 index = args.args[0];
529
530 res = platform_get_resource(pdev, IORESOURCE_MEM, index);
531 if (!res) {
532 dev_err(dev, "failed to get mem resource %d\n", index);
533 return -ENODEV;
534 }
535
536 if (!request_mem_region(res->start, resource_size(res), res->name)) {
537 dev_err(dev, "failed to request resource %pR\n", res);
538 return -EBUSY;
539 }
540
541 base = ioremap(res->start, resource_size(res));
542 if (!base) {
543 dev_err(dev, "failed to map resource %pR\n", res);
544 ret = -ENOMEM;
545 goto release_region;
546 }
547
548 data = kzalloc(sizeof(*data), GFP_KERNEL);
549 if (!data) {
550 ret = -ENOMEM;
551 goto unmap_base;
552 }
553
554 data->soc_data = of_device_get_match_data(&pdev->dev);
555 data->base = base;
556 data->res = res;
557
558 /* HW should be in enabled state to proceed */
559 if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
560 dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
561 ret = -ENODEV;
562 goto error;
563 }
564
565 if (readl_relaxed(base + data->soc_data->reg_dcvs_ctrl) & 0x1)
566 data->per_core_dcvs = true;
567
568 qcom_get_related_cpus(index, policy->cpus);
569 if (cpumask_empty(policy->cpus)) {
570 dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
571 ret = -ENOENT;
572 goto error;
573 }
574
575 policy->driver_data = data;
576 policy->dvfs_possible_from_any_cpu = true;
577
578 ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy);
579 if (ret) {
580 dev_err(dev, "Domain-%d failed to read LUT\n", index);
581 goto error;
582 }
583
584 ret = dev_pm_opp_get_opp_count(cpu_dev);
585 if (ret <= 0) {
586 dev_err(cpu_dev, "Failed to add OPPs\n");
587 ret = -ENODEV;
588 goto error;
589 }
590
591 if (policy_has_boost_freq(policy)) {
592 ret = cpufreq_enable_boost_support();
593 if (ret)
594 dev_warn(cpu_dev, "failed to enable boost: %d\n", ret);
595 }
596
597 ret = qcom_cpufreq_hw_lmh_init(policy, index);
598 if (ret)
599 goto error;
600
601 return 0;
602 error:
603 kfree(data);
604 unmap_base:
605 iounmap(base);
606 release_region:
607 release_mem_region(res->start, resource_size(res));
608 return ret;
609 }
610
qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy * policy)611 static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
612 {
613 struct device *cpu_dev = get_cpu_device(policy->cpu);
614 struct qcom_cpufreq_data *data = policy->driver_data;
615 struct resource *res = data->res;
616 void __iomem *base = data->base;
617
618 dev_pm_opp_remove_all_dynamic(cpu_dev);
619 dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
620 qcom_cpufreq_hw_lmh_exit(data);
621 kfree(policy->freq_table);
622 kfree(data);
623 iounmap(base);
624 release_mem_region(res->start, resource_size(res));
625
626 return 0;
627 }
628
qcom_cpufreq_ready(struct cpufreq_policy * policy)629 static void qcom_cpufreq_ready(struct cpufreq_policy *policy)
630 {
631 struct qcom_cpufreq_data *data = policy->driver_data;
632
633 if (data->throttle_irq >= 0)
634 enable_irq(data->throttle_irq);
635 }
636
637 static struct freq_attr *qcom_cpufreq_hw_attr[] = {
638 &cpufreq_freq_attr_scaling_available_freqs,
639 &cpufreq_freq_attr_scaling_boost_freqs,
640 NULL
641 };
642
643 static struct cpufreq_driver cpufreq_qcom_hw_driver = {
644 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
645 CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
646 CPUFREQ_IS_COOLING_DEV,
647 .verify = cpufreq_generic_frequency_table_verify,
648 .target_index = qcom_cpufreq_hw_target_index,
649 .get = qcom_cpufreq_hw_get,
650 .init = qcom_cpufreq_hw_cpu_init,
651 .exit = qcom_cpufreq_hw_cpu_exit,
652 .online = qcom_cpufreq_hw_cpu_online,
653 .offline = qcom_cpufreq_hw_cpu_offline,
654 .register_em = cpufreq_register_em_with_opp,
655 .fast_switch = qcom_cpufreq_hw_fast_switch,
656 .name = "qcom-cpufreq-hw",
657 .attr = qcom_cpufreq_hw_attr,
658 .ready = qcom_cpufreq_ready,
659 };
660
qcom_cpufreq_hw_driver_probe(struct platform_device * pdev)661 static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
662 {
663 struct device *cpu_dev;
664 struct clk *clk;
665 int ret;
666
667 clk = clk_get(&pdev->dev, "xo");
668 if (IS_ERR(clk))
669 return PTR_ERR(clk);
670
671 xo_rate = clk_get_rate(clk);
672 clk_put(clk);
673
674 clk = clk_get(&pdev->dev, "alternate");
675 if (IS_ERR(clk))
676 return PTR_ERR(clk);
677
678 cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
679 clk_put(clk);
680
681 cpufreq_qcom_hw_driver.driver_data = pdev;
682
683 /* Check for optional interconnect paths on CPU0 */
684 cpu_dev = get_cpu_device(0);
685 if (!cpu_dev)
686 return -EPROBE_DEFER;
687
688 ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
689 if (ret)
690 return ret;
691
692 ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
693 if (ret)
694 dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
695 else
696 dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
697
698 return ret;
699 }
700
qcom_cpufreq_hw_driver_remove(struct platform_device * pdev)701 static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
702 {
703 return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
704 }
705
706 static struct platform_driver qcom_cpufreq_hw_driver = {
707 .probe = qcom_cpufreq_hw_driver_probe,
708 .remove = qcom_cpufreq_hw_driver_remove,
709 .driver = {
710 .name = "qcom-cpufreq-hw",
711 .of_match_table = qcom_cpufreq_hw_match,
712 },
713 };
714
qcom_cpufreq_hw_init(void)715 static int __init qcom_cpufreq_hw_init(void)
716 {
717 return platform_driver_register(&qcom_cpufreq_hw_driver);
718 }
719 postcore_initcall(qcom_cpufreq_hw_init);
720
qcom_cpufreq_hw_exit(void)721 static void __exit qcom_cpufreq_hw_exit(void)
722 {
723 platform_driver_unregister(&qcom_cpufreq_hw_driver);
724 }
725 module_exit(qcom_cpufreq_hw_exit);
726
727 MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
728 MODULE_LICENSE("GPL v2");
729
