1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022 Samsung Electronics Co., Ltd.
4 * Author: Chanho Park <chanho61.park@samsung.com>
5 *
6 * Common Clock Framework support for ExynosAuto V9 SoC.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15
16 #include <dt-bindings/clock/samsung,exynosautov9.h>
17
18 #include "clk.h"
19 #include "clk-exynos-arm64.h"
20
21 /* ---- CMU_TOP ------------------------------------------------------------ */
22
23 /* Register Offset definitions for CMU_TOP (0x1b240000) */
24 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
25 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
26 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
27 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
28 #define PLL_LOCKTIME_PLL_SHARED4 0x0010
29 #define PLL_CON0_PLL_SHARED0 0x0100
30 #define PLL_CON3_PLL_SHARED0 0x010c
31 #define PLL_CON0_PLL_SHARED1 0x0140
32 #define PLL_CON3_PLL_SHARED1 0x014c
33 #define PLL_CON0_PLL_SHARED2 0x0180
34 #define PLL_CON3_PLL_SHARED2 0x018c
35 #define PLL_CON0_PLL_SHARED3 0x01c0
36 #define PLL_CON3_PLL_SHARED3 0x01cc
37 #define PLL_CON0_PLL_SHARED4 0x0200
38 #define PLL_CON3_PLL_SHARED4 0x020c
39
40 /* MUX */
41 #define CLK_CON_MUX_MUX_CLKCMU_ACC_BUS 0x1000
42 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
43 #define CLK_CON_MUX_MUX_CLKCMU_AUD_BUS 0x1008
44 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x100c
45 #define CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS 0x1010
46 #define CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS 0x1018
47 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x101c
48 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1020
49 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0x1024
50 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x102c
51 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0x1030
52 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1034
53 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS 0x1040
54 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0x1044
55 #define CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS 0x1048
56 #define CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS 0x104c
57 #define CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS 0x1050
58 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS 0x1054
59 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE 0x1058
60 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS 0x105c
61 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD 0x1060
62 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD 0x1064
63 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS 0x1068
64 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET 0x106c
65 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD 0x1070
66 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1074
67 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1078
68 #define CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH 0x107c
69 #define CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH 0x1080
70 #define CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH 0x1084
71 #define CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS 0x108c
72 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x1090
73 #define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x1094
74 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c
75 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x1098
76 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c
77 #define CLK_CON_MUX_MUX_CLKCMU_NPU_BUS 0x10a0
78 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10a4
79 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10a8
80 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10ac
81 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10b0
82 #define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS 0x10b4
83 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x10c0
84
85 /* DIV */
86 #define CLK_CON_DIV_CLKCMU_ACC_BUS 0x1800
87 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1804
88 #define CLK_CON_DIV_CLKCMU_AUD_BUS 0x1808
89 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x180c
90 #define CLK_CON_DIV_CLKCMU_BUSC_BUS 0x1810
91 #define CLK_CON_DIV_CLKCMU_BUSMC_BUS 0x1818
92 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c
93 #define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0x1820
94 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1828
95 #define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0x182c
96 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1830
97 #define CLK_CON_DIV_CLKCMU_DPTX_BUS 0x183c
98 #define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0x1840
99 #define CLK_CON_DIV_CLKCMU_DPUM_BUS 0x1844
100 #define CLK_CON_DIV_CLKCMU_DPUS0_BUS 0x1848
101 #define CLK_CON_DIV_CLKCMU_DPUS1_BUS 0x184c
102 #define CLK_CON_DIV_CLKCMU_FSYS0_BUS 0x1850
103 #define CLK_CON_DIV_CLKCMU_FSYS0_PCIE 0x1854
104 #define CLK_CON_DIV_CLKCMU_FSYS1_BUS 0x1858
105 #define CLK_CON_DIV_CLKCMU_FSYS1_USBDRD 0x185c
106 #define CLK_CON_DIV_CLKCMU_FSYS2_BUS 0x1860
107 #define CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET 0x1864
108 #define CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD 0x1868
109 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x186c
110 #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x1870
111 #define CLK_CON_DIV_CLKCMU_G3D00_SWITCH 0x1874
112 #define CLK_CON_DIV_CLKCMU_G3D01_SWITCH 0x1878
113 #define CLK_CON_DIV_CLKCMU_G3D1_SWITCH 0x187c
114 #define CLK_CON_DIV_CLKCMU_ISPB_BUS 0x1884
115 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x1888
116 #define CLK_CON_DIV_CLKCMU_MFC_WFD 0x188c
117 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x1890
118 #define CLK_CON_DIV_CLKCMU_NPU_BUS 0x1894
119 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x1898
120 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x189c
121 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18a0
122 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18a4
123 #define CLK_CON_DIV_CLKCMU_PERIS_BUS 0x18a8
124 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18b4
125
126 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18b8
127 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18bc
128 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18c0
129 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18c4
130 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18c8
131 #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x18cc
132 #define CLK_CON_DIV_PLL_SHARED2_DIV3 0x18d0
133 #define CLK_CON_DIV_PLL_SHARED2_DIV4 0x18d4
134 #define CLK_CON_DIV_PLL_SHARED4_DIV2 0x18d4
135 #define CLK_CON_DIV_PLL_SHARED4_DIV4 0x18d8
136
137 /* GATE */
138 #define CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST 0x2000
139 #define CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST 0x2004
140 #define CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST 0x2008
141 #define CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST 0x2010
142 #define CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST 0x2018
143 #define CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST 0x2020
144 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD 0x2024
145 #define CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH 0x2028
146 #define CLK_CON_GAT_GATE_CLKCMU_ACC_BUS 0x202c
147 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2030
148 #define CLK_CON_GAT_GATE_CLKCMU_AUD_BUS 0x2034
149 #define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU 0x2038
150 #define CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS 0x203c
151 #define CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS 0x2044
152 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2048
153 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x204c
154 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER 0x2050
155 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2058
156 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER 0x205c
157 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2060
158 #define CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS 0x206c
159 #define CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC 0x2070
160 #define CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS 0x2060
161 #define CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS 0x2064
162 #define CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS 0x207c
163 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS 0x2080
164 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE 0x2084
165 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS 0x2088
166 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD 0x208c
167 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS 0x2090
168 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET 0x2094
169 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD 0x2098
170 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x209c
171 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x20a0
172 #define CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH 0x20a4
173 #define CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH 0x20a8
174 #define CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH 0x20ac
175 #define CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS 0x20b4
176 #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20b8
177 #define CLK_CON_GAT_GATE_CLKCMU_MFC_WFD 0x20bc
178 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20c0
179 #define CLK_CON_GAT_GATE_CLKCMU_NPU_BUS 0x20c4
180 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20c8
181 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20cc
182 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x20d0
183 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x20d4
184 #define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS 0x20d8
185
186 static const unsigned long top_clk_regs[] __initconst = {
187 PLL_LOCKTIME_PLL_SHARED0,
188 PLL_LOCKTIME_PLL_SHARED1,
189 PLL_LOCKTIME_PLL_SHARED2,
190 PLL_LOCKTIME_PLL_SHARED3,
191 PLL_LOCKTIME_PLL_SHARED4,
192 PLL_CON0_PLL_SHARED0,
193 PLL_CON3_PLL_SHARED0,
194 PLL_CON0_PLL_SHARED1,
195 PLL_CON3_PLL_SHARED1,
196 PLL_CON0_PLL_SHARED2,
197 PLL_CON3_PLL_SHARED2,
198 PLL_CON0_PLL_SHARED3,
199 PLL_CON3_PLL_SHARED3,
200 PLL_CON0_PLL_SHARED4,
201 PLL_CON3_PLL_SHARED4,
202 CLK_CON_MUX_MUX_CLKCMU_ACC_BUS,
203 CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
204 CLK_CON_MUX_MUX_CLKCMU_AUD_BUS,
205 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
206 CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS,
207 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
208 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
209 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER,
210 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
211 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER,
212 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
213 CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS,
214 CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC,
215 CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS,
216 CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS,
217 CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS,
218 CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS,
219 CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE,
220 CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS,
221 CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD,
222 CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD,
223 CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS,
224 CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET,
225 CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD,
226 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
227 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
228 CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH,
229 CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH,
230 CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH,
231 CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS,
232 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
233 CLK_CON_MUX_MUX_CLKCMU_MFC_WFD,
234 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
235 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
236 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
237 CLK_CON_MUX_MUX_CLKCMU_NPU_BUS,
238 CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
239 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
240 CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
241 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
242 CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS,
243 CLK_CON_MUX_MUX_CMU_CMUREF,
244 CLK_CON_DIV_CLKCMU_ACC_BUS,
245 CLK_CON_DIV_CLKCMU_APM_BUS,
246 CLK_CON_DIV_CLKCMU_AUD_BUS,
247 CLK_CON_DIV_CLKCMU_AUD_CPU,
248 CLK_CON_DIV_CLKCMU_BUSC_BUS,
249 CLK_CON_DIV_CLKCMU_BUSMC_BUS,
250 CLK_CON_DIV_CLKCMU_CORE_BUS,
251 CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
252 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
253 CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
254 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
255 CLK_CON_DIV_CLKCMU_DPTX_BUS,
256 CLK_CON_DIV_CLKCMU_DPTX_DPGTC,
257 CLK_CON_DIV_CLKCMU_DPUM_BUS,
258 CLK_CON_DIV_CLKCMU_DPUS0_BUS,
259 CLK_CON_DIV_CLKCMU_DPUS1_BUS,
260 CLK_CON_DIV_CLKCMU_FSYS0_BUS,
261 CLK_CON_DIV_CLKCMU_FSYS0_PCIE,
262 CLK_CON_DIV_CLKCMU_FSYS1_BUS,
263 CLK_CON_DIV_CLKCMU_FSYS1_USBDRD,
264 CLK_CON_DIV_CLKCMU_FSYS2_BUS,
265 CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET,
266 CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD,
267 CLK_CON_DIV_CLKCMU_G2D_G2D,
268 CLK_CON_DIV_CLKCMU_G2D_MSCL,
269 CLK_CON_DIV_CLKCMU_G3D00_SWITCH,
270 CLK_CON_DIV_CLKCMU_G3D01_SWITCH,
271 CLK_CON_DIV_CLKCMU_G3D1_SWITCH,
272 CLK_CON_DIV_CLKCMU_ISPB_BUS,
273 CLK_CON_DIV_CLKCMU_MFC_MFC,
274 CLK_CON_DIV_CLKCMU_MFC_WFD,
275 CLK_CON_DIV_CLKCMU_MIF_BUSP,
276 CLK_CON_DIV_CLKCMU_NPU_BUS,
277 CLK_CON_DIV_CLKCMU_PERIC0_BUS,
278 CLK_CON_DIV_CLKCMU_PERIC0_IP,
279 CLK_CON_DIV_CLKCMU_PERIC1_BUS,
280 CLK_CON_DIV_CLKCMU_PERIC1_IP,
281 CLK_CON_DIV_CLKCMU_PERIS_BUS,
282 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
283 CLK_CON_DIV_PLL_SHARED0_DIV2,
284 CLK_CON_DIV_PLL_SHARED0_DIV3,
285 CLK_CON_DIV_PLL_SHARED1_DIV2,
286 CLK_CON_DIV_PLL_SHARED1_DIV3,
287 CLK_CON_DIV_PLL_SHARED1_DIV4,
288 CLK_CON_DIV_PLL_SHARED2_DIV2,
289 CLK_CON_DIV_PLL_SHARED2_DIV3,
290 CLK_CON_DIV_PLL_SHARED2_DIV4,
291 CLK_CON_DIV_PLL_SHARED4_DIV2,
292 CLK_CON_DIV_PLL_SHARED4_DIV4,
293 CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST,
294 CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST,
295 CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST,
296 CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST,
297 CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST,
298 CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST,
299 CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD,
300 CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH,
301 CLK_CON_GAT_GATE_CLKCMU_ACC_BUS,
302 CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
303 CLK_CON_GAT_GATE_CLKCMU_AUD_BUS,
304 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU,
305 CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS,
306 CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS,
307 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
308 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
309 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER,
310 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
311 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER,
312 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
313 CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS,
314 CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC,
315 CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS,
316 CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS,
317 CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS,
318 CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS,
319 CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE,
320 CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,
321 CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD,
322 CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS,
323 CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET,
324 CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD,
325 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
326 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
327 CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH,
328 CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH,
329 CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH,
330 CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS,
331 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
332 CLK_CON_GAT_GATE_CLKCMU_MFC_WFD,
333 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
334 CLK_CON_GAT_GATE_CLKCMU_NPU_BUS,
335 CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
336 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
337 CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
338 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
339 CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
340 };
341
342 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
343 /* CMU_TOP_PURECLKCOMP */
344 PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
345 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
346 PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared1_pll", "oscclk",
347 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
348 PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared2_pll", "oscclk",
349 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
350 PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared3_pll", "oscclk",
351 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
352 PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared4_pll", "oscclk",
353 PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
354 };
355
356 /* List of parent clocks for Muxes in CMU_TOP */
357 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
358 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
359 PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
360 PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
361 PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
362
363 PNAME(mout_clkcmu_cmu_boost_p) = { "dout_shared2_div3", "dout_shared1_div4",
364 "dout_shared2_div4", "dout_shared4_div4" };
365 PNAME(mout_clkcmu_cmu_cmuref_p) = { "oscclk", "dout_cmu_boost" };
366 PNAME(mout_clkcmu_acc_bus_p) = { "dout_shared1_div3", "dout_shared2_div3",
367 "dout_shared1_div4", "dout_shared2_div4" };
368 PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
369 "dout_shared2_div4", "dout_shared4_div4" };
370 PNAME(mout_clkcmu_aud_cpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
371 "dout_shared2_div2", "dout_shared0_div3",
372 "dout_shared4_div2", "dout_shared1_div3",
373 "fout_shared3_pll" };
374 PNAME(mout_clkcmu_aud_bus_p) = { "dout_shared4_div2", "dout_shared1_div3",
375 "dout_shared2_div3", "dout_shared1_div4" };
376 PNAME(mout_clkcmu_busc_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
377 "dout_shared2_div4", "dout_shared4_div4" };
378 PNAME(mout_clkcmu_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
379 "dout_shared2_div2", "dout_shared0_div3",
380 "dout_shared4_div2", "dout_shared1_div3",
381 "dout_shared2_div3", "fout_shared3_pll" };
382 PNAME(mout_clkcmu_cpucl0_switch_p) = {
383 "dout_shared0_div2", "dout_shared1_div2",
384 "dout_shared2_div2", "dout_shared4_div2" };
385 PNAME(mout_clkcmu_cpucl0_cluster_p) = {
386 "fout_shared2_pll", "fout_shared4_pll",
387 "dout_shared0_div2", "dout_shared1_div2",
388 "dout_shared2_div2", "dout_shared4_div2",
389 "dout_shared2_div3", "fout_shared3_pll" };
390 PNAME(mout_clkcmu_dptx_bus_p) = { "dout_shared4_div2", "dout_shared2_div3",
391 "dout_shared1_div4", "dout_shared2_div4" };
392 PNAME(mout_clkcmu_dptx_dpgtc_p) = { "oscclk", "dout_shared2_div3",
393 "dout_shared2_div4", "dout_shared4_div4" };
394 PNAME(mout_clkcmu_dpum_bus_p) = { "dout_shared1_div3", "dout_shared2_div3",
395 "dout_shared1_div4", "dout_shared2_div4",
396 "dout_shared4_div4", "fout_shared3_pll" };
397 PNAME(mout_clkcmu_fsys0_bus_p) = {
398 "dout_shared4_div2", "dout_shared2_div3",
399 "dout_shared1_div4", "dout_shared2_div4" };
400 PNAME(mout_clkcmu_fsys0_pcie_p) = { "oscclk", "dout_shared2_div4" };
401 PNAME(mout_clkcmu_fsys1_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
402 "dout_shared2_div4", "dout_shared4_div4" };
403 PNAME(mout_clkcmu_fsys1_usbdrd_p) = {
404 "oscclk", "dout_shared2_div3",
405 "dout_shared2_div4", "dout_shared4_div4" };
406 PNAME(mout_clkcmu_fsys1_mmc_card_p) = {
407 "oscclk", "dout_shared2_div2",
408 "dout_shared4_div2", "dout_shared2_div3" };
409 PNAME(mout_clkcmu_fsys2_ethernet_p) = {
410 "oscclk", "dout_shared2_div2",
411 "dout_shared0_div3", "dout_shared2_div3",
412 "dout_shared1_div4", "fout_shared3_pll" };
413 PNAME(mout_clkcmu_g2d_g2d_p) = { "dout_shared2_div2", "dout_shared0_div3",
414 "dout_shared4_div2", "dout_shared1_div3",
415 "dout_shared2_div3", "dout_shared1_div4",
416 "dout_shared2_div4", "dout_shared4_div4" };
417 PNAME(mout_clkcmu_g3d0_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
418 "dout_shared2_div2", "dout_shared4_div2" };
419 PNAME(mout_clkcmu_g3d1_switch_p) = { "dout_shared2_div2", "dout_shared4_div2",
420 "dout_shared2_div3", "dout_shared1_div4" };
421 PNAME(mout_clkcmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
422 "fout_shared2_pll", "fout_shared4_pll",
423 "dout_shared0_div2", "dout_shared1_div2",
424 "dout_shared2_div2", "fout_shared3_pll" };
425 PNAME(mout_clkcmu_npu_bus_p) = { "dout_shared1_div2", "dout_shared2_div2",
426 "dout_shared0_div3", "dout_shared4_div2",
427 "dout_shared1_div3", "dout_shared2_div3",
428 "dout_shared1_div4", "fout_shared3_pll" };
429 PNAME(mout_clkcmu_peric0_bus_p) = { "dout_shared2_div3", "dout_shared2_div4" };
430
431 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
432 /* CMU_TOP_PURECLKCOMP */
433 MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
434 PLL_CON0_PLL_SHARED0, 4, 1),
435 MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
436 PLL_CON0_PLL_SHARED1, 4, 1),
437 MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
438 PLL_CON0_PLL_SHARED2, 4, 1),
439 MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
440 PLL_CON0_PLL_SHARED3, 4, 1),
441 MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p,
442 PLL_CON0_PLL_SHARED4, 4, 1),
443
444 /* BOOST */
445 MUX(MOUT_CLKCMU_CMU_BOOST, "mout_clkcmu_cmu_boost",
446 mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
447 MUX(MOUT_CLKCMU_CMU_CMUREF, "mout_clkcmu_cmu_cmuref",
448 mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
449
450 /* ACC */
451 MUX(MOUT_CLKCMU_ACC_BUS, "mout_clkcmu_acc_bus", mout_clkcmu_acc_bus_p,
452 CLK_CON_MUX_MUX_CLKCMU_ACC_BUS, 0, 2),
453
454 /* APM */
455 MUX(MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", mout_clkcmu_apm_bus_p,
456 CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 2),
457
458 /* AUD */
459 MUX(MOUT_CLKCMU_AUD_CPU, "mout_clkcmu_aud_cpu", mout_clkcmu_aud_cpu_p,
460 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
461 MUX(MOUT_CLKCMU_AUD_BUS, "mout_clkcmu_aud_bus", mout_clkcmu_aud_bus_p,
462 CLK_CON_MUX_MUX_CLKCMU_AUD_BUS, 0, 2),
463
464 /* BUSC */
465 MUX(MOUT_CLKCMU_BUSC_BUS, "mout_clkcmu_busc_bus",
466 mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, 0, 2),
467
468 /* BUSMC */
469 MUX(MOUT_CLKCMU_BUSMC_BUS, "mout_clkcmu_busmc_bus",
470 mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS, 0, 2),
471
472 /* CORE */
473 MUX(MOUT_CLKCMU_CORE_BUS, "mout_clkcmu_core_bus",
474 mout_clkcmu_core_bus_p, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
475
476 /* CPUCL0 */
477 MUX(MOUT_CLKCMU_CPUCL0_SWITCH, "mout_clkcmu_cpucl0_switch",
478 mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
479 0, 2),
480 MUX(MOUT_CLKCMU_CPUCL0_CLUSTER, "mout_clkcmu_cpucl0_cluster",
481 mout_clkcmu_cpucl0_cluster_p,
482 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER, 0, 3),
483
484 /* CPUCL1 */
485 MUX(MOUT_CLKCMU_CPUCL1_SWITCH, "mout_clkcmu_cpucl1_switch",
486 mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
487 0, 2),
488 MUX(MOUT_CLKCMU_CPUCL1_CLUSTER, "mout_clkcmu_cpucl1_cluster",
489 mout_clkcmu_cpucl0_cluster_p,
490 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER, 0, 3),
491
492 /* DPTX */
493 MUX(MOUT_CLKCMU_DPTX_BUS, "mout_clkcmu_dptx_bus",
494 mout_clkcmu_dptx_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS, 0, 2),
495 MUX(MOUT_CLKCMU_DPTX_DPGTC, "mout_clkcmu_dptx_dpgtc",
496 mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2),
497
498 /* DPUM */
499 MUX(MOUT_CLKCMU_DPUM_BUS, "mout_clkcmu_dpum_bus",
500 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS, 0, 3),
501
502 /* DPUS */
503 MUX(MOUT_CLKCMU_DPUS0_BUS, "mout_clkcmu_dpus0_bus",
504 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS, 0, 3),
505 MUX(MOUT_CLKCMU_DPUS1_BUS, "mout_clkcmu_dpus1_bus",
506 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS, 0, 3),
507
508 /* FSYS0 */
509 MUX(MOUT_CLKCMU_FSYS0_BUS, "mout_clkcmu_fsys0_bus",
510 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS, 0, 2),
511 MUX(MOUT_CLKCMU_FSYS0_PCIE, "mout_clkcmu_fsys0_pcie",
512 mout_clkcmu_fsys0_pcie_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE, 0, 1),
513
514 /* FSYS1 */
515 MUX(MOUT_CLKCMU_FSYS1_BUS, "mout_clkcmu_fsys1_bus",
516 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS, 0, 2),
517 MUX(MOUT_CLKCMU_FSYS1_USBDRD, "mout_clkcmu_fsys1_usbdrd",
518 mout_clkcmu_fsys1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD,
519 0, 2),
520 MUX(MOUT_CLKCMU_FSYS1_MMC_CARD, "mout_clkcmu_fsys1_mmc_card",
521 mout_clkcmu_fsys1_mmc_card_p,
522 CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD, 0, 2),
523
524 /* FSYS2 */
525 MUX(MOUT_CLKCMU_FSYS2_BUS, "mout_clkcmu_fsys2_bus",
526 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS, 0, 2),
527 MUX(MOUT_CLKCMU_FSYS2_UFS_EMBD, "mout_clkcmu_fsys2_ufs_embd",
528 mout_clkcmu_fsys1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD,
529 0, 2),
530 MUX(MOUT_CLKCMU_FSYS2_ETHERNET, "mout_clkcmu_fsys2_ethernet",
531 mout_clkcmu_fsys2_ethernet_p,
532 CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET, 0, 3),
533
534 /* G2D */
535 MUX(MOUT_CLKCMU_G2D_G2D, "mout_clkcmu_g2d_g2d", mout_clkcmu_g2d_g2d_p,
536 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3),
537 MUX(MOUT_CLKCMU_G2D_MSCL, "mout_clkcmu_g2d_mscl",
538 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
539
540 /* G3D0 */
541 MUX(MOUT_CLKCMU_G3D00_SWITCH, "mout_clkcmu_g3d00_switch",
542 mout_clkcmu_g3d0_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH,
543 0, 2),
544 MUX(MOUT_CLKCMU_G3D01_SWITCH, "mout_clkcmu_g3d01_switch",
545 mout_clkcmu_g3d0_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH,
546 0, 2),
547
548 /* G3D1 */
549 MUX(MOUT_CLKCMU_G3D1_SWITCH, "mout_clkcmu_g3d1_switch",
550 mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH,
551 0, 2),
552
553 /* ISPB */
554 MUX(MOUT_CLKCMU_ISPB_BUS, "mout_clkcmu_ispb_bus",
555 mout_clkcmu_acc_bus_p, CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS, 0, 2),
556
557 /* MFC */
558 MUX(MOUT_CLKCMU_MFC_MFC, "mout_clkcmu_mfc_mfc",
559 mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
560 MUX(MOUT_CLKCMU_MFC_WFD, "mout_clkcmu_mfc_wfd",
561 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2),
562
563 /* MIF */
564 MUX(MOUT_CLKCMU_MIF_SWITCH, "mout_clkcmu_mif_switch",
565 mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
566 MUX(MOUT_CLKCMU_MIF_BUSP, "mout_clkcmu_mif_busp",
567 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
568
569 /* NPU */
570 MUX(MOUT_CLKCMU_NPU_BUS, "mout_clkcmu_npu_bus", mout_clkcmu_npu_bus_p,
571 CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 0, 3),
572
573 /* PERIC0 */
574 MUX(MOUT_CLKCMU_PERIC0_BUS, "mout_clkcmu_peric0_bus",
575 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1),
576 MUX(MOUT_CLKCMU_PERIC0_IP, "mout_clkcmu_peric0_ip",
577 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
578
579 /* PERIC1 */
580 MUX(MOUT_CLKCMU_PERIC1_BUS, "mout_clkcmu_peric1_bus",
581 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1),
582 MUX(MOUT_CLKCMU_PERIC1_IP, "mout_clkcmu_peric1_ip",
583 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
584
585 /* PERIS */
586 MUX(MOUT_CLKCMU_PERIS_BUS, "mout_clkcmu_peris_bus",
587 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1),
588 };
589
590 static const struct samsung_div_clock top_div_clks[] __initconst = {
591 /* CMU_TOP_PURECLKCOMP */
592 DIV(DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
593 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
594 DIV(DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
595 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
596
597 DIV(DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
598 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
599 DIV(DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
600 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
601 DIV(DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
602 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
603
604 DIV(DOUT_SHARED2_DIV3, "dout_shared2_div3", "mout_shared2_pll",
605 CLK_CON_DIV_PLL_SHARED2_DIV3, 0, 2),
606 DIV(DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll",
607 CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
608 DIV(DOUT_SHARED2_DIV4, "dout_shared2_div4", "dout_shared2_div2",
609 CLK_CON_DIV_PLL_SHARED2_DIV4, 0, 1),
610
611 DIV(DOUT_SHARED4_DIV2, "dout_shared4_div2", "mout_shared4_pll",
612 CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
613 DIV(DOUT_SHARED4_DIV4, "dout_shared4_div4", "dout_shared4_div2",
614 CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
615
616 /* BOOST */
617 DIV(DOUT_CLKCMU_CMU_BOOST, "dout_clkcmu_cmu_boost",
618 "gout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
619
620 /* ACC */
621 DIV(DOUT_CLKCMU_ACC_BUS, "dout_clkcmu_acc_bus", "gout_clkcmu_acc_bus",
622 CLK_CON_DIV_CLKCMU_ACC_BUS, 0, 4),
623
624 /* APM */
625 DIV(DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", "gout_clkcmu_apm_bus",
626 CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
627
628 /* AUD */
629 DIV(DOUT_CLKCMU_AUD_CPU, "dout_clkcmu_aud_cpu", "gout_clkcmu_aud_cpu",
630 CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
631 DIV(DOUT_CLKCMU_AUD_BUS, "dout_clkcmu_aud_bus", "gout_clkcmu_aud_bus",
632 CLK_CON_DIV_CLKCMU_AUD_BUS, 0, 4),
633
634 /* BUSC */
635 DIV(DOUT_CLKCMU_BUSC_BUS, "dout_clkcmu_busc_bus",
636 "gout_clkcmu_busc_bus", CLK_CON_DIV_CLKCMU_BUSC_BUS, 0, 4),
637
638 /* BUSMC */
639 DIV(DOUT_CLKCMU_BUSMC_BUS, "dout_clkcmu_busmc_bus",
640 "gout_clkcmu_busmc_bus", CLK_CON_DIV_CLKCMU_BUSMC_BUS, 0, 4),
641
642 /* CORE */
643 DIV(DOUT_CLKCMU_CORE_BUS, "dout_clkcmu_core_bus",
644 "gout_clkcmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
645
646 /* CPUCL0 */
647 DIV(DOUT_CLKCMU_CPUCL0_SWITCH, "dout_clkcmu_cpucl0_switch",
648 "gout_clkcmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
649 0, 3),
650 DIV(DOUT_CLKCMU_CPUCL0_CLUSTER, "dout_clkcmu_cpucl0_cluster",
651 "gout_clkcmu_cpucl0_cluster", CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
652 0, 3),
653
654 /* CPUCL1 */
655 DIV(DOUT_CLKCMU_CPUCL1_SWITCH, "dout_clkcmu_cpucl1_switch",
656 "gout_clkcmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
657 0, 3),
658 DIV(DOUT_CLKCMU_CPUCL1_CLUSTER, "dout_clkcmu_cpucl1_cluster",
659 "gout_clkcmu_cpucl1_cluster", CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
660 0, 3),
661
662 /* DPTX */
663 DIV(DOUT_CLKCMU_DPTX_BUS, "dout_clkcmu_dptx_bus",
664 "gout_clkcmu_dptx_bus", CLK_CON_DIV_CLKCMU_DPTX_BUS, 0, 4),
665 DIV(DOUT_CLKCMU_DPTX_DPGTC, "dout_clkcmu_dptx_dpgtc",
666 "gout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3),
667
668 /* DPUM */
669 DIV(DOUT_CLKCMU_DPUM_BUS, "dout_clkcmu_dpum_bus",
670 "gout_clkcmu_dpum_bus", CLK_CON_DIV_CLKCMU_DPUM_BUS, 0, 4),
671
672 /* DPUS */
673 DIV(DOUT_CLKCMU_DPUS0_BUS, "dout_clkcmu_dpus0_bus",
674 "gout_clkcmu_dpus0_bus", CLK_CON_DIV_CLKCMU_DPUS0_BUS, 0, 4),
675 DIV(DOUT_CLKCMU_DPUS1_BUS, "dout_clkcmu_dpus1_bus",
676 "gout_clkcmu_dpus1_bus", CLK_CON_DIV_CLKCMU_DPUS1_BUS, 0, 4),
677
678 /* FSYS0 */
679 DIV(DOUT_CLKCMU_FSYS0_BUS, "dout_clkcmu_fsys0_bus",
680 "gout_clkcmu_fsys0_bus", CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0, 4),
681
682 /* FSYS1 */
683 DIV(DOUT_CLKCMU_FSYS1_BUS, "dout_clkcmu_fsys1_bus",
684 "gout_clkcmu_fsys1_bus", CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0, 4),
685 DIV(DOUT_CLKCMU_FSYS1_USBDRD, "dout_clkcmu_fsys1_usbdrd",
686 "gout_clkcmu_fsys1_usbdrd", CLK_CON_DIV_CLKCMU_FSYS1_USBDRD, 0, 4),
687
688 /* FSYS2 */
689 DIV(DOUT_CLKCMU_FSYS2_BUS, "dout_clkcmu_fsys2_bus",
690 "gout_clkcmu_fsys2_bus", CLK_CON_DIV_CLKCMU_FSYS2_BUS, 0, 4),
691 DIV(DOUT_CLKCMU_FSYS2_UFS_EMBD, "dout_clkcmu_fsys2_ufs_embd",
692 "gout_clkcmu_fsys2_ufs_embd", CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD,
693 0, 3),
694 DIV(DOUT_CLKCMU_FSYS2_ETHERNET, "dout_clkcmu_fsys2_ethernet",
695 "gout_clkcmu_fsys2_ethernet", CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET,
696 0, 3),
697
698 /* G2D */
699 DIV(DOUT_CLKCMU_G2D_G2D, "dout_clkcmu_g2d_g2d", "gout_clkcmu_g2d_g2d",
700 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
701 DIV(DOUT_CLKCMU_G2D_MSCL, "dout_clkcmu_g2d_mscl",
702 "gout_clkcmu_g2d_mscl", CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
703
704 /* G3D0 */
705 DIV(DOUT_CLKCMU_G3D00_SWITCH, "dout_clkcmu_g3d00_switch",
706 "gout_clkcmu_g3d00_switch", CLK_CON_DIV_CLKCMU_G3D00_SWITCH, 0, 3),
707 DIV(DOUT_CLKCMU_G3D01_SWITCH, "dout_clkcmu_g3d01_switch",
708 "gout_clkcmu_g3d01_switch", CLK_CON_DIV_CLKCMU_G3D01_SWITCH, 0, 3),
709
710 /* G3D1 */
711 DIV(DOUT_CLKCMU_G3D1_SWITCH, "dout_clkcmu_g3d1_switch",
712 "gout_clkcmu_g3d1_switch", CLK_CON_DIV_CLKCMU_G3D1_SWITCH, 0, 3),
713
714 /* ISPB */
715 DIV(DOUT_CLKCMU_ISPB_BUS, "dout_clkcmu_ispb_bus",
716 "gout_clkcmu_ispb_bus", CLK_CON_DIV_CLKCMU_ISPB_BUS, 0, 4),
717
718 /* MFC */
719 DIV(DOUT_CLKCMU_MFC_MFC, "dout_clkcmu_mfc_mfc", "gout_clkcmu_mfc_mfc",
720 CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
721 DIV(DOUT_CLKCMU_MFC_WFD, "dout_clkcmu_mfc_wfd", "gout_clkcmu_mfc_wfd",
722 CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
723
724 /* MIF */
725 DIV(DOUT_CLKCMU_MIF_BUSP, "dout_clkcmu_mif_busp",
726 "gout_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
727
728 /* NPU */
729 DIV(DOUT_CLKCMU_NPU_BUS, "dout_clkcmu_npu_bus", "gout_clkcmu_npu_bus",
730 CLK_CON_DIV_CLKCMU_NPU_BUS, 0, 4),
731
732 /* PERIC0 */
733 DIV(DOUT_CLKCMU_PERIC0_BUS, "dout_clkcmu_peric0_bus",
734 "gout_clkcmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
735 DIV(DOUT_CLKCMU_PERIC0_IP, "dout_clkcmu_peric0_ip",
736 "gout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
737
738 /* PERIC1 */
739 DIV(DOUT_CLKCMU_PERIC1_BUS, "dout_clkcmu_peric1_bus",
740 "gout_clkcmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
741 DIV(DOUT_CLKCMU_PERIC1_IP, "dout_clkcmu_peric1_ip",
742 "gout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
743
744 /* PERIS */
745 DIV(DOUT_CLKCMU_PERIS_BUS, "dout_clkcmu_peris_bus",
746 "gout_clkcmu_peris_bus", CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4),
747 };
748
749 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
750 FFACTOR(DOUT_CLKCMU_FSYS0_PCIE, "dout_clkcmu_fsys0_pcie",
751 "gout_clkcmu_fsys0_pcie", 1, 4, 0),
752 };
753
754 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
755 /* BOOST */
756 GATE(GOUT_CLKCMU_CMU_BOOST, "gout_clkcmu_cmu_boost",
757 "mout_clkcmu_cmu_boost", CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
758 21, 0, 0),
759
760 GATE(GOUT_CLKCMU_CPUCL0_BOOST, "gout_clkcmu_cpucl0_boost",
761 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST, 21, 0, 0),
762 GATE(GOUT_CLKCMU_CPUCL1_BOOST, "gout_clkcmu_cpucl1_boost",
763 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST, 21, 0, 0),
764 GATE(GOUT_CLKCMU_CORE_BOOST, "gout_clkcmu_core_boost",
765 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST, 21, 0, 0),
766 GATE(GOUT_CLKCMU_BUSC_BOOST, "gout_clkcmu_busc_boost",
767 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST, 21, 0, 0),
768
769 GATE(GOUT_CLKCMU_BUSMC_BOOST, "gout_clkcmu_busmc_boost",
770 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST, 21, 0, 0),
771 GATE(GOUT_CLKCMU_MIF_BOOST, "gout_clkcmu_mif_boost", "dout_cmu_boost",
772 CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST, 21, 0, 0),
773
774 /* ACC */
775 GATE(GOUT_CLKCMU_ACC_BUS, "gout_clkcmu_acc_bus", "mout_clkcmu_acc_bus",
776 CLK_CON_GAT_GATE_CLKCMU_ACC_BUS, 21, 0, 0),
777
778 /* APM */
779 GATE(GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", "mout_clkcmu_apm_bus",
780 CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0),
781
782 /* AUD */
783 GATE(GOUT_CLKCMU_AUD_CPU, "gout_clkcmu_aud_cpu", "mout_clkcmu_aud_cpu",
784 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 21, 0, 0),
785 GATE(GOUT_CLKCMU_AUD_BUS, "gout_clkcmu_aud_bus", "mout_clkcmu_aud_bus",
786 CLK_CON_GAT_GATE_CLKCMU_AUD_BUS, 21, 0, 0),
787
788 /* BUSC */
789 GATE(GOUT_CLKCMU_BUSC_BUS, "gout_clkcmu_busc_bus",
790 "mout_clkcmu_busc_bus", CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, 21,
791 CLK_IS_CRITICAL, 0),
792
793 /* BUSMC */
794 GATE(GOUT_CLKCMU_BUSMC_BUS, "gout_clkcmu_busmc_bus",
795 "mout_clkcmu_busmc_bus", CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS, 21,
796 CLK_IS_CRITICAL, 0),
797
798 /* CORE */
799 GATE(GOUT_CLKCMU_CORE_BUS, "gout_clkcmu_core_bus",
800 "mout_clkcmu_core_bus", CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
801 21, 0, 0),
802
803 /* CPUCL0 */
804 GATE(GOUT_CLKCMU_CPUCL0_SWITCH, "gout_clkcmu_cpucl0_switch",
805 "mout_clkcmu_cpucl0_switch",
806 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
807 GATE(GOUT_CLKCMU_CPUCL0_CLUSTER, "gout_clkcmu_cpucl0_cluster",
808 "mout_clkcmu_cpucl0_cluster",
809 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
810
811 /* CPUCL1 */
812 GATE(GOUT_CLKCMU_CPUCL1_SWITCH, "gout_clkcmu_cpucl1_switch",
813 "mout_clkcmu_cpucl1_switch",
814 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
815 GATE(GOUT_CLKCMU_CPUCL1_CLUSTER, "gout_clkcmu_cpucl1_cluster",
816 "mout_clkcmu_cpucl1_cluster",
817 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
818
819 /* DPTX */
820 GATE(GOUT_CLKCMU_DPTX_BUS, "gout_clkcmu_dptx_bus",
821 "mout_clkcmu_dptx_bus", CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS,
822 21, 0, 0),
823 GATE(GOUT_CLKCMU_DPTX_DPGTC, "gout_clkcmu_dptx_dpgtc",
824 "mout_clkcmu_dptx_dpgtc", CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC,
825 21, 0, 0),
826
827 /* DPUM */
828 GATE(GOUT_CLKCMU_DPUM_BUS, "gout_clkcmu_dpum_bus",
829 "mout_clkcmu_dpum_bus", CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS,
830 21, 0, 0),
831
832 /* DPUS */
833 GATE(GOUT_CLKCMU_DPUS0_BUS, "gout_clkcmu_dpus0_bus",
834 "mout_clkcmu_dpus0_bus", CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS,
835 21, 0, 0),
836 GATE(GOUT_CLKCMU_DPUS1_BUS, "gout_clkcmu_dpus1_bus",
837 "mout_clkcmu_dpus1_bus", CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS,
838 21, 0, 0),
839
840 /* FSYS0 */
841 GATE(GOUT_CLKCMU_FSYS0_BUS, "gout_clkcmu_fsys0_bus",
842 "mout_clkcmu_fsys0_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS,
843 21, 0, 0),
844 GATE(GOUT_CLKCMU_FSYS0_PCIE, "gout_clkcmu_fsys0_pcie",
845 "mout_clkcmu_fsys0_pcie", CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE,
846 21, 0, 0),
847
848 /* FSYS1 */
849 GATE(GOUT_CLKCMU_FSYS1_BUS, "gout_clkcmu_fsys1_bus",
850 "mout_clkcmu_fsys1_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,
851 21, 0, 0),
852 GATE(GOUT_CLKCMU_FSYS1_USBDRD, "gout_clkcmu_fsys1_usbdrd",
853 "mout_clkcmu_fsys1_usbdrd", CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD,
854 21, 0, 0),
855 GATE(GOUT_CLKCMU_FSYS1_MMC_CARD, "gout_clkcmu_fsys1_mmc_card",
856 "mout_clkcmu_fsys1_mmc_card",
857 CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD, 21, 0, 0),
858
859 /* FSYS2 */
860 GATE(GOUT_CLKCMU_FSYS2_BUS, "gout_clkcmu_fsys2_bus",
861 "mout_clkcmu_fsys2_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS,
862 21, 0, 0),
863 GATE(GOUT_CLKCMU_FSYS2_UFS_EMBD, "gout_clkcmu_fsys2_ufs_embd",
864 "mout_clkcmu_fsys2_ufs_embd",
865 CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD, 21, 0, 0),
866 GATE(GOUT_CLKCMU_FSYS2_ETHERNET, "gout_clkcmu_fsys2_ethernet",
867 "mout_clkcmu_fsys2_ethernet",
868 CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET, 21, 0, 0),
869
870 /* G2D */
871 GATE(GOUT_CLKCMU_G2D_G2D, "gout_clkcmu_g2d_g2d",
872 "mout_clkcmu_g2d_g2d", CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
873 GATE(GOUT_CLKCMU_G2D_MSCL, "gout_clkcmu_g2d_mscl",
874 "mout_clkcmu_g2d_mscl", CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
875 21, 0, 0),
876
877 /* G3D0 */
878 GATE(GOUT_CLKCMU_G3D00_SWITCH, "gout_clkcmu_g3d00_switch",
879 "mout_clkcmu_g3d00_switch", CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH,
880 21, 0, 0),
881 GATE(GOUT_CLKCMU_G3D01_SWITCH, "gout_clkcmu_g3d01_switch",
882 "mout_clkcmu_g3d01_switch", CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH,
883 21, 0, 0),
884
885 /* G3D1 */
886 GATE(GOUT_CLKCMU_G3D1_SWITCH, "gout_clkcmu_g3d1_switch",
887 "mout_clkcmu_g3d1_switch", CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH,
888 21, 0, 0),
889
890 /* ISPB */
891 GATE(GOUT_CLKCMU_ISPB_BUS, "gout_clkcmu_ispb_bus",
892 "mout_clkcmu_ispb_bus", CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS,
893 21, 0, 0),
894
895 /* MFC */
896 GATE(GOUT_CLKCMU_MFC_MFC, "gout_clkcmu_mfc_mfc", "mout_clkcmu_mfc_mfc",
897 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
898 GATE(GOUT_CLKCMU_MFC_WFD, "gout_clkcmu_mfc_wfd", "mout_clkcmu_mfc_wfd",
899 CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, 21, 0, 0),
900
901 /* MIF */
902 GATE(GOUT_CLKCMU_MIF_SWITCH, "gout_clkcmu_mif_switch",
903 "mout_clkcmu_mif_switch", CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH,
904 21, CLK_IGNORE_UNUSED, 0),
905 GATE(GOUT_CLKCMU_MIF_BUSP, "gout_clkcmu_mif_busp",
906 "mout_clkcmu_mif_busp", CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
907 21, CLK_IGNORE_UNUSED, 0),
908
909 /* NPU */
910 GATE(GOUT_CLKCMU_NPU_BUS, "gout_clkcmu_npu_bus", "mout_clkcmu_npu_bus",
911 CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 21, 0, 0),
912
913 /* PERIC0 */
914 GATE(GOUT_CLKCMU_PERIC0_BUS, "gout_clkcmu_peric0_bus",
915 "mout_clkcmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
916 21, 0, 0),
917 GATE(GOUT_CLKCMU_PERIC0_IP, "gout_clkcmu_peric0_ip",
918 "mout_clkcmu_peric0_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
919 21, 0, 0),
920
921 /* PERIC1 */
922 GATE(GOUT_CLKCMU_PERIC1_BUS, "gout_clkcmu_peric1_bus",
923 "mout_clkcmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
924 21, 0, 0),
925 GATE(GOUT_CLKCMU_PERIC1_IP, "gout_clkcmu_peric1_ip",
926 "mout_clkcmu_peric1_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
927 21, 0, 0),
928
929 /* PERIS */
930 GATE(GOUT_CLKCMU_PERIS_BUS, "gout_clkcmu_peris_bus",
931 "mout_clkcmu_peris_bus", CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
932 21, CLK_IGNORE_UNUSED, 0),
933 };
934
935 static const struct samsung_cmu_info top_cmu_info __initconst = {
936 .pll_clks = top_pll_clks,
937 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
938 .mux_clks = top_mux_clks,
939 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
940 .div_clks = top_div_clks,
941 .nr_div_clks = ARRAY_SIZE(top_div_clks),
942 .fixed_factor_clks = top_fixed_factor_clks,
943 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
944 .gate_clks = top_gate_clks,
945 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
946 .nr_clk_ids = TOP_NR_CLK,
947 .clk_regs = top_clk_regs,
948 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
949 };
950
exynosautov9_cmu_top_init(struct device_node * np)951 static void __init exynosautov9_cmu_top_init(struct device_node *np)
952 {
953 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
954 }
955
956 /* Register CMU_TOP early, as it's a dependency for other early domains */
957 CLK_OF_DECLARE(exynosautov9_cmu_top, "samsung,exynosautov9-cmu-top",
958 exynosautov9_cmu_top_init);
959
960 /* ---- CMU_BUSMC ---------------------------------------------------------- */
961
962 /* Register Offset definitions for CMU_BUSMC (0x1b200000) */
963 #define PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER 0x0600
964 #define CLK_CON_DIV_DIV_CLK_BUSMC_BUSP 0x1800
965 #define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK 0x2078
966 #define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2080
967
968 static const unsigned long busmc_clk_regs[] __initconst = {
969 PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER,
970 CLK_CON_DIV_DIV_CLK_BUSMC_BUSP,
971 CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK,
972 CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK,
973 };
974
975 /* List of parent clocks for Muxes in CMU_BUSMC */
976 PNAME(mout_busmc_bus_user_p) = { "oscclk", "dout_clkcmu_busmc_bus" };
977
978 static const struct samsung_mux_clock busmc_mux_clks[] __initconst = {
979 MUX(CLK_MOUT_BUSMC_BUS_USER, "mout_busmc_bus_user",
980 mout_busmc_bus_user_p, PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER, 4, 1),
981 };
982
983 static const struct samsung_div_clock busmc_div_clks[] __initconst = {
984 DIV(CLK_DOUT_BUSMC_BUSP, "dout_busmc_busp", "mout_busmc_bus_user",
985 CLK_CON_DIV_DIV_CLK_BUSMC_BUSP, 0, 3),
986 };
987
988 static const struct samsung_gate_clock busmc_gate_clks[] __initconst = {
989 GATE(CLK_GOUT_BUSMC_PDMA0_PCLK, "gout_busmc_pdma0_pclk",
990 "dout_busmc_busp",
991 CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK, 21,
992 0, 0),
993 GATE(CLK_GOUT_BUSMC_SPDMA_PCLK, "gout_busmc_spdma_pclk",
994 "dout_busmc_busp",
995 CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK, 21,
996 0, 0),
997 };
998
999 static const struct samsung_cmu_info busmc_cmu_info __initconst = {
1000 .mux_clks = busmc_mux_clks,
1001 .nr_mux_clks = ARRAY_SIZE(busmc_mux_clks),
1002 .div_clks = busmc_div_clks,
1003 .nr_div_clks = ARRAY_SIZE(busmc_div_clks),
1004 .gate_clks = busmc_gate_clks,
1005 .nr_gate_clks = ARRAY_SIZE(busmc_gate_clks),
1006 .nr_clk_ids = BUSMC_NR_CLK,
1007 .clk_regs = busmc_clk_regs,
1008 .nr_clk_regs = ARRAY_SIZE(busmc_clk_regs),
1009 .clk_name = "dout_clkcmu_busmc_bus",
1010 };
1011
1012 /* ---- CMU_CORE ----------------------------------------------------------- */
1013
1014 /* Register Offset definitions for CMU_CORE (0x1b030000) */
1015 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600
1016 #define CLK_CON_MUX_MUX_CORE_CMUREF 0x1000
1017 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
1018 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK 0x2000
1019 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK 0x2004
1020 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK 0x2008
1021
1022 static const unsigned long core_clk_regs[] __initconst = {
1023 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
1024 CLK_CON_MUX_MUX_CORE_CMUREF,
1025 CLK_CON_DIV_DIV_CLK_CORE_BUSP,
1026 CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK,
1027 CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK,
1028 CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK,
1029 };
1030
1031 /* List of parent clocks for Muxes in CMU_CORE */
1032 PNAME(mout_core_bus_user_p) = { "oscclk", "dout_clkcmu_core_bus" };
1033
1034 static const struct samsung_mux_clock core_mux_clks[] __initconst = {
1035 MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
1036 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
1037 };
1038
1039 static const struct samsung_div_clock core_div_clks[] __initconst = {
1040 DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
1041 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 3),
1042 };
1043
1044 static const struct samsung_gate_clock core_gate_clks[] __initconst = {
1045 GATE(CLK_GOUT_CORE_CCI_CLK, "gout_core_cci_clk", "mout_core_bus_user",
1046 CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK, 21,
1047 CLK_IS_CRITICAL, 0),
1048 GATE(CLK_GOUT_CORE_CCI_PCLK, "gout_core_cci_pclk", "dout_core_busp",
1049 CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK, 21,
1050 CLK_IS_CRITICAL, 0),
1051 GATE(CLK_GOUT_CORE_CMU_CORE_PCLK, "gout_core_cmu_core_pclk",
1052 "dout_core_busp",
1053 CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, 21,
1054 CLK_IS_CRITICAL, 0),
1055 };
1056
1057 static const struct samsung_cmu_info core_cmu_info __initconst = {
1058 .mux_clks = core_mux_clks,
1059 .nr_mux_clks = ARRAY_SIZE(core_mux_clks),
1060 .div_clks = core_div_clks,
1061 .nr_div_clks = ARRAY_SIZE(core_div_clks),
1062 .gate_clks = core_gate_clks,
1063 .nr_gate_clks = ARRAY_SIZE(core_gate_clks),
1064 .nr_clk_ids = CORE_NR_CLK,
1065 .clk_regs = core_clk_regs,
1066 .nr_clk_regs = ARRAY_SIZE(core_clk_regs),
1067 .clk_name = "dout_clkcmu_core_bus",
1068 };
1069
1070 /* ---- CMU_FSYS0 ---------------------------------------------------------- */
1071
1072 /* Register Offset definitions for CMU_FSYS2 (0x17700000) */
1073 #define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER 0x0600
1074 #define PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER 0x0610
1075 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x2000
1076
1077 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN 0x2004
1078 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN 0x2008
1079 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN 0x200c
1080 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN 0x2010
1081 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN 0x2014
1082 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN 0x2018
1083
1084 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK 0x205c
1085 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK 0x2060
1086 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK 0x2064
1087 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK 0x206c
1088 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK 0x2070
1089 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK 0x2074
1090 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK 0x207c
1091
1092 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK 0x2084
1093 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK 0x2088
1094 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK 0x208c
1095 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK 0x2094
1096 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK 0x2098
1097 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK 0x209c
1098 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK 0x20a4
1099
1100 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK 0x20ac
1101 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK 0x20b0
1102 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK 0x20b4
1103 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK 0x20bc
1104 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK 0x20c0
1105 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK 0x20c4
1106 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK 0x20cc
1107
1108 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK 0x20d4
1109 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK 0x20d8
1110 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK 0x20dc
1111 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK 0x20e0
1112 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK 0x20e4
1113 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK 0x20e8
1114
1115
1116 static const unsigned long fsys0_clk_regs[] __initconst = {
1117 PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER,
1118 PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER,
1119 CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
1120 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN,
1121 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN,
1122 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN,
1123 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN,
1124 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN,
1125 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN,
1126 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK,
1127 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK,
1128 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK,
1129 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK,
1130 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK,
1131 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK,
1132 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK,
1133 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK,
1134 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK,
1135 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK,
1136 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK,
1137 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK,
1138 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK,
1139 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK,
1140 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK,
1141 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK,
1142 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK,
1143 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK,
1144 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK,
1145 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK,
1146 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK,
1147 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK,
1148 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK,
1149 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK,
1150 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK,
1151 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK,
1152 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK,
1153 };
1154
1155 /* List of parent clocks for Muxes in CMU_FSYS0 */
1156 PNAME(mout_fsys0_bus_user_p) = { "oscclk", "dout_clkcmu_fsys0_bus" };
1157 PNAME(mout_fsys0_pcie_user_p) = { "oscclk", "dout_clkcmu_fsys0_pcie" };
1158
1159 static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
1160 MUX(CLK_MOUT_FSYS0_BUS_USER, "mout_fsys0_bus_user",
1161 mout_fsys0_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER, 4, 1),
1162 MUX(CLK_MOUT_FSYS0_PCIE_USER, "mout_fsys0_pcie_user",
1163 mout_fsys0_pcie_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER, 4, 1),
1164 };
1165
1166 static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
1167 GATE(CLK_GOUT_FSYS0_BUS_PCLK, "gout_fsys0_bus_pclk",
1168 "mout_fsys0_bus_user",
1169 CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
1170 21, CLK_IGNORE_UNUSED, 0),
1171
1172 /* Gen3 2L0 */
1173 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK,
1174 "gout_fsys0_pcie_gen3_2l0_x1_refclk", "mout_fsys0_pcie_user",
1175 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN,
1176 21, 0, 0),
1177 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK,
1178 "gout_fsys0_pcie_gen3_2l0_x2_refclk", "mout_fsys0_pcie_user",
1179 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN,
1180 21, 0, 0),
1181 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK,
1182 "gout_fsys0_pcie_gen3_2l0_x1_dbi_aclk", "mout_fsys0_bus_user",
1183 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK,
1184 21, 0, 0),
1185 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK,
1186 "gout_fsys0_pcie_gen3_2l0_x1_mstr_aclk", "mout_fsys0_bus_user",
1187 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK,
1188 21, 0, 0),
1189 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK,
1190 "gout_fsys0_pcie_gen3_2l0_x1_slv_aclk", "mout_fsys0_bus_user",
1191 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK,
1192 21, 0, 0),
1193 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK,
1194 "gout_fsys0_pcie_gen3_2l0_x2_dbi_aclk", "mout_fsys0_bus_user",
1195 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK,
1196 21, 0, 0),
1197 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK,
1198 "gout_fsys0_pcie_gen3_2l0_x2_mstr_aclk", "mout_fsys0_bus_user",
1199 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK,
1200 21, 0, 0),
1201 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK,
1202 "gout_fsys0_pcie_gen3_2l0_x2_slv_aclk", "mout_fsys0_bus_user",
1203 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK,
1204 21, 0, 0),
1205 GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK,
1206 "gout_fsys0_pcie_gen3a_2l0_clk", "mout_fsys0_pcie_user",
1207 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK,
1208 21, 0, 0),
1209 GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK,
1210 "gout_fsys0_pcie_gen3b_2l0_clk", "mout_fsys0_pcie_user",
1211 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK,
1212 21, 0, 0),
1213
1214 /* Gen3 2L1 */
1215 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK,
1216 "gout_fsys0_pcie_gen3_2l1_x1_refclk", "mout_fsys0_pcie_user",
1217 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN,
1218 21, 0, 0),
1219 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK,
1220 "gout_fsys0_pcie_gen3_2l1_x2_refclk", "mout_fsys0_pcie_user",
1221 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN,
1222 21, 0, 0),
1223 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK,
1224 "gout_fsys0_pcie_gen3_2l1_x1_dbi_aclk", "mout_fsys0_bus_user",
1225 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK,
1226 21, 0, 0),
1227 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK,
1228 "gout_fsys0_pcie_gen3_2l1_x1_mstr_aclk", "mout_fsys0_bus_user",
1229 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK,
1230 21, 0, 0),
1231 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK,
1232 "gout_fsys0_pcie_gen3_2l1_x1_slv_aclk", "mout_fsys0_bus_user",
1233 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK,
1234 21, 0, 0),
1235 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK,
1236 "gout_fsys0_pcie_gen3_2l1_x2_dbi_aclk", "mout_fsys0_bus_user",
1237 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK,
1238 21, 0, 0),
1239 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK,
1240 "gout_fsys0_pcie_gen3_2l1_x2_mstr_aclk", "mout_fsys0_bus_user",
1241 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK,
1242 21, 0, 0),
1243 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK,
1244 "gout_fsys0_pcie_gen3_2l1_x2_slv_aclk", "mout_fsys0_bus_user",
1245 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK,
1246 21, 0, 0),
1247 GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK,
1248 "gout_fsys0_pcie_gen3a_2l1_clk", "mout_fsys0_pcie_user",
1249 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK,
1250 21, 0, 0),
1251 GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK,
1252 "gout_fsys0_pcie_gen3b_2l1_clk", "mout_fsys0_pcie_user",
1253 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK,
1254 21, 0, 0),
1255
1256 /* Gen3 4L */
1257 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK,
1258 "gout_fsys0_pcie_gen3_4l_x2_refclk", "mout_fsys0_pcie_user",
1259 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN,
1260 21, 0, 0),
1261 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK,
1262 "gout_fsys0_pcie_gen3_4l_x4_refclk", "mout_fsys0_pcie_user",
1263 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN,
1264 21, 0, 0),
1265 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK,
1266 "gout_fsys0_pcie_gen3_4l_x2_dbi_aclk", "mout_fsys0_bus_user",
1267 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK,
1268 21, 0, 0),
1269 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK,
1270 "gout_fsys0_pcie_gen3_4l_x2_mstr_aclk", "mout_fsys0_bus_user",
1271 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK,
1272 21, 0, 0),
1273 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK,
1274 "gout_fsys0_pcie_gen3_4l_x2_slv_aclk", "mout_fsys0_bus_user",
1275 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK,
1276 21, 0, 0),
1277 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK,
1278 "gout_fsys0_pcie_gen3_4l_x4_dbi_aclk", "mout_fsys0_bus_user",
1279 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK,
1280 21, 0, 0),
1281 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK,
1282 "gout_fsys0_pcie_gen3_4l_x4_mstr_aclk", "mout_fsys0_bus_user",
1283 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK,
1284 21, 0, 0),
1285 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK,
1286 "gout_fsys0_pcie_gen3_4l_x4_slv_aclk", "mout_fsys0_bus_user",
1287 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK,
1288 21, 0, 0),
1289 GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK,
1290 "gout_fsys0_pcie_gen3a_4l_clk", "mout_fsys0_pcie_user",
1291 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK,
1292 21, 0, 0),
1293 GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK,
1294 "gout_fsys0_pcie_gen3b_4l_clk", "mout_fsys0_pcie_user",
1295 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK,
1296 21, 0, 0),
1297 };
1298
1299 static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
1300 .mux_clks = fsys0_mux_clks,
1301 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
1302 .gate_clks = fsys0_gate_clks,
1303 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
1304 .nr_clk_ids = FSYS0_NR_CLK,
1305 .clk_regs = fsys0_clk_regs,
1306 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
1307 .clk_name = "dout_clkcmu_fsys0_bus",
1308 };
1309
1310 /* ---- CMU_FSYS1 ---------------------------------------------------------- */
1311
1312 /* Register Offset definitions for CMU_FSYS1 (0x17040000) */
1313 #define PLL_LOCKTIME_PLL_MMC 0x0000
1314 #define PLL_CON0_PLL_MMC 0x0100
1315 #define PLL_CON3_PLL_MMC 0x010c
1316 #define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0600
1317 #define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0610
1318 #define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER 0x0620
1319
1320 #define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD 0x1000
1321 #define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD 0x1800
1322
1323 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2018
1324 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x202c
1325 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2028
1326
1327 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 0x204c
1328 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 0x2058
1329 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 0x2064
1330 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 0x2070
1331
1332 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK 0x2074
1333 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK 0x2078
1334 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK 0x207c
1335 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK 0x2080
1336
1337 static const unsigned long fsys1_clk_regs[] __initconst = {
1338 PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER,
1339 };
1340
1341 static const struct samsung_pll_clock fsys1_pll_clks[] __initconst = {
1342 PLL(pll_0831x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
1343 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
1344 };
1345
1346 /* List of parent clocks for Muxes in CMU_FSYS1 */
1347 PNAME(mout_fsys1_bus_user_p) = { "oscclk", "dout_clkcmu_fsys1_bus" };
1348 PNAME(mout_fsys1_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
1349 PNAME(mout_fsys1_mmc_card_user_p) = { "oscclk", "gout_clkcmu_fsys1_mmc_card" };
1350 PNAME(mout_fsys1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_fsys1_usbdrd" };
1351 PNAME(mout_fsys1_mmc_card_p) = { "mout_fsys1_mmc_card_user",
1352 "mout_fsys1_mmc_pll" };
1353
1354 static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
1355 MUX(CLK_MOUT_FSYS1_BUS_USER, "mout_fsys1_bus_user",
1356 mout_fsys1_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 4, 1),
1357 MUX(CLK_MOUT_FSYS1_MMC_PLL, "mout_fsys1_mmc_pll", mout_fsys1_mmc_pll_p,
1358 PLL_CON0_PLL_MMC, 4, 1),
1359 MUX(CLK_MOUT_FSYS1_MMC_CARD_USER, "mout_fsys1_mmc_card_user",
1360 mout_fsys1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER,
1361 4, 1),
1362 MUX(CLK_MOUT_FSYS1_USBDRD_USER, "mout_fsys1_usbdrd_user",
1363 mout_fsys1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER,
1364 4, 1),
1365 MUX(CLK_MOUT_FSYS1_MMC_CARD, "mout_fsys1_mmc_card",
1366 mout_fsys1_mmc_card_p, CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD,
1367 0, 1),
1368 };
1369
1370 static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
1371 DIV(CLK_DOUT_FSYS1_MMC_CARD, "dout_fsys1_mmc_card",
1372 "mout_fsys1_mmc_card",
1373 CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD, 0, 9),
1374 };
1375
1376 static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
1377 GATE(CLK_GOUT_FSYS1_PCLK, "gout_fsys1_pclk", "mout_fsys1_bus_user",
1378 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
1379 21, CLK_IGNORE_UNUSED, 0),
1380 GATE(CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN, "gout_fsys1_mmc_card_sdclkin",
1381 "dout_fsys1_mmc_card",
1382 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
1383 21, CLK_SET_RATE_PARENT, 0),
1384 GATE(CLK_GOUT_FSYS1_MMC_CARD_ACLK, "gout_fsys1_mmc_card_aclk",
1385 "dout_fsys1_mmc_card",
1386 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
1387 21, 0, 0),
1388 GATE(CLK_GOUT_FSYS1_USB20DRD_0_REFCLK, "gout_fsys1_usb20drd_0_refclk",
1389 "mout_fsys1_usbdrd_user",
1390 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40,
1391 21, 0, 0),
1392 GATE(CLK_GOUT_FSYS1_USB20DRD_1_REFCLK, "gout_fsys1_usb20drd_1_refclk",
1393 "mout_fsys1_usbdrd_user",
1394 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40,
1395 21, 0, 0),
1396 GATE(CLK_GOUT_FSYS1_USB30DRD_0_REFCLK, "gout_fsys1_usb30drd_0_refclk",
1397 "mout_fsys1_usbdrd_user",
1398 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40,
1399 21, 0, 0),
1400 GATE(CLK_GOUT_FSYS1_USB30DRD_1_REFCLK, "gout_fsys1_usb30drd_1_refclk",
1401 "mout_fsys1_usbdrd_user",
1402 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40,
1403 21, 0, 0),
1404 GATE(CLK_GOUT_FSYS1_USB20_0_ACLK, "gout_fsys1_usb20_0_aclk",
1405 "mout_fsys1_usbdrd_user",
1406 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK,
1407 21, 0, 0),
1408 GATE(CLK_GOUT_FSYS1_USB20_1_ACLK, "gout_fsys1_usb20_1_aclk",
1409 "mout_fsys1_usbdrd_user",
1410 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK,
1411 21, 0, 0),
1412 GATE(CLK_GOUT_FSYS1_USB30_0_ACLK, "gout_fsys1_usb30_0_aclk",
1413 "mout_fsys1_usbdrd_user",
1414 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK,
1415 21, 0, 0),
1416 GATE(CLK_GOUT_FSYS1_USB30_1_ACLK, "gout_fsys1_usb30_1_aclk",
1417 "mout_fsys1_usbdrd_user",
1418 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK,
1419 21, 0, 0),
1420 };
1421
1422 static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
1423 .pll_clks = fsys1_pll_clks,
1424 .nr_pll_clks = ARRAY_SIZE(fsys1_pll_clks),
1425 .mux_clks = fsys1_mux_clks,
1426 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
1427 .div_clks = fsys1_div_clks,
1428 .nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
1429 .gate_clks = fsys1_gate_clks,
1430 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
1431 .nr_clk_ids = FSYS1_NR_CLK,
1432 .clk_regs = fsys1_clk_regs,
1433 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
1434 .clk_name = "dout_clkcmu_fsys1_bus",
1435 };
1436
1437 /* ---- CMU_FSYS2 ---------------------------------------------------------- */
1438
1439 /* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
1440 #define PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER 0x0600
1441 #define PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER 0x0620
1442 #define PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER 0x0610
1443 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK 0x2098
1444 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO 0x209c
1445 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK 0x20a4
1446 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO 0x20a8
1447
1448 static const unsigned long fsys2_clk_regs[] __initconst = {
1449 PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER,
1450 PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER,
1451 PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER,
1452 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK,
1453 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO,
1454 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK,
1455 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO,
1456 };
1457
1458 /* List of parent clocks for Muxes in CMU_FSYS2 */
1459 PNAME(mout_fsys2_bus_user_p) = { "oscclk", "dout_clkcmu_fsys2_bus" };
1460 PNAME(mout_fsys2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_fsys2_ufs_embd" };
1461 PNAME(mout_fsys2_ethernet_user_p) = { "oscclk", "dout_clkcmu_fsys2_ethernet" };
1462
1463 static const struct samsung_mux_clock fsys2_mux_clks[] __initconst = {
1464 MUX(CLK_MOUT_FSYS2_BUS_USER, "mout_fsys2_bus_user",
1465 mout_fsys2_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER, 4, 1),
1466 MUX(CLK_MOUT_FSYS2_UFS_EMBD_USER, "mout_fsys2_ufs_embd_user",
1467 mout_fsys2_ufs_embd_user_p,
1468 PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER, 4, 1),
1469 MUX(CLK_MOUT_FSYS2_ETHERNET_USER, "mout_fsys2_ethernet_user",
1470 mout_fsys2_ethernet_user_p,
1471 PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER, 4, 1),
1472 };
1473
1474 static const struct samsung_gate_clock fsys2_gate_clks[] __initconst = {
1475 GATE(CLK_GOUT_FSYS2_UFS_EMBD0_ACLK, "gout_fsys2_ufs_embd0_aclk",
1476 "mout_fsys2_ufs_embd_user",
1477 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK, 21,
1478 0, 0),
1479 GATE(CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO, "gout_fsys2_ufs_embd0_unipro",
1480 "mout_fsys2_ufs_embd_user",
1481 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO,
1482 21, 0, 0),
1483 GATE(CLK_GOUT_FSYS2_UFS_EMBD1_ACLK, "gout_fsys2_ufs_embd1_aclk",
1484 "mout_fsys2_ufs_embd_user",
1485 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK, 21,
1486 0, 0),
1487 GATE(CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO, "gout_fsys2_ufs_embd1_unipro",
1488 "mout_fsys2_ufs_embd_user",
1489 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO,
1490 21, 0, 0),
1491 };
1492
1493 static const struct samsung_cmu_info fsys2_cmu_info __initconst = {
1494 .mux_clks = fsys2_mux_clks,
1495 .nr_mux_clks = ARRAY_SIZE(fsys2_mux_clks),
1496 .gate_clks = fsys2_gate_clks,
1497 .nr_gate_clks = ARRAY_SIZE(fsys2_gate_clks),
1498 .nr_clk_ids = FSYS2_NR_CLK,
1499 .clk_regs = fsys2_clk_regs,
1500 .nr_clk_regs = ARRAY_SIZE(fsys2_clk_regs),
1501 .clk_name = "dout_clkcmu_fsys2_bus",
1502 };
1503
1504 /* ---- CMU_PERIC0 --------------------------------------------------------- */
1505
1506 /* Register Offset definitions for CMU_PERIC0 (0x10200000) */
1507 #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
1508 #define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0610
1509 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1000
1510 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1004
1511 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x1008
1512 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x100c
1513 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1010
1514 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1014
1515 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1018
1516 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1800
1517 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1804
1518 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x1808
1519 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x180c
1520 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1810
1521 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1814
1522 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1818
1523 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x2014
1524 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2018
1525 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x2024
1526 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2028
1527 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x202c
1528 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2030
1529 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x2034
1530 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2038
1531 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x203c
1532 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2040
1533 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x201c
1534 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2020
1535 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x2044
1536 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2048
1537 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x2058
1538 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x205c
1539 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060
1540 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064
1541 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068
1542 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
1543 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070
1544 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074
1545 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x204c
1546 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2050
1547
1548 static const unsigned long peric0_clk_regs[] __initconst = {
1549 PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
1550 PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER,
1551 CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI,
1552 CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI,
1553 CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI,
1554 CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI,
1555 CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI,
1556 CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI,
1557 CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C,
1558 CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1559 CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1560 CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1561 CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1562 CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1563 CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1564 CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
1565 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
1566 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
1567 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
1568 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
1569 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
1570 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
1571 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
1572 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
1573 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
1574 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
1575 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
1576 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
1577 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
1578 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
1579 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
1580 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
1581 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
1582 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
1583 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
1584 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
1585 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
1586 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
1587 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
1588 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
1589 };
1590
1591 /* List of parent clocks for Muxes in CMU_PERIC0 */
1592 PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_clkcmu_peric0_bus" };
1593 PNAME(mout_peric0_ip_user_p) = { "oscclk", "dout_clkcmu_peric0_ip" };
1594 PNAME(mout_peric0_usi_p) = { "oscclk", "mout_peric0_ip_user" };
1595
1596 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
1597 MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
1598 mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1),
1599 MUX(CLK_MOUT_PERIC0_IP_USER, "mout_peric0_ip_user",
1600 mout_peric0_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 4, 1),
1601 /* USI00 ~ USI05 */
1602 MUX(CLK_MOUT_PERIC0_USI00_USI, "mout_peric0_usi00_usi",
1603 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),
1604 MUX(CLK_MOUT_PERIC0_USI01_USI, "mout_peric0_usi01_usi",
1605 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),
1606 MUX(CLK_MOUT_PERIC0_USI02_USI, "mout_peric0_usi02_usi",
1607 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),
1608 MUX(CLK_MOUT_PERIC0_USI03_USI, "mout_peric0_usi03_usi",
1609 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),
1610 MUX(CLK_MOUT_PERIC0_USI04_USI, "mout_peric0_usi04_usi",
1611 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),
1612 MUX(CLK_MOUT_PERIC0_USI05_USI, "mout_peric0_usi05_usi",
1613 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),
1614 /* USI_I2C */
1615 MUX(CLK_MOUT_PERIC0_USI_I2C, "mout_peric0_usi_i2c",
1616 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),
1617 };
1618
1619 static const struct samsung_div_clock peric0_div_clks[] __initconst = {
1620 /* USI00 ~ USI05 */
1621 DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
1622 "mout_peric0_usi00_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1623 0, 4),
1624 DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
1625 "mout_peric0_usi01_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1626 0, 4),
1627 DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
1628 "mout_peric0_usi02_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1629 0, 4),
1630 DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
1631 "mout_peric0_usi03_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1632 0, 4),
1633 DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
1634 "mout_peric0_usi04_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1635 0, 4),
1636 DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
1637 "mout_peric0_usi05_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1638 0, 4),
1639 /* USI_I2C */
1640 DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c",
1641 "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),
1642 };
1643
1644 static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
1645 /* IPCLK */
1646 GATE(CLK_GOUT_PERIC0_IPCLK_0, "gout_peric0_ipclk_0",
1647 "dout_peric0_usi00_usi",
1648 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
1649 21, 0, 0),
1650 GATE(CLK_GOUT_PERIC0_IPCLK_1, "gout_peric0_ipclk_1",
1651 "dout_peric0_usi_i2c",
1652 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
1653 21, 0, 0),
1654 GATE(CLK_GOUT_PERIC0_IPCLK_2, "gout_peric0_ipclk_2",
1655 "dout_peric0_usi01_usi",
1656 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
1657 21, 0, 0),
1658 GATE(CLK_GOUT_PERIC0_IPCLK_3, "gout_peric0_ipclk_3",
1659 "dout_peric0_usi_i2c",
1660 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
1661 21, 0, 0),
1662 GATE(CLK_GOUT_PERIC0_IPCLK_4, "gout_peric0_ipclk_4",
1663 "dout_peric0_usi02_usi",
1664 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
1665 21, 0, 0),
1666 GATE(CLK_GOUT_PERIC0_IPCLK_5, "gout_peric0_ipclk_5",
1667 "dout_peric0_usi_i2c",
1668 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
1669 21, 0, 0),
1670 GATE(CLK_GOUT_PERIC0_IPCLK_6, "gout_peric0_ipclk_6",
1671 "dout_peric0_usi03_usi",
1672 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
1673 21, 0, 0),
1674 GATE(CLK_GOUT_PERIC0_IPCLK_7, "gout_peric0_ipclk_7",
1675 "dout_peric0_usi_i2c",
1676 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
1677 21, 0, 0),
1678 GATE(CLK_GOUT_PERIC0_IPCLK_8, "gout_peric0_ipclk_8",
1679 "dout_peric0_usi04_usi",
1680 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
1681 21, 0, 0),
1682 GATE(CLK_GOUT_PERIC0_IPCLK_9, "gout_peric0_ipclk_9",
1683 "dout_peric0_usi_i2c",
1684 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
1685 21, 0, 0),
1686 GATE(CLK_GOUT_PERIC0_IPCLK_10, "gout_peric0_ipclk_10",
1687 "dout_peric0_usi05_usi",
1688 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
1689 21, 0, 0),
1690 GATE(CLK_GOUT_PERIC0_IPCLK_11, "gout_peric0_ipclk_11",
1691 "dout_peric0_usi_i2c",
1692 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
1693 21, 0, 0),
1694
1695 /* PCLK */
1696 GATE(CLK_GOUT_PERIC0_PCLK_0, "gout_peric0_pclk_0",
1697 "mout_peric0_bus_user",
1698 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
1699 21, 0, 0),
1700 GATE(CLK_GOUT_PERIC0_PCLK_1, "gout_peric0_pclk_1",
1701 "mout_peric0_bus_user",
1702 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
1703 21, 0, 0),
1704 GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2",
1705 "mout_peric0_bus_user",
1706 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
1707 21, 0, 0),
1708 GATE(CLK_GOUT_PERIC0_PCLK_3, "gout_peric0_pclk_3",
1709 "mout_peric0_bus_user",
1710 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
1711 21, 0, 0),
1712 GATE(CLK_GOUT_PERIC0_PCLK_4, "gout_peric0_pclk_4",
1713 "mout_peric0_bus_user",
1714 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
1715 21, 0, 0),
1716 GATE(CLK_GOUT_PERIC0_PCLK_5, "gout_peric0_pclk_5",
1717 "mout_peric0_bus_user",
1718 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
1719 21, 0, 0),
1720 GATE(CLK_GOUT_PERIC0_PCLK_6, "gout_peric0_pclk_6",
1721 "mout_peric0_bus_user",
1722 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
1723 21, 0, 0),
1724 GATE(CLK_GOUT_PERIC0_PCLK_7, "gout_peric0_pclk_7",
1725 "mout_peric0_bus_user",
1726 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
1727 21, 0, 0),
1728 GATE(CLK_GOUT_PERIC0_PCLK_8, "gout_peric0_pclk_8",
1729 "mout_peric0_bus_user",
1730 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
1731 21, 0, 0),
1732 GATE(CLK_GOUT_PERIC0_PCLK_9, "gout_peric0_pclk_9",
1733 "mout_peric0_bus_user",
1734 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
1735 21, 0, 0),
1736 GATE(CLK_GOUT_PERIC0_PCLK_10, "gout_peric0_pclk_10",
1737 "mout_peric0_bus_user",
1738 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
1739 21, 0, 0),
1740 GATE(CLK_GOUT_PERIC0_PCLK_11, "gout_peric0_pclk_11",
1741 "mout_peric0_bus_user",
1742 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
1743 21, 0, 0),
1744 };
1745
1746 static const struct samsung_cmu_info peric0_cmu_info __initconst = {
1747 .mux_clks = peric0_mux_clks,
1748 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
1749 .div_clks = peric0_div_clks,
1750 .nr_div_clks = ARRAY_SIZE(peric0_div_clks),
1751 .gate_clks = peric0_gate_clks,
1752 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
1753 .nr_clk_ids = PERIC0_NR_CLK,
1754 .clk_regs = peric0_clk_regs,
1755 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
1756 .clk_name = "dout_clkcmu_peric0_bus",
1757 };
1758
1759 /* ---- CMU_PERIC1 --------------------------------------------------------- */
1760
1761 /* Register Offset definitions for CMU_PERIC1 (0x10800000) */
1762 #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
1763 #define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x0610
1764 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI 0x1000
1765 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI 0x1004
1766 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI 0x1008
1767 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x100c
1768 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1010
1769 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x1014
1770 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1018
1771 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI 0x1800
1772 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI 0x1804
1773 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI 0x1808
1774 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x180c
1775 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1810
1776 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x1814
1777 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1818
1778 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0 0x2014
1779 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2018
1780 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024
1781 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028
1782 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c
1783 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030
1784 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034
1785 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7 0x2038
1786 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x203c
1787 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9 0x2040
1788 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10 0x201c
1789 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0x2020
1790 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0 0x2044
1791 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x2048
1792 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2054
1793 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2058
1794 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x205c
1795 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2060
1796 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2064
1797 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0x2068
1798 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x206c
1799 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0x2070
1800 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x204c
1801 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x2050
1802
1803 static const unsigned long peric1_clk_regs[] __initconst = {
1804 PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
1805 PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER,
1806 CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI,
1807 CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI,
1808 CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI,
1809 CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI,
1810 CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI,
1811 CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI,
1812 CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C,
1813 CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
1814 CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
1815 CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
1816 CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1817 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1818 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1819 CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
1820 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0,
1821 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
1822 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
1823 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
1824 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
1825 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
1826 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
1827 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7,
1828 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
1829 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9,
1830 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10,
1831 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11,
1832 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
1833 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
1834 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
1835 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
1836 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
1837 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
1838 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
1839 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
1840 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
1841 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9,
1842 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
1843 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11,
1844 };
1845
1846 /* List of parent clocks for Muxes in CMU_PERIC1 */
1847 PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_clkcmu_peric1_bus" };
1848 PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" };
1849 PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" };
1850
1851 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
1852 MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
1853 mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1),
1854 MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user",
1855 mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1),
1856 /* USI06 ~ USI11 */
1857 MUX(CLK_MOUT_PERIC1_USI06_USI, "mout_peric1_usi06_usi",
1858 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI, 0, 1),
1859 MUX(CLK_MOUT_PERIC1_USI07_USI, "mout_peric1_usi07_usi",
1860 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI, 0, 1),
1861 MUX(CLK_MOUT_PERIC1_USI08_USI, "mout_peric1_usi08_usi",
1862 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI, 0, 1),
1863 MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi",
1864 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
1865 MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi",
1866 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
1867 MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi",
1868 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
1869 /* USI_I2C */
1870 MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c",
1871 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
1872 };
1873
1874 static const struct samsung_div_clock peric1_div_clks[] __initconst = {
1875 /* USI06 ~ USI11 */
1876 DIV(CLK_DOUT_PERIC1_USI06_USI, "dout_peric1_usi06_usi",
1877 "mout_peric1_usi06_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
1878 0, 4),
1879 DIV(CLK_DOUT_PERIC1_USI07_USI, "dout_peric1_usi07_usi",
1880 "mout_peric1_usi07_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
1881 0, 4),
1882 DIV(CLK_DOUT_PERIC1_USI08_USI, "dout_peric1_usi08_usi",
1883 "mout_peric1_usi08_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
1884 0, 4),
1885 DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
1886 "mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1887 0, 4),
1888 DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
1889 "mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1890 0, 4),
1891 DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
1892 "mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1893 0, 4),
1894 /* USI_I2C */
1895 DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
1896 "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
1897 };
1898
1899 static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
1900 /* IPCLK */
1901 GATE(CLK_GOUT_PERIC1_IPCLK_0, "gout_peric1_ipclk_0",
1902 "dout_peric1_usi06_usi",
1903 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0,
1904 21, 0, 0),
1905 GATE(CLK_GOUT_PERIC1_IPCLK_1, "gout_peric1_ipclk_1",
1906 "dout_peric1_usi_i2c",
1907 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
1908 21, 0, 0),
1909 GATE(CLK_GOUT_PERIC1_IPCLK_2, "gout_peric1_ipclk_2",
1910 "dout_peric1_usi07_usi",
1911 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
1912 21, 0, 0),
1913 GATE(CLK_GOUT_PERIC1_IPCLK_3, "gout_peric1_ipclk_3",
1914 "dout_peric1_usi_i2c",
1915 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
1916 21, 0, 0),
1917 GATE(CLK_GOUT_PERIC1_IPCLK_4, "gout_peric1_ipclk_4",
1918 "dout_peric1_usi08_usi",
1919 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
1920 21, 0, 0),
1921 GATE(CLK_GOUT_PERIC1_IPCLK_5, "gout_peric1_ipclk_5",
1922 "dout_peric1_usi_i2c",
1923 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
1924 21, 0, 0),
1925 GATE(CLK_GOUT_PERIC1_IPCLK_6, "gout_peric1_ipclk_6",
1926 "dout_peric1_usi09_usi",
1927 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
1928 21, 0, 0),
1929 GATE(CLK_GOUT_PERIC1_IPCLK_7, "gout_peric1_ipclk_7",
1930 "dout_peric1_usi_i2c",
1931 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7,
1932 21, 0, 0),
1933 GATE(CLK_GOUT_PERIC1_IPCLK_8, "gout_peric1_ipclk_8",
1934 "dout_peric1_usi10_usi",
1935 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
1936 21, 0, 0),
1937 GATE(CLK_GOUT_PERIC1_IPCLK_9, "gout_peric1_ipclk_9",
1938 "dout_peric1_usi_i2c",
1939 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9,
1940 21, 0, 0),
1941 GATE(CLK_GOUT_PERIC1_IPCLK_10, "gout_peric1_ipclk_10",
1942 "dout_peric1_usi11_usi",
1943 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10,
1944 21, 0, 0),
1945 GATE(CLK_GOUT_PERIC1_IPCLK_11, "gout_peric1_ipclk_11",
1946 "dout_peric1_usi_i2c",
1947 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11,
1948 21, 0, 0),
1949
1950 /* PCLK */
1951 GATE(CLK_GOUT_PERIC1_PCLK_0, "gout_peric1_pclk_0",
1952 "mout_peric1_bus_user",
1953 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
1954 21, 0, 0),
1955 GATE(CLK_GOUT_PERIC1_PCLK_1, "gout_peric1_pclk_1",
1956 "mout_peric1_bus_user",
1957 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
1958 21, 0, 0),
1959 GATE(CLK_GOUT_PERIC1_PCLK_2, "gout_peric1_pclk_2",
1960 "mout_peric1_bus_user",
1961 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
1962 21, 0, 0),
1963 GATE(CLK_GOUT_PERIC1_PCLK_3, "gout_peric1_pclk_3",
1964 "mout_peric1_bus_user",
1965 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
1966 21, 0, 0),
1967 GATE(CLK_GOUT_PERIC1_PCLK_4, "gout_peric1_pclk_4",
1968 "mout_peric1_bus_user",
1969 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
1970 21, 0, 0),
1971 GATE(CLK_GOUT_PERIC1_PCLK_5, "gout_peric1_pclk_5",
1972 "mout_peric1_bus_user",
1973 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
1974 21, 0, 0),
1975 GATE(CLK_GOUT_PERIC1_PCLK_6, "gout_peric1_pclk_6",
1976 "mout_peric1_bus_user",
1977 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
1978 21, 0, 0),
1979 GATE(CLK_GOUT_PERIC1_PCLK_7, "gout_peric1_pclk_7",
1980 "mout_peric1_bus_user",
1981 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
1982 21, 0, 0),
1983 GATE(CLK_GOUT_PERIC1_PCLK_8, "gout_peric1_pclk_8",
1984 "mout_peric1_bus_user",
1985 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
1986 21, 0, 0),
1987 GATE(CLK_GOUT_PERIC1_PCLK_9, "gout_peric1_pclk_9",
1988 "mout_peric1_bus_user",
1989 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9,
1990 21, 0, 0),
1991 GATE(CLK_GOUT_PERIC1_PCLK_10, "gout_peric1_pclk_10",
1992 "mout_peric1_bus_user",
1993 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
1994 21, 0, 0),
1995 GATE(CLK_GOUT_PERIC1_PCLK_11, "gout_peric1_pclk_11",
1996 "mout_peric1_bus_user",
1997 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11,
1998 21, 0, 0),
1999 };
2000
2001 static const struct samsung_cmu_info peric1_cmu_info __initconst = {
2002 .mux_clks = peric1_mux_clks,
2003 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
2004 .div_clks = peric1_div_clks,
2005 .nr_div_clks = ARRAY_SIZE(peric1_div_clks),
2006 .gate_clks = peric1_gate_clks,
2007 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
2008 .nr_clk_ids = PERIC1_NR_CLK,
2009 .clk_regs = peric1_clk_regs,
2010 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
2011 .clk_name = "dout_clkcmu_peric1_bus",
2012 };
2013
2014 /* ---- CMU_PERIS ---------------------------------------------------------- */
2015
2016 /* Register Offset definitions for CMU_PERIS (0x10020000) */
2017 #define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER 0x0600
2018 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x2058
2019 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x205c
2020 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x2060
2021
2022 static const unsigned long peris_clk_regs[] __initconst = {
2023 PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,
2024 CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
2025 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
2026 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
2027 };
2028
2029 /* List of parent clocks for Muxes in CMU_PERIS */
2030 PNAME(mout_peris_bus_user_p) = { "oscclk", "dout_clkcmu_peris_bus" };
2031
2032 static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
2033 MUX(CLK_MOUT_PERIS_BUS_USER, "mout_peris_bus_user",
2034 mout_peris_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER, 4, 1),
2035 };
2036
2037 static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
2038 GATE(CLK_GOUT_SYSREG_PERIS_PCLK, "gout_sysreg_peris_pclk",
2039 "mout_peris_bus_user",
2040 CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
2041 21, CLK_IGNORE_UNUSED, 0),
2042 GATE(CLK_GOUT_WDT_CLUSTER0, "gout_wdt_cluster0", "mout_peris_bus_user",
2043 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
2044 21, 0, 0),
2045 GATE(CLK_GOUT_WDT_CLUSTER1, "gout_wdt_cluster1", "mout_peris_bus_user",
2046 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
2047 21, 0, 0),
2048 };
2049
2050 static const struct samsung_cmu_info peris_cmu_info __initconst = {
2051 .mux_clks = peris_mux_clks,
2052 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
2053 .gate_clks = peris_gate_clks,
2054 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
2055 .nr_clk_ids = PERIS_NR_CLK,
2056 .clk_regs = peris_clk_regs,
2057 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
2058 .clk_name = "dout_clkcmu_peris_bus",
2059 };
2060
exynosautov9_cmu_probe(struct platform_device * pdev)2061 static int __init exynosautov9_cmu_probe(struct platform_device *pdev)
2062 {
2063 const struct samsung_cmu_info *info;
2064 struct device *dev = &pdev->dev;
2065
2066 info = of_device_get_match_data(dev);
2067 exynos_arm64_register_cmu(dev, dev->of_node, info);
2068
2069 return 0;
2070 }
2071
2072 static const struct of_device_id exynosautov9_cmu_of_match[] = {
2073 {
2074 .compatible = "samsung,exynosautov9-cmu-busmc",
2075 .data = &busmc_cmu_info,
2076 }, {
2077 .compatible = "samsung,exynosautov9-cmu-core",
2078 .data = &core_cmu_info,
2079 }, {
2080 .compatible = "samsung,exynosautov9-cmu-fsys0",
2081 .data = &fsys0_cmu_info,
2082 }, {
2083 .compatible = "samsung,exynosautov9-cmu-fsys1",
2084 .data = &fsys1_cmu_info,
2085 }, {
2086 .compatible = "samsung,exynosautov9-cmu-fsys2",
2087 .data = &fsys2_cmu_info,
2088 }, {
2089 .compatible = "samsung,exynosautov9-cmu-peric0",
2090 .data = &peric0_cmu_info,
2091 }, {
2092 .compatible = "samsung,exynosautov9-cmu-peric1",
2093 .data = &peric1_cmu_info,
2094 }, {
2095 .compatible = "samsung,exynosautov9-cmu-peris",
2096 .data = &peris_cmu_info,
2097 }, {
2098 },
2099 };
2100
2101 static struct platform_driver exynosautov9_cmu_driver __refdata = {
2102 .driver = {
2103 .name = "exynosautov9-cmu",
2104 .of_match_table = exynosautov9_cmu_of_match,
2105 .suppress_bind_attrs = true,
2106 },
2107 .probe = exynosautov9_cmu_probe,
2108 };
2109
exynosautov9_cmu_init(void)2110 static int __init exynosautov9_cmu_init(void)
2111 {
2112 return platform_driver_register(&exynosautov9_cmu_driver);
2113 }
2114 core_initcall(exynosautov9_cmu_init);
2115
