1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
8 #include <linux/err.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
16
17 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
18
19 #include "common.h"
20 #include "clk-regmap.h"
21 #include "clk-regmap-divider.h"
22 #include "clk-alpha-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
25 #include "reset.h"
26 #include "gdsc.h"
27
28 enum {
29 P_XO,
30 P_GPLL0,
31 P_GPLL0_DIV,
32 P_MMPLL0_OUT_EVEN,
33 P_MMPLL1_OUT_EVEN,
34 P_MMPLL3_OUT_EVEN,
35 P_MMPLL4_OUT_EVEN,
36 P_MMPLL5_OUT_EVEN,
37 P_MMPLL6_OUT_EVEN,
38 P_MMPLL7_OUT_EVEN,
39 P_MMPLL10_OUT_EVEN,
40 P_DSI0PLL,
41 P_DSI1PLL,
42 P_DSI0PLL_BYTE,
43 P_DSI1PLL_BYTE,
44 P_HDMIPLL,
45 P_DPVCO,
46 P_DPLINK,
47 P_CORE_BI_PLL_TEST_SE,
48 };
49
50 static struct clk_fixed_factor gpll0_div = {
51 .mult = 1,
52 .div = 2,
53 .hw.init = &(struct clk_init_data){
54 .name = "mmss_gpll0_div",
55 .parent_data = &(const struct clk_parent_data){
56 .fw_name = "gpll0"
57 },
58 .num_parents = 1,
59 .ops = &clk_fixed_factor_ops,
60 },
61 };
62
63 static const struct clk_div_table post_div_table_fabia_even[] = {
64 { 0x0, 1 },
65 { 0x1, 2 },
66 { 0x3, 4 },
67 { 0x7, 8 },
68 { }
69 };
70
71 static struct clk_alpha_pll mmpll0 = {
72 .offset = 0xc000,
73 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
74 .clkr = {
75 .enable_reg = 0x1e0,
76 .enable_mask = BIT(0),
77 .hw.init = &(struct clk_init_data){
78 .name = "mmpll0",
79 .parent_data = &(const struct clk_parent_data){
80 .fw_name = "xo"
81 },
82 .num_parents = 1,
83 .ops = &clk_alpha_pll_fixed_fabia_ops,
84 },
85 },
86 };
87
88 static struct clk_alpha_pll_postdiv mmpll0_out_even = {
89 .offset = 0xc000,
90 .post_div_shift = 8,
91 .post_div_table = post_div_table_fabia_even,
92 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
93 .width = 4,
94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
95 .clkr.hw.init = &(struct clk_init_data){
96 .name = "mmpll0_out_even",
97 .parent_hws = (const struct clk_hw *[]){ &mmpll0.clkr.hw },
98 .num_parents = 1,
99 .ops = &clk_alpha_pll_postdiv_fabia_ops,
100 },
101 };
102
103 static struct clk_alpha_pll mmpll1 = {
104 .offset = 0xc050,
105 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
106 .clkr = {
107 .enable_reg = 0x1e0,
108 .enable_mask = BIT(1),
109 .hw.init = &(struct clk_init_data){
110 .name = "mmpll1",
111 .parent_data = &(const struct clk_parent_data){
112 .fw_name = "xo"
113 },
114 .num_parents = 1,
115 .ops = &clk_alpha_pll_fixed_fabia_ops,
116 },
117 },
118 };
119
120 static struct clk_alpha_pll_postdiv mmpll1_out_even = {
121 .offset = 0xc050,
122 .post_div_shift = 8,
123 .post_div_table = post_div_table_fabia_even,
124 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
125 .width = 4,
126 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
127 .clkr.hw.init = &(struct clk_init_data){
128 .name = "mmpll1_out_even",
129 .parent_hws = (const struct clk_hw *[]){ &mmpll1.clkr.hw },
130 .num_parents = 1,
131 .ops = &clk_alpha_pll_postdiv_fabia_ops,
132 },
133 };
134
135 static struct clk_alpha_pll mmpll3 = {
136 .offset = 0x0,
137 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
138 .clkr.hw.init = &(struct clk_init_data){
139 .name = "mmpll3",
140 .parent_data = &(const struct clk_parent_data){
141 .fw_name = "xo"
142 },
143 .num_parents = 1,
144 .ops = &clk_alpha_pll_fixed_fabia_ops,
145 },
146 };
147
148 static struct clk_alpha_pll_postdiv mmpll3_out_even = {
149 .offset = 0x0,
150 .post_div_shift = 8,
151 .post_div_table = post_div_table_fabia_even,
152 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
153 .width = 4,
154 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
155 .clkr.hw.init = &(struct clk_init_data){
156 .name = "mmpll3_out_even",
157 .parent_hws = (const struct clk_hw *[]){ &mmpll3.clkr.hw },
158 .num_parents = 1,
159 .ops = &clk_alpha_pll_postdiv_fabia_ops,
160 },
161 };
162
163 static struct clk_alpha_pll mmpll4 = {
164 .offset = 0x50,
165 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
166 .clkr.hw.init = &(struct clk_init_data){
167 .name = "mmpll4",
168 .parent_data = &(const struct clk_parent_data){
169 .fw_name = "xo"
170 },
171 .num_parents = 1,
172 .ops = &clk_alpha_pll_fixed_fabia_ops,
173 },
174 };
175
176 static struct clk_alpha_pll_postdiv mmpll4_out_even = {
177 .offset = 0x50,
178 .post_div_shift = 8,
179 .post_div_table = post_div_table_fabia_even,
180 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
181 .width = 4,
182 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
183 .clkr.hw.init = &(struct clk_init_data){
184 .name = "mmpll4_out_even",
185 .parent_hws = (const struct clk_hw *[]){ &mmpll4.clkr.hw },
186 .num_parents = 1,
187 .ops = &clk_alpha_pll_postdiv_fabia_ops,
188 },
189 };
190
191 static struct clk_alpha_pll mmpll5 = {
192 .offset = 0xa0,
193 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
194 .clkr.hw.init = &(struct clk_init_data){
195 .name = "mmpll5",
196 .parent_data = &(const struct clk_parent_data){
197 .fw_name = "xo"
198 },
199 .num_parents = 1,
200 .ops = &clk_alpha_pll_fixed_fabia_ops,
201 },
202 };
203
204 static struct clk_alpha_pll_postdiv mmpll5_out_even = {
205 .offset = 0xa0,
206 .post_div_shift = 8,
207 .post_div_table = post_div_table_fabia_even,
208 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
209 .width = 4,
210 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
211 .clkr.hw.init = &(struct clk_init_data){
212 .name = "mmpll5_out_even",
213 .parent_hws = (const struct clk_hw *[]){ &mmpll5.clkr.hw },
214 .num_parents = 1,
215 .ops = &clk_alpha_pll_postdiv_fabia_ops,
216 },
217 };
218
219 static struct clk_alpha_pll mmpll6 = {
220 .offset = 0xf0,
221 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
222 .clkr.hw.init = &(struct clk_init_data){
223 .name = "mmpll6",
224 .parent_data = &(const struct clk_parent_data){
225 .fw_name = "xo"
226 },
227 .num_parents = 1,
228 .ops = &clk_alpha_pll_fixed_fabia_ops,
229 },
230 };
231
232 static struct clk_alpha_pll_postdiv mmpll6_out_even = {
233 .offset = 0xf0,
234 .post_div_shift = 8,
235 .post_div_table = post_div_table_fabia_even,
236 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
237 .width = 4,
238 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
239 .clkr.hw.init = &(struct clk_init_data){
240 .name = "mmpll6_out_even",
241 .parent_hws = (const struct clk_hw *[]){ &mmpll6.clkr.hw },
242 .num_parents = 1,
243 .ops = &clk_alpha_pll_postdiv_fabia_ops,
244 },
245 };
246
247 static struct clk_alpha_pll mmpll7 = {
248 .offset = 0x140,
249 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
250 .clkr.hw.init = &(struct clk_init_data){
251 .name = "mmpll7",
252 .parent_data = &(const struct clk_parent_data){
253 .fw_name = "xo"
254 },
255 .num_parents = 1,
256 .ops = &clk_alpha_pll_fixed_fabia_ops,
257 },
258 };
259
260 static struct clk_alpha_pll_postdiv mmpll7_out_even = {
261 .offset = 0x140,
262 .post_div_shift = 8,
263 .post_div_table = post_div_table_fabia_even,
264 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
265 .width = 4,
266 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
267 .clkr.hw.init = &(struct clk_init_data){
268 .name = "mmpll7_out_even",
269 .parent_hws = (const struct clk_hw *[]){ &mmpll7.clkr.hw },
270 .num_parents = 1,
271 .ops = &clk_alpha_pll_postdiv_fabia_ops,
272 },
273 };
274
275 static struct clk_alpha_pll mmpll10 = {
276 .offset = 0x190,
277 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
278 .clkr.hw.init = &(struct clk_init_data){
279 .name = "mmpll10",
280 .parent_data = &(const struct clk_parent_data){
281 .fw_name = "xo"
282 },
283 .num_parents = 1,
284 .ops = &clk_alpha_pll_fixed_fabia_ops,
285 },
286 };
287
288 static struct clk_alpha_pll_postdiv mmpll10_out_even = {
289 .offset = 0x190,
290 .post_div_shift = 8,
291 .post_div_table = post_div_table_fabia_even,
292 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
293 .width = 4,
294 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
295 .clkr.hw.init = &(struct clk_init_data){
296 .name = "mmpll10_out_even",
297 .parent_hws = (const struct clk_hw *[]){ &mmpll10.clkr.hw },
298 .num_parents = 1,
299 .ops = &clk_alpha_pll_postdiv_fabia_ops,
300 },
301 };
302
303 static const struct parent_map mmss_xo_hdmi_map[] = {
304 { P_XO, 0 },
305 { P_HDMIPLL, 1 },
306 { P_CORE_BI_PLL_TEST_SE, 7 }
307 };
308
309 static const struct clk_parent_data mmss_xo_hdmi[] = {
310 { .fw_name = "xo" },
311 { .fw_name = "hdmipll" },
312 { .fw_name = "core_bi_pll_test_se" },
313 };
314
315 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
316 { P_XO, 0 },
317 { P_DSI0PLL, 1 },
318 { P_DSI1PLL, 2 },
319 { P_CORE_BI_PLL_TEST_SE, 7 }
320 };
321
322 static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = {
323 { .fw_name = "xo" },
324 { .fw_name = "dsi0dsi" },
325 { .fw_name = "dsi1dsi" },
326 { .fw_name = "core_bi_pll_test_se" },
327 };
328
329 static const struct parent_map mmss_xo_dsibyte_map[] = {
330 { P_XO, 0 },
331 { P_DSI0PLL_BYTE, 1 },
332 { P_DSI1PLL_BYTE, 2 },
333 { P_CORE_BI_PLL_TEST_SE, 7 }
334 };
335
336 static const struct clk_parent_data mmss_xo_dsibyte[] = {
337 { .fw_name = "xo" },
338 { .fw_name = "dsi0byte" },
339 { .fw_name = "dsi1byte" },
340 { .fw_name = "core_bi_pll_test_se" },
341 };
342
343 static const struct parent_map mmss_xo_dp_map[] = {
344 { P_XO, 0 },
345 { P_DPLINK, 1 },
346 { P_DPVCO, 2 },
347 { P_CORE_BI_PLL_TEST_SE, 7 }
348 };
349
350 static const struct clk_parent_data mmss_xo_dp[] = {
351 { .fw_name = "xo" },
352 { .fw_name = "dplink" },
353 { .fw_name = "dpvco" },
354 { .fw_name = "core_bi_pll_test_se" },
355 };
356
357 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
358 { P_XO, 0 },
359 { P_GPLL0, 5 },
360 { P_GPLL0_DIV, 6 },
361 { P_CORE_BI_PLL_TEST_SE, 7 }
362 };
363
364 static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
365 { .fw_name = "xo" },
366 { .fw_name = "gpll0" },
367 { .hw = &gpll0_div.hw },
368 { .fw_name = "core_bi_pll_test_se" },
369 };
370
371 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
372 { P_XO, 0 },
373 { P_MMPLL0_OUT_EVEN, 1 },
374 { P_GPLL0, 5 },
375 { P_GPLL0_DIV, 6 },
376 { P_CORE_BI_PLL_TEST_SE, 7 }
377 };
378
379 static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
380 { .fw_name = "xo" },
381 { .hw = &mmpll0_out_even.clkr.hw },
382 { .fw_name = "gpll0" },
383 { .hw = &gpll0_div.hw },
384 { .fw_name = "core_bi_pll_test_se" },
385 };
386
387 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
388 { P_XO, 0 },
389 { P_MMPLL0_OUT_EVEN, 1 },
390 { P_MMPLL1_OUT_EVEN, 2 },
391 { P_GPLL0, 5 },
392 { P_GPLL0_DIV, 6 },
393 { P_CORE_BI_PLL_TEST_SE, 7 }
394 };
395
396 static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
397 { .fw_name = "xo" },
398 { .hw = &mmpll0_out_even.clkr.hw },
399 { .hw = &mmpll1_out_even.clkr.hw },
400 { .fw_name = "gpll0" },
401 { .hw = &gpll0_div.hw },
402 { .fw_name = "core_bi_pll_test_se" },
403 };
404
405 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
406 { P_XO, 0 },
407 { P_MMPLL0_OUT_EVEN, 1 },
408 { P_MMPLL5_OUT_EVEN, 2 },
409 { P_GPLL0, 5 },
410 { P_GPLL0_DIV, 6 },
411 { P_CORE_BI_PLL_TEST_SE, 7 }
412 };
413
414 static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
415 { .fw_name = "xo" },
416 { .hw = &mmpll0_out_even.clkr.hw },
417 { .hw = &mmpll5_out_even.clkr.hw },
418 { .fw_name = "gpll0" },
419 { .hw = &gpll0_div.hw },
420 { .fw_name = "core_bi_pll_test_se" },
421 };
422
423 static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = {
424 { P_XO, 0 },
425 { P_MMPLL0_OUT_EVEN, 1 },
426 { P_MMPLL3_OUT_EVEN, 3 },
427 { P_MMPLL6_OUT_EVEN, 4 },
428 { P_GPLL0, 5 },
429 { P_GPLL0_DIV, 6 },
430 { P_CORE_BI_PLL_TEST_SE, 7 }
431 };
432
433 static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div[] = {
434 { .fw_name = "xo" },
435 { .hw = &mmpll0_out_even.clkr.hw },
436 { .hw = &mmpll3_out_even.clkr.hw },
437 { .hw = &mmpll6_out_even.clkr.hw },
438 { .fw_name = "gpll0" },
439 { .hw = &gpll0_div.hw },
440 { .fw_name = "core_bi_pll_test_se" },
441 };
442
443 static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
444 { P_XO, 0 },
445 { P_MMPLL4_OUT_EVEN, 1 },
446 { P_MMPLL7_OUT_EVEN, 2 },
447 { P_MMPLL10_OUT_EVEN, 3 },
448 { P_GPLL0, 5 },
449 { P_GPLL0_DIV, 6 },
450 { P_CORE_BI_PLL_TEST_SE, 7 }
451 };
452
453 static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
454 { .fw_name = "xo" },
455 { .hw = &mmpll4_out_even.clkr.hw },
456 { .hw = &mmpll7_out_even.clkr.hw },
457 { .hw = &mmpll10_out_even.clkr.hw },
458 { .fw_name = "gpll0" },
459 { .hw = &gpll0_div.hw },
460 { .fw_name = "core_bi_pll_test_se" },
461 };
462
463 static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
464 { P_XO, 0 },
465 { P_MMPLL0_OUT_EVEN, 1 },
466 { P_MMPLL7_OUT_EVEN, 2 },
467 { P_MMPLL10_OUT_EVEN, 3 },
468 { P_GPLL0, 5 },
469 { P_GPLL0_DIV, 6 },
470 { P_CORE_BI_PLL_TEST_SE, 7 }
471 };
472
473 static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div[] = {
474 { .fw_name = "xo" },
475 { .hw = &mmpll0_out_even.clkr.hw },
476 { .hw = &mmpll7_out_even.clkr.hw },
477 { .hw = &mmpll10_out_even.clkr.hw },
478 { .fw_name = "gpll0" },
479 { .hw = &gpll0_div.hw },
480 { .fw_name = "core_bi_pll_test_se" },
481 };
482
483 static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
484 { P_XO, 0 },
485 { P_MMPLL0_OUT_EVEN, 1 },
486 { P_MMPLL4_OUT_EVEN, 2 },
487 { P_MMPLL7_OUT_EVEN, 3 },
488 { P_MMPLL10_OUT_EVEN, 4 },
489 { P_GPLL0, 5 },
490 { P_GPLL0_DIV, 6 },
491 { P_CORE_BI_PLL_TEST_SE, 7 }
492 };
493
494 static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
495 { .fw_name = "xo" },
496 { .hw = &mmpll0_out_even.clkr.hw },
497 { .hw = &mmpll4_out_even.clkr.hw },
498 { .hw = &mmpll7_out_even.clkr.hw },
499 { .hw = &mmpll10_out_even.clkr.hw },
500 { .fw_name = "gpll0" },
501 { .hw = &gpll0_div.hw },
502 { .fw_name = "core_bi_pll_test_se" },
503 };
504
505 static struct clk_rcg2 byte0_clk_src = {
506 .cmd_rcgr = 0x2120,
507 .hid_width = 5,
508 .parent_map = mmss_xo_dsibyte_map,
509 .clkr.hw.init = &(struct clk_init_data){
510 .name = "byte0_clk_src",
511 .parent_data = mmss_xo_dsibyte,
512 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
513 .ops = &clk_byte2_ops,
514 .flags = CLK_SET_RATE_PARENT,
515 },
516 };
517
518 static struct clk_rcg2 byte1_clk_src = {
519 .cmd_rcgr = 0x2140,
520 .hid_width = 5,
521 .parent_map = mmss_xo_dsibyte_map,
522 .clkr.hw.init = &(struct clk_init_data){
523 .name = "byte1_clk_src",
524 .parent_data = mmss_xo_dsibyte,
525 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
526 .ops = &clk_byte2_ops,
527 .flags = CLK_SET_RATE_PARENT,
528 },
529 };
530
531 static const struct freq_tbl ftbl_cci_clk_src[] = {
532 F(37500000, P_GPLL0, 16, 0, 0),
533 F(50000000, P_GPLL0, 12, 0, 0),
534 F(100000000, P_GPLL0, 6, 0, 0),
535 { }
536 };
537
538 static struct clk_rcg2 cci_clk_src = {
539 .cmd_rcgr = 0x3300,
540 .hid_width = 5,
541 .parent_map = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map,
542 .freq_tbl = ftbl_cci_clk_src,
543 .clkr.hw.init = &(struct clk_init_data){
544 .name = "cci_clk_src",
545 .parent_data = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div,
546 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div),
547 .ops = &clk_rcg2_ops,
548 },
549 };
550
551 static const struct freq_tbl ftbl_cpp_clk_src[] = {
552 F(100000000, P_GPLL0, 6, 0, 0),
553 F(200000000, P_GPLL0, 3, 0, 0),
554 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
555 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
556 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
557 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
558 F(600000000, P_GPLL0, 1, 0, 0),
559 { }
560 };
561
562 static struct clk_rcg2 cpp_clk_src = {
563 .cmd_rcgr = 0x3640,
564 .hid_width = 5,
565 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
566 .freq_tbl = ftbl_cpp_clk_src,
567 .clkr.hw.init = &(struct clk_init_data){
568 .name = "cpp_clk_src",
569 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
570 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
571 .ops = &clk_rcg2_ops,
572 },
573 };
574
575 static const struct freq_tbl ftbl_csi_clk_src[] = {
576 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
577 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
578 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
579 F(300000000, P_GPLL0, 2, 0, 0),
580 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
581 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
582 { }
583 };
584
585 static struct clk_rcg2 csi0_clk_src = {
586 .cmd_rcgr = 0x3090,
587 .hid_width = 5,
588 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
589 .freq_tbl = ftbl_csi_clk_src,
590 .clkr.hw.init = &(struct clk_init_data){
591 .name = "csi0_clk_src",
592 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
593 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
594 .ops = &clk_rcg2_ops,
595 },
596 };
597
598 static struct clk_rcg2 csi1_clk_src = {
599 .cmd_rcgr = 0x3100,
600 .hid_width = 5,
601 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
602 .freq_tbl = ftbl_csi_clk_src,
603 .clkr.hw.init = &(struct clk_init_data){
604 .name = "csi1_clk_src",
605 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
606 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
607 .ops = &clk_rcg2_ops,
608 },
609 };
610
611 static struct clk_rcg2 csi2_clk_src = {
612 .cmd_rcgr = 0x3160,
613 .hid_width = 5,
614 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
615 .freq_tbl = ftbl_csi_clk_src,
616 .clkr.hw.init = &(struct clk_init_data){
617 .name = "csi2_clk_src",
618 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
619 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
620 .ops = &clk_rcg2_ops,
621 },
622 };
623
624 static struct clk_rcg2 csi3_clk_src = {
625 .cmd_rcgr = 0x31c0,
626 .hid_width = 5,
627 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
628 .freq_tbl = ftbl_csi_clk_src,
629 .clkr.hw.init = &(struct clk_init_data){
630 .name = "csi3_clk_src",
631 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
632 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
633 .ops = &clk_rcg2_ops,
634 },
635 };
636
637 static const struct freq_tbl ftbl_csiphy_clk_src[] = {
638 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
639 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
640 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
641 F(300000000, P_GPLL0, 2, 0, 0),
642 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
643 { }
644 };
645
646 static struct clk_rcg2 csiphy_clk_src = {
647 .cmd_rcgr = 0x3800,
648 .hid_width = 5,
649 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
650 .freq_tbl = ftbl_csiphy_clk_src,
651 .clkr.hw.init = &(struct clk_init_data){
652 .name = "csiphy_clk_src",
653 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
654 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
655 .ops = &clk_rcg2_ops,
656 },
657 };
658
659 static const struct freq_tbl ftbl_csiphytimer_clk_src[] = {
660 F(200000000, P_GPLL0, 3, 0, 0),
661 F(269333333, P_MMPLL0_OUT_EVEN, 3, 0, 0),
662 { }
663 };
664
665 static struct clk_rcg2 csi0phytimer_clk_src = {
666 .cmd_rcgr = 0x3000,
667 .hid_width = 5,
668 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
669 .freq_tbl = ftbl_csiphytimer_clk_src,
670 .clkr.hw.init = &(struct clk_init_data){
671 .name = "csi0phytimer_clk_src",
672 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
673 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
674 .ops = &clk_rcg2_ops,
675 },
676 };
677
678 static struct clk_rcg2 csi1phytimer_clk_src = {
679 .cmd_rcgr = 0x3030,
680 .hid_width = 5,
681 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
682 .freq_tbl = ftbl_csiphytimer_clk_src,
683 .clkr.hw.init = &(struct clk_init_data){
684 .name = "csi1phytimer_clk_src",
685 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
686 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
687 .ops = &clk_rcg2_ops,
688 },
689 };
690
691 static struct clk_rcg2 csi2phytimer_clk_src = {
692 .cmd_rcgr = 0x3060,
693 .hid_width = 5,
694 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
695 .freq_tbl = ftbl_csiphytimer_clk_src,
696 .clkr.hw.init = &(struct clk_init_data){
697 .name = "csi2phytimer_clk_src",
698 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
699 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
700 .ops = &clk_rcg2_ops,
701 },
702 };
703
704 static const struct freq_tbl ftbl_dp_aux_clk_src[] = {
705 F(19200000, P_XO, 1, 0, 0),
706 { }
707 };
708
709 static struct clk_rcg2 dp_aux_clk_src = {
710 .cmd_rcgr = 0x2260,
711 .hid_width = 5,
712 .parent_map = mmss_xo_gpll0_gpll0_div_map,
713 .freq_tbl = ftbl_dp_aux_clk_src,
714 .clkr.hw.init = &(struct clk_init_data){
715 .name = "dp_aux_clk_src",
716 .parent_data = mmss_xo_gpll0_gpll0_div,
717 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
718 .ops = &clk_rcg2_ops,
719 },
720 };
721
722 static const struct freq_tbl ftbl_dp_crypto_clk_src[] = {
723 F(101250, P_DPLINK, 1, 5, 16),
724 F(168750, P_DPLINK, 1, 5, 16),
725 F(337500, P_DPLINK, 1, 5, 16),
726 { }
727 };
728
729 static struct clk_rcg2 dp_crypto_clk_src = {
730 .cmd_rcgr = 0x2220,
731 .hid_width = 5,
732 .parent_map = mmss_xo_dp_map,
733 .freq_tbl = ftbl_dp_crypto_clk_src,
734 .clkr.hw.init = &(struct clk_init_data){
735 .name = "dp_crypto_clk_src",
736 .parent_data = mmss_xo_dp,
737 .num_parents = ARRAY_SIZE(mmss_xo_dp),
738 .ops = &clk_rcg2_ops,
739 },
740 };
741
742 static const struct freq_tbl ftbl_dp_link_clk_src[] = {
743 F(162000, P_DPLINK, 2, 0, 0),
744 F(270000, P_DPLINK, 2, 0, 0),
745 F(540000, P_DPLINK, 2, 0, 0),
746 { }
747 };
748
749 static struct clk_rcg2 dp_link_clk_src = {
750 .cmd_rcgr = 0x2200,
751 .hid_width = 5,
752 .parent_map = mmss_xo_dp_map,
753 .freq_tbl = ftbl_dp_link_clk_src,
754 .clkr.hw.init = &(struct clk_init_data){
755 .name = "dp_link_clk_src",
756 .parent_data = mmss_xo_dp,
757 .num_parents = ARRAY_SIZE(mmss_xo_dp),
758 .ops = &clk_rcg2_ops,
759 },
760 };
761
762 static const struct freq_tbl ftbl_dp_pixel_clk_src[] = {
763 F(154000000, P_DPVCO, 1, 0, 0),
764 F(337500000, P_DPVCO, 2, 0, 0),
765 F(675000000, P_DPVCO, 2, 0, 0),
766 { }
767 };
768
769 static struct clk_rcg2 dp_pixel_clk_src = {
770 .cmd_rcgr = 0x2240,
771 .hid_width = 5,
772 .parent_map = mmss_xo_dp_map,
773 .freq_tbl = ftbl_dp_pixel_clk_src,
774 .clkr.hw.init = &(struct clk_init_data){
775 .name = "dp_pixel_clk_src",
776 .parent_data = mmss_xo_dp,
777 .num_parents = ARRAY_SIZE(mmss_xo_dp),
778 .ops = &clk_rcg2_ops,
779 },
780 };
781
782 static const struct freq_tbl ftbl_esc_clk_src[] = {
783 F(19200000, P_XO, 1, 0, 0),
784 { }
785 };
786
787 static struct clk_rcg2 esc0_clk_src = {
788 .cmd_rcgr = 0x2160,
789 .hid_width = 5,
790 .parent_map = mmss_xo_dsibyte_map,
791 .freq_tbl = ftbl_esc_clk_src,
792 .clkr.hw.init = &(struct clk_init_data){
793 .name = "esc0_clk_src",
794 .parent_data = mmss_xo_dsibyte,
795 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
796 .ops = &clk_rcg2_ops,
797 },
798 };
799
800 static struct clk_rcg2 esc1_clk_src = {
801 .cmd_rcgr = 0x2180,
802 .hid_width = 5,
803 .parent_map = mmss_xo_dsibyte_map,
804 .freq_tbl = ftbl_esc_clk_src,
805 .clkr.hw.init = &(struct clk_init_data){
806 .name = "esc1_clk_src",
807 .parent_data = mmss_xo_dsibyte,
808 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
809 .ops = &clk_rcg2_ops,
810 },
811 };
812
813 static const struct freq_tbl ftbl_extpclk_clk_src[] = {
814 { .src = P_HDMIPLL },
815 { }
816 };
817
818 static struct clk_rcg2 extpclk_clk_src = {
819 .cmd_rcgr = 0x2060,
820 .hid_width = 5,
821 .parent_map = mmss_xo_hdmi_map,
822 .freq_tbl = ftbl_extpclk_clk_src,
823 .clkr.hw.init = &(struct clk_init_data){
824 .name = "extpclk_clk_src",
825 .parent_data = mmss_xo_hdmi,
826 .num_parents = ARRAY_SIZE(mmss_xo_hdmi),
827 .ops = &clk_byte_ops,
828 .flags = CLK_SET_RATE_PARENT,
829 },
830 };
831
832 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
833 F(100000000, P_GPLL0, 6, 0, 0),
834 F(200000000, P_GPLL0, 3, 0, 0),
835 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
836 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
837 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
838 { }
839 };
840
841 static struct clk_rcg2 fd_core_clk_src = {
842 .cmd_rcgr = 0x3b00,
843 .hid_width = 5,
844 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
845 .freq_tbl = ftbl_fd_core_clk_src,
846 .clkr.hw.init = &(struct clk_init_data){
847 .name = "fd_core_clk_src",
848 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
849 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
850 .ops = &clk_rcg2_ops,
851 },
852 };
853
854 static const struct freq_tbl ftbl_hdmi_clk_src[] = {
855 F(19200000, P_XO, 1, 0, 0),
856 { }
857 };
858
859 static struct clk_rcg2 hdmi_clk_src = {
860 .cmd_rcgr = 0x2100,
861 .hid_width = 5,
862 .parent_map = mmss_xo_gpll0_gpll0_div_map,
863 .freq_tbl = ftbl_hdmi_clk_src,
864 .clkr.hw.init = &(struct clk_init_data){
865 .name = "hdmi_clk_src",
866 .parent_data = mmss_xo_gpll0_gpll0_div,
867 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
868 .ops = &clk_rcg2_ops,
869 },
870 };
871
872 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
873 F(75000000, P_GPLL0, 8, 0, 0),
874 F(150000000, P_GPLL0, 4, 0, 0),
875 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
876 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
877 { }
878 };
879
880 static struct clk_rcg2 jpeg0_clk_src = {
881 .cmd_rcgr = 0x3500,
882 .hid_width = 5,
883 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
884 .freq_tbl = ftbl_jpeg0_clk_src,
885 .clkr.hw.init = &(struct clk_init_data){
886 .name = "jpeg0_clk_src",
887 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
888 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
889 .ops = &clk_rcg2_ops,
890 },
891 };
892
893 static const struct freq_tbl ftbl_maxi_clk_src[] = {
894 F(19200000, P_XO, 1, 0, 0),
895 F(75000000, P_GPLL0_DIV, 4, 0, 0),
896 F(171428571, P_GPLL0, 3.5, 0, 0),
897 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
898 F(406000000, P_MMPLL1_OUT_EVEN, 2, 0, 0),
899 { }
900 };
901
902 static struct clk_rcg2 maxi_clk_src = {
903 .cmd_rcgr = 0xf020,
904 .hid_width = 5,
905 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
906 .freq_tbl = ftbl_maxi_clk_src,
907 .clkr.hw.init = &(struct clk_init_data){
908 .name = "maxi_clk_src",
909 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
910 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
911 .ops = &clk_rcg2_ops,
912 },
913 };
914
915 static const struct freq_tbl ftbl_mclk_clk_src[] = {
916 F(4800000, P_XO, 4, 0, 0),
917 F(6000000, P_GPLL0_DIV, 10, 1, 5),
918 F(8000000, P_GPLL0_DIV, 1, 2, 75),
919 F(9600000, P_XO, 2, 0, 0),
920 F(16666667, P_GPLL0_DIV, 2, 1, 9),
921 F(19200000, P_XO, 1, 0, 0),
922 F(24000000, P_GPLL0_DIV, 1, 2, 25),
923 F(33333333, P_GPLL0_DIV, 1, 2, 9),
924 F(48000000, P_GPLL0, 1, 2, 25),
925 F(66666667, P_GPLL0, 1, 2, 9),
926 { }
927 };
928
929 static struct clk_rcg2 mclk0_clk_src = {
930 .cmd_rcgr = 0x3360,
931 .hid_width = 5,
932 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
933 .freq_tbl = ftbl_mclk_clk_src,
934 .clkr.hw.init = &(struct clk_init_data){
935 .name = "mclk0_clk_src",
936 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
937 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
938 .ops = &clk_rcg2_ops,
939 },
940 };
941
942 static struct clk_rcg2 mclk1_clk_src = {
943 .cmd_rcgr = 0x3390,
944 .hid_width = 5,
945 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
946 .freq_tbl = ftbl_mclk_clk_src,
947 .clkr.hw.init = &(struct clk_init_data){
948 .name = "mclk1_clk_src",
949 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
950 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
951 .ops = &clk_rcg2_ops,
952 },
953 };
954
955 static struct clk_rcg2 mclk2_clk_src = {
956 .cmd_rcgr = 0x33c0,
957 .hid_width = 5,
958 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
959 .freq_tbl = ftbl_mclk_clk_src,
960 .clkr.hw.init = &(struct clk_init_data){
961 .name = "mclk2_clk_src",
962 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
963 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
964 .ops = &clk_rcg2_ops,
965 },
966 };
967
968 static struct clk_rcg2 mclk3_clk_src = {
969 .cmd_rcgr = 0x33f0,
970 .hid_width = 5,
971 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
972 .freq_tbl = ftbl_mclk_clk_src,
973 .clkr.hw.init = &(struct clk_init_data){
974 .name = "mclk3_clk_src",
975 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
976 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
977 .ops = &clk_rcg2_ops,
978 },
979 };
980
981 static const struct freq_tbl ftbl_mdp_clk_src[] = {
982 F(85714286, P_GPLL0, 7, 0, 0),
983 F(100000000, P_GPLL0, 6, 0, 0),
984 F(150000000, P_GPLL0, 4, 0, 0),
985 F(171428571, P_GPLL0, 3.5, 0, 0),
986 F(200000000, P_GPLL0, 3, 0, 0),
987 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
988 F(300000000, P_GPLL0, 2, 0, 0),
989 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
990 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
991 { }
992 };
993
994 static struct clk_rcg2 mdp_clk_src = {
995 .cmd_rcgr = 0x2040,
996 .hid_width = 5,
997 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
998 .freq_tbl = ftbl_mdp_clk_src,
999 .clkr.hw.init = &(struct clk_init_data){
1000 .name = "mdp_clk_src",
1001 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
1002 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
1003 .ops = &clk_rcg2_ops,
1004 },
1005 };
1006
1007 static const struct freq_tbl ftbl_vsync_clk_src[] = {
1008 F(19200000, P_XO, 1, 0, 0),
1009 { }
1010 };
1011
1012 static struct clk_rcg2 vsync_clk_src = {
1013 .cmd_rcgr = 0x2080,
1014 .hid_width = 5,
1015 .parent_map = mmss_xo_gpll0_gpll0_div_map,
1016 .freq_tbl = ftbl_vsync_clk_src,
1017 .clkr.hw.init = &(struct clk_init_data){
1018 .name = "vsync_clk_src",
1019 .parent_data = mmss_xo_gpll0_gpll0_div,
1020 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
1021 .ops = &clk_rcg2_ops,
1022 },
1023 };
1024
1025 static const struct freq_tbl ftbl_ahb_clk_src[] = {
1026 F(19200000, P_XO, 1, 0, 0),
1027 F(40000000, P_GPLL0, 15, 0, 0),
1028 F(80800000, P_MMPLL0_OUT_EVEN, 10, 0, 0),
1029 { }
1030 };
1031
1032 static struct clk_rcg2 ahb_clk_src = {
1033 .cmd_rcgr = 0x5000,
1034 .hid_width = 5,
1035 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
1036 .freq_tbl = ftbl_ahb_clk_src,
1037 .clkr.hw.init = &(struct clk_init_data){
1038 .name = "ahb_clk_src",
1039 .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
1040 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
1041 .ops = &clk_rcg2_ops,
1042 },
1043 };
1044
1045 static const struct freq_tbl ftbl_axi_clk_src[] = {
1046 F(75000000, P_GPLL0, 8, 0, 0),
1047 F(171428571, P_GPLL0, 3.5, 0, 0),
1048 F(240000000, P_GPLL0, 2.5, 0, 0),
1049 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
1050 F(406000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1051 { }
1052 };
1053
1054 /* RO to linux */
1055 static struct clk_rcg2 axi_clk_src = {
1056 .cmd_rcgr = 0xd000,
1057 .hid_width = 5,
1058 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
1059 .freq_tbl = ftbl_axi_clk_src,
1060 .clkr.hw.init = &(struct clk_init_data){
1061 .name = "axi_clk_src",
1062 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
1063 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
1064 .ops = &clk_rcg2_ops,
1065 },
1066 };
1067
1068 static struct clk_rcg2 pclk0_clk_src = {
1069 .cmd_rcgr = 0x2000,
1070 .mnd_width = 8,
1071 .hid_width = 5,
1072 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
1073 .clkr.hw.init = &(struct clk_init_data){
1074 .name = "pclk0_clk_src",
1075 .parent_data = mmss_xo_dsi0pll_dsi1pll,
1076 .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
1077 .ops = &clk_pixel_ops,
1078 .flags = CLK_SET_RATE_PARENT,
1079 },
1080 };
1081
1082 static struct clk_rcg2 pclk1_clk_src = {
1083 .cmd_rcgr = 0x2020,
1084 .mnd_width = 8,
1085 .hid_width = 5,
1086 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
1087 .clkr.hw.init = &(struct clk_init_data){
1088 .name = "pclk1_clk_src",
1089 .parent_data = mmss_xo_dsi0pll_dsi1pll,
1090 .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
1091 .ops = &clk_pixel_ops,
1092 .flags = CLK_SET_RATE_PARENT,
1093 },
1094 };
1095
1096 static const struct freq_tbl ftbl_rot_clk_src[] = {
1097 F(171428571, P_GPLL0, 3.5, 0, 0),
1098 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
1099 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
1100 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1101 { }
1102 };
1103
1104 static struct clk_rcg2 rot_clk_src = {
1105 .cmd_rcgr = 0x21a0,
1106 .hid_width = 5,
1107 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
1108 .freq_tbl = ftbl_rot_clk_src,
1109 .clkr.hw.init = &(struct clk_init_data){
1110 .name = "rot_clk_src",
1111 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
1112 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
1113 .ops = &clk_rcg2_ops,
1114 },
1115 };
1116
1117 static const struct freq_tbl ftbl_video_core_clk_src[] = {
1118 F(200000000, P_GPLL0, 3, 0, 0),
1119 F(269330000, P_MMPLL0_OUT_EVEN, 3, 0, 0),
1120 F(355200000, P_MMPLL6_OUT_EVEN, 2.5, 0, 0),
1121 F(444000000, P_MMPLL6_OUT_EVEN, 2, 0, 0),
1122 F(533000000, P_MMPLL3_OUT_EVEN, 2, 0, 0),
1123 { }
1124 };
1125
1126 static struct clk_rcg2 video_core_clk_src = {
1127 .cmd_rcgr = 0x1000,
1128 .hid_width = 5,
1129 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1130 .freq_tbl = ftbl_video_core_clk_src,
1131 .clkr.hw.init = &(struct clk_init_data){
1132 .name = "video_core_clk_src",
1133 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1134 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
1135 .ops = &clk_rcg2_ops,
1136 },
1137 };
1138
1139 static struct clk_rcg2 video_subcore0_clk_src = {
1140 .cmd_rcgr = 0x1060,
1141 .hid_width = 5,
1142 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1143 .freq_tbl = ftbl_video_core_clk_src,
1144 .clkr.hw.init = &(struct clk_init_data){
1145 .name = "video_subcore0_clk_src",
1146 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1147 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
1148 .ops = &clk_rcg2_ops,
1149 },
1150 };
1151
1152 static struct clk_rcg2 video_subcore1_clk_src = {
1153 .cmd_rcgr = 0x1080,
1154 .hid_width = 5,
1155 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1156 .freq_tbl = ftbl_video_core_clk_src,
1157 .clkr.hw.init = &(struct clk_init_data){
1158 .name = "video_subcore1_clk_src",
1159 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1160 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
1161 .ops = &clk_rcg2_ops,
1162 },
1163 };
1164
1165 static const struct freq_tbl ftbl_vfe_clk_src[] = {
1166 F(200000000, P_GPLL0, 3, 0, 0),
1167 F(300000000, P_GPLL0, 2, 0, 0),
1168 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
1169 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
1170 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1171 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
1172 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
1173 F(600000000, P_GPLL0, 1, 0, 0),
1174 { }
1175 };
1176
1177 static struct clk_rcg2 vfe0_clk_src = {
1178 .cmd_rcgr = 0x3600,
1179 .hid_width = 5,
1180 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
1181 .freq_tbl = ftbl_vfe_clk_src,
1182 .clkr.hw.init = &(struct clk_init_data){
1183 .name = "vfe0_clk_src",
1184 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
1185 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
1186 .ops = &clk_rcg2_ops,
1187 },
1188 };
1189
1190 static struct clk_rcg2 vfe1_clk_src = {
1191 .cmd_rcgr = 0x3620,
1192 .hid_width = 5,
1193 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
1194 .freq_tbl = ftbl_vfe_clk_src,
1195 .clkr.hw.init = &(struct clk_init_data){
1196 .name = "vfe1_clk_src",
1197 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
1198 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
1199 .ops = &clk_rcg2_ops,
1200 },
1201 };
1202
1203 static struct clk_branch misc_ahb_clk = {
1204 .halt_reg = 0x328,
1205 .hwcg_reg = 0x328,
1206 .hwcg_bit = 1,
1207 .clkr = {
1208 .enable_reg = 0x328,
1209 .enable_mask = BIT(0),
1210 .hw.init = &(struct clk_init_data){
1211 .name = "misc_ahb_clk",
1212 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1213 .num_parents = 1,
1214 .ops = &clk_branch2_ops,
1215 .flags = CLK_SET_RATE_PARENT,
1216 },
1217 },
1218 };
1219
1220 static struct clk_branch video_core_clk = {
1221 .halt_reg = 0x1028,
1222 .clkr = {
1223 .enable_reg = 0x1028,
1224 .enable_mask = BIT(0),
1225 .hw.init = &(struct clk_init_data){
1226 .name = "video_core_clk",
1227 .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
1228 .num_parents = 1,
1229 .ops = &clk_branch2_ops,
1230 .flags = CLK_SET_RATE_PARENT,
1231 },
1232 },
1233 };
1234
1235 static struct clk_branch video_ahb_clk = {
1236 .halt_reg = 0x1030,
1237 .hwcg_reg = 0x1030,
1238 .hwcg_bit = 1,
1239 .clkr = {
1240 .enable_reg = 0x1030,
1241 .enable_mask = BIT(0),
1242 .hw.init = &(struct clk_init_data){
1243 .name = "video_ahb_clk",
1244 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1245 .num_parents = 1,
1246 .ops = &clk_branch2_ops,
1247 .flags = CLK_SET_RATE_PARENT,
1248 },
1249 },
1250 };
1251
1252 static struct clk_branch video_axi_clk = {
1253 .halt_reg = 0x1034,
1254 .clkr = {
1255 .enable_reg = 0x1034,
1256 .enable_mask = BIT(0),
1257 .hw.init = &(struct clk_init_data){
1258 .name = "video_axi_clk",
1259 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1260 .num_parents = 1,
1261 .ops = &clk_branch2_ops,
1262 },
1263 },
1264 };
1265
1266 static struct clk_branch video_maxi_clk = {
1267 .halt_reg = 0x1038,
1268 .clkr = {
1269 .enable_reg = 0x1038,
1270 .enable_mask = BIT(0),
1271 .hw.init = &(struct clk_init_data){
1272 .name = "video_maxi_clk",
1273 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
1274 .num_parents = 1,
1275 .ops = &clk_branch2_ops,
1276 .flags = CLK_SET_RATE_PARENT,
1277 },
1278 },
1279 };
1280
1281 static struct clk_branch video_subcore0_clk = {
1282 .halt_reg = 0x1048,
1283 .clkr = {
1284 .enable_reg = 0x1048,
1285 .enable_mask = BIT(0),
1286 .hw.init = &(struct clk_init_data){
1287 .name = "video_subcore0_clk",
1288 .parent_hws = (const struct clk_hw *[]){ &video_subcore0_clk_src.clkr.hw },
1289 .num_parents = 1,
1290 .ops = &clk_branch2_ops,
1291 .flags = CLK_SET_RATE_PARENT,
1292 },
1293 },
1294 };
1295
1296 static struct clk_branch video_subcore1_clk = {
1297 .halt_reg = 0x104c,
1298 .clkr = {
1299 .enable_reg = 0x104c,
1300 .enable_mask = BIT(0),
1301 .hw.init = &(struct clk_init_data){
1302 .name = "video_subcore1_clk",
1303 .parent_hws = (const struct clk_hw *[]){ &video_subcore1_clk_src.clkr.hw },
1304 .num_parents = 1,
1305 .ops = &clk_branch2_ops,
1306 .flags = CLK_SET_RATE_PARENT,
1307 },
1308 },
1309 };
1310
1311 static struct clk_branch mdss_ahb_clk = {
1312 .halt_reg = 0x2308,
1313 .hwcg_reg = 0x2308,
1314 .hwcg_bit = 1,
1315 .clkr = {
1316 .enable_reg = 0x2308,
1317 .enable_mask = BIT(0),
1318 .hw.init = &(struct clk_init_data){
1319 .name = "mdss_ahb_clk",
1320 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1321 .num_parents = 1,
1322 .ops = &clk_branch2_ops,
1323 .flags = CLK_SET_RATE_PARENT,
1324 },
1325 },
1326 };
1327
1328 static struct clk_branch mdss_hdmi_dp_ahb_clk = {
1329 .halt_reg = 0x230c,
1330 .clkr = {
1331 .enable_reg = 0x230c,
1332 .enable_mask = BIT(0),
1333 .hw.init = &(struct clk_init_data){
1334 .name = "mdss_hdmi_dp_ahb_clk",
1335 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1336 .num_parents = 1,
1337 .ops = &clk_branch2_ops,
1338 .flags = CLK_SET_RATE_PARENT,
1339 },
1340 },
1341 };
1342
1343 static struct clk_branch mdss_axi_clk = {
1344 .halt_reg = 0x2310,
1345 .clkr = {
1346 .enable_reg = 0x2310,
1347 .enable_mask = BIT(0),
1348 .hw.init = &(struct clk_init_data){
1349 .name = "mdss_axi_clk",
1350 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1351 .num_parents = 1,
1352 .ops = &clk_branch2_ops,
1353 },
1354 },
1355 };
1356
1357 static struct clk_branch mdss_pclk0_clk = {
1358 .halt_reg = 0x2314,
1359 .clkr = {
1360 .enable_reg = 0x2314,
1361 .enable_mask = BIT(0),
1362 .hw.init = &(struct clk_init_data){
1363 .name = "mdss_pclk0_clk",
1364 .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
1365 .num_parents = 1,
1366 .ops = &clk_branch2_ops,
1367 .flags = CLK_SET_RATE_PARENT,
1368 },
1369 },
1370 };
1371
1372 static struct clk_branch mdss_pclk1_clk = {
1373 .halt_reg = 0x2318,
1374 .clkr = {
1375 .enable_reg = 0x2318,
1376 .enable_mask = BIT(0),
1377 .hw.init = &(struct clk_init_data){
1378 .name = "mdss_pclk1_clk",
1379 .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
1380 .num_parents = 1,
1381 .ops = &clk_branch2_ops,
1382 .flags = CLK_SET_RATE_PARENT,
1383 },
1384 },
1385 };
1386
1387 static struct clk_branch mdss_mdp_clk = {
1388 .halt_reg = 0x231c,
1389 .clkr = {
1390 .enable_reg = 0x231c,
1391 .enable_mask = BIT(0),
1392 .hw.init = &(struct clk_init_data){
1393 .name = "mdss_mdp_clk",
1394 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1395 .num_parents = 1,
1396 .ops = &clk_branch2_ops,
1397 .flags = CLK_SET_RATE_PARENT,
1398 },
1399 },
1400 };
1401
1402 static struct clk_branch mdss_mdp_lut_clk = {
1403 .halt_reg = 0x2320,
1404 .clkr = {
1405 .enable_reg = 0x2320,
1406 .enable_mask = BIT(0),
1407 .hw.init = &(struct clk_init_data){
1408 .name = "mdss_mdp_lut_clk",
1409 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1410 .num_parents = 1,
1411 .ops = &clk_branch2_ops,
1412 .flags = CLK_SET_RATE_PARENT,
1413 },
1414 },
1415 };
1416
1417 static struct clk_branch mdss_extpclk_clk = {
1418 .halt_reg = 0x2324,
1419 .clkr = {
1420 .enable_reg = 0x2324,
1421 .enable_mask = BIT(0),
1422 .hw.init = &(struct clk_init_data){
1423 .name = "mdss_extpclk_clk",
1424 .parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
1425 .num_parents = 1,
1426 .ops = &clk_branch2_ops,
1427 .flags = CLK_SET_RATE_PARENT,
1428 },
1429 },
1430 };
1431
1432 static struct clk_branch mdss_vsync_clk = {
1433 .halt_reg = 0x2328,
1434 .clkr = {
1435 .enable_reg = 0x2328,
1436 .enable_mask = BIT(0),
1437 .hw.init = &(struct clk_init_data){
1438 .name = "mdss_vsync_clk",
1439 .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
1440 .num_parents = 1,
1441 .ops = &clk_branch2_ops,
1442 .flags = CLK_SET_RATE_PARENT,
1443 },
1444 },
1445 };
1446
1447 static struct clk_branch mdss_hdmi_clk = {
1448 .halt_reg = 0x2338,
1449 .clkr = {
1450 .enable_reg = 0x2338,
1451 .enable_mask = BIT(0),
1452 .hw.init = &(struct clk_init_data){
1453 .name = "mdss_hdmi_clk",
1454 .parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
1455 .num_parents = 1,
1456 .ops = &clk_branch2_ops,
1457 .flags = CLK_SET_RATE_PARENT,
1458 },
1459 },
1460 };
1461
1462 static struct clk_branch mdss_byte0_clk = {
1463 .halt_reg = 0x233c,
1464 .clkr = {
1465 .enable_reg = 0x233c,
1466 .enable_mask = BIT(0),
1467 .hw.init = &(struct clk_init_data){
1468 .name = "mdss_byte0_clk",
1469 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1470 .num_parents = 1,
1471 .ops = &clk_branch2_ops,
1472 .flags = CLK_SET_RATE_PARENT,
1473 },
1474 },
1475 };
1476
1477 static struct clk_branch mdss_byte1_clk = {
1478 .halt_reg = 0x2340,
1479 .clkr = {
1480 .enable_reg = 0x2340,
1481 .enable_mask = BIT(0),
1482 .hw.init = &(struct clk_init_data){
1483 .name = "mdss_byte1_clk",
1484 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1485 .num_parents = 1,
1486 .ops = &clk_branch2_ops,
1487 .flags = CLK_SET_RATE_PARENT,
1488 },
1489 },
1490 };
1491
1492 static struct clk_branch mdss_esc0_clk = {
1493 .halt_reg = 0x2344,
1494 .clkr = {
1495 .enable_reg = 0x2344,
1496 .enable_mask = BIT(0),
1497 .hw.init = &(struct clk_init_data){
1498 .name = "mdss_esc0_clk",
1499 .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
1500 .num_parents = 1,
1501 .ops = &clk_branch2_ops,
1502 .flags = CLK_SET_RATE_PARENT,
1503 },
1504 },
1505 };
1506
1507 static struct clk_branch mdss_esc1_clk = {
1508 .halt_reg = 0x2348,
1509 .clkr = {
1510 .enable_reg = 0x2348,
1511 .enable_mask = BIT(0),
1512 .hw.init = &(struct clk_init_data){
1513 .name = "mdss_esc1_clk",
1514 .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
1515 .num_parents = 1,
1516 .ops = &clk_branch2_ops,
1517 .flags = CLK_SET_RATE_PARENT,
1518 },
1519 },
1520 };
1521
1522 static struct clk_branch mdss_rot_clk = {
1523 .halt_reg = 0x2350,
1524 .clkr = {
1525 .enable_reg = 0x2350,
1526 .enable_mask = BIT(0),
1527 .hw.init = &(struct clk_init_data){
1528 .name = "mdss_rot_clk",
1529 .parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw },
1530 .num_parents = 1,
1531 .ops = &clk_branch2_ops,
1532 .flags = CLK_SET_RATE_PARENT,
1533 },
1534 },
1535 };
1536
1537 static struct clk_branch mdss_dp_link_clk = {
1538 .halt_reg = 0x2354,
1539 .clkr = {
1540 .enable_reg = 0x2354,
1541 .enable_mask = BIT(0),
1542 .hw.init = &(struct clk_init_data){
1543 .name = "mdss_dp_link_clk",
1544 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
1545 .num_parents = 1,
1546 .ops = &clk_branch2_ops,
1547 .flags = CLK_SET_RATE_PARENT,
1548 },
1549 },
1550 };
1551
1552 static struct clk_branch mdss_dp_link_intf_clk = {
1553 .halt_reg = 0x2358,
1554 .clkr = {
1555 .enable_reg = 0x2358,
1556 .enable_mask = BIT(0),
1557 .hw.init = &(struct clk_init_data){
1558 .name = "mdss_dp_link_intf_clk",
1559 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
1560 .num_parents = 1,
1561 .ops = &clk_branch2_ops,
1562 .flags = CLK_SET_RATE_PARENT,
1563 },
1564 },
1565 };
1566
1567 static struct clk_branch mdss_dp_crypto_clk = {
1568 .halt_reg = 0x235c,
1569 .clkr = {
1570 .enable_reg = 0x235c,
1571 .enable_mask = BIT(0),
1572 .hw.init = &(struct clk_init_data){
1573 .name = "mdss_dp_crypto_clk",
1574 .parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw },
1575 .num_parents = 1,
1576 .ops = &clk_branch2_ops,
1577 .flags = CLK_SET_RATE_PARENT,
1578 },
1579 },
1580 };
1581
1582 static struct clk_branch mdss_dp_pixel_clk = {
1583 .halt_reg = 0x2360,
1584 .clkr = {
1585 .enable_reg = 0x2360,
1586 .enable_mask = BIT(0),
1587 .hw.init = &(struct clk_init_data){
1588 .name = "mdss_dp_pixel_clk",
1589 .parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw },
1590 .num_parents = 1,
1591 .ops = &clk_branch2_ops,
1592 .flags = CLK_SET_RATE_PARENT,
1593 },
1594 },
1595 };
1596
1597 static struct clk_branch mdss_dp_aux_clk = {
1598 .halt_reg = 0x2364,
1599 .clkr = {
1600 .enable_reg = 0x2364,
1601 .enable_mask = BIT(0),
1602 .hw.init = &(struct clk_init_data){
1603 .name = "mdss_dp_aux_clk",
1604 .parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw },
1605 .num_parents = 1,
1606 .ops = &clk_branch2_ops,
1607 .flags = CLK_SET_RATE_PARENT,
1608 },
1609 },
1610 };
1611
1612 static struct clk_branch mdss_byte0_intf_clk = {
1613 .halt_reg = 0x2374,
1614 .clkr = {
1615 .enable_reg = 0x2374,
1616 .enable_mask = BIT(0),
1617 .hw.init = &(struct clk_init_data){
1618 .name = "mdss_byte0_intf_clk",
1619 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1620 .num_parents = 1,
1621 .ops = &clk_branch2_ops,
1622 .flags = CLK_SET_RATE_PARENT,
1623 },
1624 },
1625 };
1626
1627 static struct clk_branch mdss_byte1_intf_clk = {
1628 .halt_reg = 0x2378,
1629 .clkr = {
1630 .enable_reg = 0x2378,
1631 .enable_mask = BIT(0),
1632 .hw.init = &(struct clk_init_data){
1633 .name = "mdss_byte1_intf_clk",
1634 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1635 .num_parents = 1,
1636 .ops = &clk_branch2_ops,
1637 .flags = CLK_SET_RATE_PARENT,
1638 },
1639 },
1640 };
1641
1642 static struct clk_branch camss_csi0phytimer_clk = {
1643 .halt_reg = 0x3024,
1644 .clkr = {
1645 .enable_reg = 0x3024,
1646 .enable_mask = BIT(0),
1647 .hw.init = &(struct clk_init_data){
1648 .name = "camss_csi0phytimer_clk",
1649 .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1650 .num_parents = 1,
1651 .ops = &clk_branch2_ops,
1652 .flags = CLK_SET_RATE_PARENT,
1653 },
1654 },
1655 };
1656
1657 static struct clk_branch camss_csi1phytimer_clk = {
1658 .halt_reg = 0x3054,
1659 .clkr = {
1660 .enable_reg = 0x3054,
1661 .enable_mask = BIT(0),
1662 .hw.init = &(struct clk_init_data){
1663 .name = "camss_csi1phytimer_clk",
1664 .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1665 .num_parents = 1,
1666 .ops = &clk_branch2_ops,
1667 .flags = CLK_SET_RATE_PARENT,
1668 },
1669 },
1670 };
1671
1672 static struct clk_branch camss_csi2phytimer_clk = {
1673 .halt_reg = 0x3084,
1674 .clkr = {
1675 .enable_reg = 0x3084,
1676 .enable_mask = BIT(0),
1677 .hw.init = &(struct clk_init_data){
1678 .name = "camss_csi2phytimer_clk",
1679 .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1680 .num_parents = 1,
1681 .ops = &clk_branch2_ops,
1682 .flags = CLK_SET_RATE_PARENT,
1683 },
1684 },
1685 };
1686
1687 static struct clk_branch camss_csi0_clk = {
1688 .halt_reg = 0x30b4,
1689 .clkr = {
1690 .enable_reg = 0x30b4,
1691 .enable_mask = BIT(0),
1692 .hw.init = &(struct clk_init_data){
1693 .name = "camss_csi0_clk",
1694 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1695 .num_parents = 1,
1696 .ops = &clk_branch2_ops,
1697 .flags = CLK_SET_RATE_PARENT,
1698 },
1699 },
1700 };
1701
1702 static struct clk_branch camss_csi0_ahb_clk = {
1703 .halt_reg = 0x30bc,
1704 .clkr = {
1705 .enable_reg = 0x30bc,
1706 .enable_mask = BIT(0),
1707 .hw.init = &(struct clk_init_data){
1708 .name = "camss_csi0_ahb_clk",
1709 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1710 .num_parents = 1,
1711 .ops = &clk_branch2_ops,
1712 .flags = CLK_SET_RATE_PARENT,
1713 },
1714 },
1715 };
1716
1717 static struct clk_branch camss_csi0rdi_clk = {
1718 .halt_reg = 0x30d4,
1719 .clkr = {
1720 .enable_reg = 0x30d4,
1721 .enable_mask = BIT(0),
1722 .hw.init = &(struct clk_init_data){
1723 .name = "camss_csi0rdi_clk",
1724 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1725 .num_parents = 1,
1726 .ops = &clk_branch2_ops,
1727 .flags = CLK_SET_RATE_PARENT,
1728 },
1729 },
1730 };
1731
1732 static struct clk_branch camss_csi0pix_clk = {
1733 .halt_reg = 0x30e4,
1734 .clkr = {
1735 .enable_reg = 0x30e4,
1736 .enable_mask = BIT(0),
1737 .hw.init = &(struct clk_init_data){
1738 .name = "camss_csi0pix_clk",
1739 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1740 .num_parents = 1,
1741 .ops = &clk_branch2_ops,
1742 .flags = CLK_SET_RATE_PARENT,
1743 },
1744 },
1745 };
1746
1747 static struct clk_branch camss_csi1_clk = {
1748 .halt_reg = 0x3124,
1749 .clkr = {
1750 .enable_reg = 0x3124,
1751 .enable_mask = BIT(0),
1752 .hw.init = &(struct clk_init_data){
1753 .name = "camss_csi1_clk",
1754 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1755 .num_parents = 1,
1756 .ops = &clk_branch2_ops,
1757 .flags = CLK_SET_RATE_PARENT,
1758 },
1759 },
1760 };
1761
1762 static struct clk_branch camss_csi1_ahb_clk = {
1763 .halt_reg = 0x3128,
1764 .clkr = {
1765 .enable_reg = 0x3128,
1766 .enable_mask = BIT(0),
1767 .hw.init = &(struct clk_init_data){
1768 .name = "camss_csi1_ahb_clk",
1769 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1770 .num_parents = 1,
1771 .ops = &clk_branch2_ops,
1772 .flags = CLK_SET_RATE_PARENT,
1773 },
1774 },
1775 };
1776
1777 static struct clk_branch camss_csi1rdi_clk = {
1778 .halt_reg = 0x3144,
1779 .clkr = {
1780 .enable_reg = 0x3144,
1781 .enable_mask = BIT(0),
1782 .hw.init = &(struct clk_init_data){
1783 .name = "camss_csi1rdi_clk",
1784 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1785 .num_parents = 1,
1786 .ops = &clk_branch2_ops,
1787 .flags = CLK_SET_RATE_PARENT,
1788 },
1789 },
1790 };
1791
1792 static struct clk_branch camss_csi1pix_clk = {
1793 .halt_reg = 0x3154,
1794 .clkr = {
1795 .enable_reg = 0x3154,
1796 .enable_mask = BIT(0),
1797 .hw.init = &(struct clk_init_data){
1798 .name = "camss_csi1pix_clk",
1799 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1800 .num_parents = 1,
1801 .ops = &clk_branch2_ops,
1802 .flags = CLK_SET_RATE_PARENT,
1803 },
1804 },
1805 };
1806
1807 static struct clk_branch camss_csi2_clk = {
1808 .halt_reg = 0x3184,
1809 .clkr = {
1810 .enable_reg = 0x3184,
1811 .enable_mask = BIT(0),
1812 .hw.init = &(struct clk_init_data){
1813 .name = "camss_csi2_clk",
1814 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1815 .num_parents = 1,
1816 .ops = &clk_branch2_ops,
1817 .flags = CLK_SET_RATE_PARENT,
1818 },
1819 },
1820 };
1821
1822 static struct clk_branch camss_csi2_ahb_clk = {
1823 .halt_reg = 0x3188,
1824 .clkr = {
1825 .enable_reg = 0x3188,
1826 .enable_mask = BIT(0),
1827 .hw.init = &(struct clk_init_data){
1828 .name = "camss_csi2_ahb_clk",
1829 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1830 .num_parents = 1,
1831 .ops = &clk_branch2_ops,
1832 .flags = CLK_SET_RATE_PARENT,
1833 },
1834 },
1835 };
1836
1837 static struct clk_branch camss_csi2rdi_clk = {
1838 .halt_reg = 0x31a4,
1839 .clkr = {
1840 .enable_reg = 0x31a4,
1841 .enable_mask = BIT(0),
1842 .hw.init = &(struct clk_init_data){
1843 .name = "camss_csi2rdi_clk",
1844 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1845 .num_parents = 1,
1846 .ops = &clk_branch2_ops,
1847 .flags = CLK_SET_RATE_PARENT,
1848 },
1849 },
1850 };
1851
1852 static struct clk_branch camss_csi2pix_clk = {
1853 .halt_reg = 0x31b4,
1854 .clkr = {
1855 .enable_reg = 0x31b4,
1856 .enable_mask = BIT(0),
1857 .hw.init = &(struct clk_init_data){
1858 .name = "camss_csi2pix_clk",
1859 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1860 .num_parents = 1,
1861 .ops = &clk_branch2_ops,
1862 .flags = CLK_SET_RATE_PARENT,
1863 },
1864 },
1865 };
1866
1867 static struct clk_branch camss_csi3_clk = {
1868 .halt_reg = 0x31e4,
1869 .clkr = {
1870 .enable_reg = 0x31e4,
1871 .enable_mask = BIT(0),
1872 .hw.init = &(struct clk_init_data){
1873 .name = "camss_csi3_clk",
1874 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1875 .num_parents = 1,
1876 .ops = &clk_branch2_ops,
1877 .flags = CLK_SET_RATE_PARENT,
1878 },
1879 },
1880 };
1881
1882 static struct clk_branch camss_csi3_ahb_clk = {
1883 .halt_reg = 0x31e8,
1884 .clkr = {
1885 .enable_reg = 0x31e8,
1886 .enable_mask = BIT(0),
1887 .hw.init = &(struct clk_init_data){
1888 .name = "camss_csi3_ahb_clk",
1889 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1890 .num_parents = 1,
1891 .ops = &clk_branch2_ops,
1892 .flags = CLK_SET_RATE_PARENT,
1893 },
1894 },
1895 };
1896
1897 static struct clk_branch camss_csi3rdi_clk = {
1898 .halt_reg = 0x3204,
1899 .clkr = {
1900 .enable_reg = 0x3204,
1901 .enable_mask = BIT(0),
1902 .hw.init = &(struct clk_init_data){
1903 .name = "camss_csi3rdi_clk",
1904 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1905 .num_parents = 1,
1906 .ops = &clk_branch2_ops,
1907 .flags = CLK_SET_RATE_PARENT,
1908 },
1909 },
1910 };
1911
1912 static struct clk_branch camss_csi3pix_clk = {
1913 .halt_reg = 0x3214,
1914 .clkr = {
1915 .enable_reg = 0x3214,
1916 .enable_mask = BIT(0),
1917 .hw.init = &(struct clk_init_data){
1918 .name = "camss_csi3pix_clk",
1919 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1920 .num_parents = 1,
1921 .ops = &clk_branch2_ops,
1922 .flags = CLK_SET_RATE_PARENT,
1923 },
1924 },
1925 };
1926
1927 static struct clk_branch camss_ispif_ahb_clk = {
1928 .halt_reg = 0x3224,
1929 .clkr = {
1930 .enable_reg = 0x3224,
1931 .enable_mask = BIT(0),
1932 .hw.init = &(struct clk_init_data){
1933 .name = "camss_ispif_ahb_clk",
1934 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1935 .num_parents = 1,
1936 .ops = &clk_branch2_ops,
1937 .flags = CLK_SET_RATE_PARENT,
1938 },
1939 },
1940 };
1941
1942 static struct clk_branch camss_cci_clk = {
1943 .halt_reg = 0x3344,
1944 .clkr = {
1945 .enable_reg = 0x3344,
1946 .enable_mask = BIT(0),
1947 .hw.init = &(struct clk_init_data){
1948 .name = "camss_cci_clk",
1949 .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1950 .num_parents = 1,
1951 .ops = &clk_branch2_ops,
1952 .flags = CLK_SET_RATE_PARENT,
1953 },
1954 },
1955 };
1956
1957 static struct clk_branch camss_cci_ahb_clk = {
1958 .halt_reg = 0x3348,
1959 .clkr = {
1960 .enable_reg = 0x3348,
1961 .enable_mask = BIT(0),
1962 .hw.init = &(struct clk_init_data){
1963 .name = "camss_cci_ahb_clk",
1964 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1965 .num_parents = 1,
1966 .ops = &clk_branch2_ops,
1967 .flags = CLK_SET_RATE_PARENT,
1968 },
1969 },
1970 };
1971
1972 static struct clk_branch camss_mclk0_clk = {
1973 .halt_reg = 0x3384,
1974 .clkr = {
1975 .enable_reg = 0x3384,
1976 .enable_mask = BIT(0),
1977 .hw.init = &(struct clk_init_data){
1978 .name = "camss_mclk0_clk",
1979 .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1980 .num_parents = 1,
1981 .ops = &clk_branch2_ops,
1982 .flags = CLK_SET_RATE_PARENT,
1983 },
1984 },
1985 };
1986
1987 static struct clk_branch camss_mclk1_clk = {
1988 .halt_reg = 0x33b4,
1989 .clkr = {
1990 .enable_reg = 0x33b4,
1991 .enable_mask = BIT(0),
1992 .hw.init = &(struct clk_init_data){
1993 .name = "camss_mclk1_clk",
1994 .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
1995 .num_parents = 1,
1996 .ops = &clk_branch2_ops,
1997 .flags = CLK_SET_RATE_PARENT,
1998 },
1999 },
2000 };
2001
2002 static struct clk_branch camss_mclk2_clk = {
2003 .halt_reg = 0x33e4,
2004 .clkr = {
2005 .enable_reg = 0x33e4,
2006 .enable_mask = BIT(0),
2007 .hw.init = &(struct clk_init_data){
2008 .name = "camss_mclk2_clk",
2009 .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
2010 .num_parents = 1,
2011 .ops = &clk_branch2_ops,
2012 .flags = CLK_SET_RATE_PARENT,
2013 },
2014 },
2015 };
2016
2017 static struct clk_branch camss_mclk3_clk = {
2018 .halt_reg = 0x3414,
2019 .clkr = {
2020 .enable_reg = 0x3414,
2021 .enable_mask = BIT(0),
2022 .hw.init = &(struct clk_init_data){
2023 .name = "camss_mclk3_clk",
2024 .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
2025 .num_parents = 1,
2026 .ops = &clk_branch2_ops,
2027 .flags = CLK_SET_RATE_PARENT,
2028 },
2029 },
2030 };
2031
2032 static struct clk_branch camss_top_ahb_clk = {
2033 .halt_reg = 0x3484,
2034 .clkr = {
2035 .enable_reg = 0x3484,
2036 .enable_mask = BIT(0),
2037 .hw.init = &(struct clk_init_data){
2038 .name = "camss_top_ahb_clk",
2039 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2040 .num_parents = 1,
2041 .ops = &clk_branch2_ops,
2042 .flags = CLK_SET_RATE_PARENT,
2043 },
2044 },
2045 };
2046
2047 static struct clk_branch camss_ahb_clk = {
2048 .halt_reg = 0x348c,
2049 .clkr = {
2050 .enable_reg = 0x348c,
2051 .enable_mask = BIT(0),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "camss_ahb_clk",
2054 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2055 .num_parents = 1,
2056 .ops = &clk_branch2_ops,
2057 .flags = CLK_SET_RATE_PARENT,
2058 },
2059 },
2060 };
2061
2062 static struct clk_branch camss_micro_ahb_clk = {
2063 .halt_reg = 0x3494,
2064 .clkr = {
2065 .enable_reg = 0x3494,
2066 .enable_mask = BIT(0),
2067 .hw.init = &(struct clk_init_data){
2068 .name = "camss_micro_ahb_clk",
2069 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2070 .num_parents = 1,
2071 .ops = &clk_branch2_ops,
2072 .flags = CLK_SET_RATE_PARENT,
2073 },
2074 },
2075 };
2076
2077 static struct clk_branch camss_jpeg0_clk = {
2078 .halt_reg = 0x35a8,
2079 .clkr = {
2080 .enable_reg = 0x35a8,
2081 .enable_mask = BIT(0),
2082 .hw.init = &(struct clk_init_data){
2083 .name = "camss_jpeg0_clk",
2084 .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
2085 .num_parents = 1,
2086 .ops = &clk_branch2_ops,
2087 .flags = CLK_SET_RATE_PARENT,
2088 },
2089 },
2090 };
2091
2092 static struct clk_branch camss_jpeg_ahb_clk = {
2093 .halt_reg = 0x35b4,
2094 .clkr = {
2095 .enable_reg = 0x35b4,
2096 .enable_mask = BIT(0),
2097 .hw.init = &(struct clk_init_data){
2098 .name = "camss_jpeg_ahb_clk",
2099 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2100 .num_parents = 1,
2101 .ops = &clk_branch2_ops,
2102 .flags = CLK_SET_RATE_PARENT,
2103 },
2104 },
2105 };
2106
2107 static struct clk_branch camss_jpeg_axi_clk = {
2108 .halt_reg = 0x35b8,
2109 .clkr = {
2110 .enable_reg = 0x35b8,
2111 .enable_mask = BIT(0),
2112 .hw.init = &(struct clk_init_data){
2113 .name = "camss_jpeg_axi_clk",
2114 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2115 .num_parents = 1,
2116 .ops = &clk_branch2_ops,
2117 },
2118 },
2119 };
2120
2121 static struct clk_branch camss_vfe0_ahb_clk = {
2122 .halt_reg = 0x3668,
2123 .clkr = {
2124 .enable_reg = 0x3668,
2125 .enable_mask = BIT(0),
2126 .hw.init = &(struct clk_init_data){
2127 .name = "camss_vfe0_ahb_clk",
2128 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2129 .num_parents = 1,
2130 .ops = &clk_branch2_ops,
2131 .flags = CLK_SET_RATE_PARENT,
2132 },
2133 },
2134 };
2135
2136 static struct clk_branch camss_vfe1_ahb_clk = {
2137 .halt_reg = 0x3678,
2138 .clkr = {
2139 .enable_reg = 0x3678,
2140 .enable_mask = BIT(0),
2141 .hw.init = &(struct clk_init_data){
2142 .name = "camss_vfe1_ahb_clk",
2143 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2144 .num_parents = 1,
2145 .ops = &clk_branch2_ops,
2146 .flags = CLK_SET_RATE_PARENT,
2147 },
2148 },
2149 };
2150
2151 static struct clk_branch camss_vfe0_clk = {
2152 .halt_reg = 0x36a8,
2153 .clkr = {
2154 .enable_reg = 0x36a8,
2155 .enable_mask = BIT(0),
2156 .hw.init = &(struct clk_init_data){
2157 .name = "camss_vfe0_clk",
2158 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2159 .num_parents = 1,
2160 .ops = &clk_branch2_ops,
2161 .flags = CLK_SET_RATE_PARENT,
2162 },
2163 },
2164 };
2165
2166 static struct clk_branch camss_vfe1_clk = {
2167 .halt_reg = 0x36ac,
2168 .clkr = {
2169 .enable_reg = 0x36ac,
2170 .enable_mask = BIT(0),
2171 .hw.init = &(struct clk_init_data){
2172 .name = "camss_vfe1_clk",
2173 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2174 .num_parents = 1,
2175 .ops = &clk_branch2_ops,
2176 .flags = CLK_SET_RATE_PARENT,
2177 },
2178 },
2179 };
2180
2181 static struct clk_branch camss_cpp_clk = {
2182 .halt_reg = 0x36b0,
2183 .clkr = {
2184 .enable_reg = 0x36b0,
2185 .enable_mask = BIT(0),
2186 .hw.init = &(struct clk_init_data){
2187 .name = "camss_cpp_clk",
2188 .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
2189 .num_parents = 1,
2190 .ops = &clk_branch2_ops,
2191 .flags = CLK_SET_RATE_PARENT,
2192 },
2193 },
2194 };
2195
2196 static struct clk_branch camss_cpp_ahb_clk = {
2197 .halt_reg = 0x36b4,
2198 .clkr = {
2199 .enable_reg = 0x36b4,
2200 .enable_mask = BIT(0),
2201 .hw.init = &(struct clk_init_data){
2202 .name = "camss_cpp_ahb_clk",
2203 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2204 .num_parents = 1,
2205 .ops = &clk_branch2_ops,
2206 .flags = CLK_SET_RATE_PARENT,
2207 },
2208 },
2209 };
2210
2211 static struct clk_branch camss_vfe_vbif_ahb_clk = {
2212 .halt_reg = 0x36b8,
2213 .clkr = {
2214 .enable_reg = 0x36b8,
2215 .enable_mask = BIT(0),
2216 .hw.init = &(struct clk_init_data){
2217 .name = "camss_vfe_vbif_ahb_clk",
2218 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2219 .num_parents = 1,
2220 .ops = &clk_branch2_ops,
2221 .flags = CLK_SET_RATE_PARENT,
2222 },
2223 },
2224 };
2225
2226 static struct clk_branch camss_vfe_vbif_axi_clk = {
2227 .halt_reg = 0x36bc,
2228 .clkr = {
2229 .enable_reg = 0x36bc,
2230 .enable_mask = BIT(0),
2231 .hw.init = &(struct clk_init_data){
2232 .name = "camss_vfe_vbif_axi_clk",
2233 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2234 .num_parents = 1,
2235 .ops = &clk_branch2_ops,
2236 },
2237 },
2238 };
2239
2240 static struct clk_branch camss_cpp_axi_clk = {
2241 .halt_reg = 0x36c4,
2242 .clkr = {
2243 .enable_reg = 0x36c4,
2244 .enable_mask = BIT(0),
2245 .hw.init = &(struct clk_init_data){
2246 .name = "camss_cpp_axi_clk",
2247 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2248 .num_parents = 1,
2249 .ops = &clk_branch2_ops,
2250 },
2251 },
2252 };
2253
2254 static struct clk_branch camss_cpp_vbif_ahb_clk = {
2255 .halt_reg = 0x36c8,
2256 .clkr = {
2257 .enable_reg = 0x36c8,
2258 .enable_mask = BIT(0),
2259 .hw.init = &(struct clk_init_data){
2260 .name = "camss_cpp_vbif_ahb_clk",
2261 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2262 .num_parents = 1,
2263 .ops = &clk_branch2_ops,
2264 .flags = CLK_SET_RATE_PARENT,
2265 },
2266 },
2267 };
2268
2269 static struct clk_branch camss_csi_vfe0_clk = {
2270 .halt_reg = 0x3704,
2271 .clkr = {
2272 .enable_reg = 0x3704,
2273 .enable_mask = BIT(0),
2274 .hw.init = &(struct clk_init_data){
2275 .name = "camss_csi_vfe0_clk",
2276 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2277 .num_parents = 1,
2278 .ops = &clk_branch2_ops,
2279 .flags = CLK_SET_RATE_PARENT,
2280 },
2281 },
2282 };
2283
2284 static struct clk_branch camss_csi_vfe1_clk = {
2285 .halt_reg = 0x3714,
2286 .clkr = {
2287 .enable_reg = 0x3714,
2288 .enable_mask = BIT(0),
2289 .hw.init = &(struct clk_init_data){
2290 .name = "camss_csi_vfe1_clk",
2291 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2292 .num_parents = 1,
2293 .ops = &clk_branch2_ops,
2294 .flags = CLK_SET_RATE_PARENT,
2295 },
2296 },
2297 };
2298
2299 static struct clk_branch camss_vfe0_stream_clk = {
2300 .halt_reg = 0x3720,
2301 .clkr = {
2302 .enable_reg = 0x3720,
2303 .enable_mask = BIT(0),
2304 .hw.init = &(struct clk_init_data){
2305 .name = "camss_vfe0_stream_clk",
2306 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2307 .num_parents = 1,
2308 .ops = &clk_branch2_ops,
2309 .flags = CLK_SET_RATE_PARENT,
2310 },
2311 },
2312 };
2313
2314 static struct clk_branch camss_vfe1_stream_clk = {
2315 .halt_reg = 0x3724,
2316 .clkr = {
2317 .enable_reg = 0x3724,
2318 .enable_mask = BIT(0),
2319 .hw.init = &(struct clk_init_data){
2320 .name = "camss_vfe1_stream_clk",
2321 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2322 .num_parents = 1,
2323 .ops = &clk_branch2_ops,
2324 .flags = CLK_SET_RATE_PARENT,
2325 },
2326 },
2327 };
2328
2329 static struct clk_branch camss_cphy_csid0_clk = {
2330 .halt_reg = 0x3730,
2331 .clkr = {
2332 .enable_reg = 0x3730,
2333 .enable_mask = BIT(0),
2334 .hw.init = &(struct clk_init_data){
2335 .name = "camss_cphy_csid0_clk",
2336 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2337 .num_parents = 1,
2338 .ops = &clk_branch2_ops,
2339 .flags = CLK_SET_RATE_PARENT,
2340 },
2341 },
2342 };
2343
2344 static struct clk_branch camss_cphy_csid1_clk = {
2345 .halt_reg = 0x3734,
2346 .clkr = {
2347 .enable_reg = 0x3734,
2348 .enable_mask = BIT(0),
2349 .hw.init = &(struct clk_init_data){
2350 .name = "camss_cphy_csid1_clk",
2351 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2352 .num_parents = 1,
2353 .ops = &clk_branch2_ops,
2354 .flags = CLK_SET_RATE_PARENT,
2355 },
2356 },
2357 };
2358
2359 static struct clk_branch camss_cphy_csid2_clk = {
2360 .halt_reg = 0x3738,
2361 .clkr = {
2362 .enable_reg = 0x3738,
2363 .enable_mask = BIT(0),
2364 .hw.init = &(struct clk_init_data){
2365 .name = "camss_cphy_csid2_clk",
2366 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2367 .num_parents = 1,
2368 .ops = &clk_branch2_ops,
2369 .flags = CLK_SET_RATE_PARENT,
2370 },
2371 },
2372 };
2373
2374 static struct clk_branch camss_cphy_csid3_clk = {
2375 .halt_reg = 0x373c,
2376 .clkr = {
2377 .enable_reg = 0x373c,
2378 .enable_mask = BIT(0),
2379 .hw.init = &(struct clk_init_data){
2380 .name = "camss_cphy_csid3_clk",
2381 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2382 .num_parents = 1,
2383 .ops = &clk_branch2_ops,
2384 .flags = CLK_SET_RATE_PARENT,
2385 },
2386 },
2387 };
2388
2389 static struct clk_branch camss_csiphy0_clk = {
2390 .halt_reg = 0x3740,
2391 .clkr = {
2392 .enable_reg = 0x3740,
2393 .enable_mask = BIT(0),
2394 .hw.init = &(struct clk_init_data){
2395 .name = "camss_csiphy0_clk",
2396 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2397 .num_parents = 1,
2398 .ops = &clk_branch2_ops,
2399 .flags = CLK_SET_RATE_PARENT,
2400 },
2401 },
2402 };
2403
2404 static struct clk_branch camss_csiphy1_clk = {
2405 .halt_reg = 0x3744,
2406 .clkr = {
2407 .enable_reg = 0x3744,
2408 .enable_mask = BIT(0),
2409 .hw.init = &(struct clk_init_data){
2410 .name = "camss_csiphy1_clk",
2411 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2412 .num_parents = 1,
2413 .ops = &clk_branch2_ops,
2414 .flags = CLK_SET_RATE_PARENT,
2415 },
2416 },
2417 };
2418
2419 static struct clk_branch camss_csiphy2_clk = {
2420 .halt_reg = 0x3748,
2421 .clkr = {
2422 .enable_reg = 0x3748,
2423 .enable_mask = BIT(0),
2424 .hw.init = &(struct clk_init_data){
2425 .name = "camss_csiphy2_clk",
2426 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2427 .num_parents = 1,
2428 .ops = &clk_branch2_ops,
2429 .flags = CLK_SET_RATE_PARENT,
2430 },
2431 },
2432 };
2433
2434 static struct clk_branch fd_core_clk = {
2435 .halt_reg = 0x3b68,
2436 .clkr = {
2437 .enable_reg = 0x3b68,
2438 .enable_mask = BIT(0),
2439 .hw.init = &(struct clk_init_data){
2440 .name = "fd_core_clk",
2441 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
2442 .num_parents = 1,
2443 .ops = &clk_branch2_ops,
2444 .flags = CLK_SET_RATE_PARENT,
2445 },
2446 },
2447 };
2448
2449 static struct clk_branch fd_core_uar_clk = {
2450 .halt_reg = 0x3b6c,
2451 .clkr = {
2452 .enable_reg = 0x3b6c,
2453 .enable_mask = BIT(0),
2454 .hw.init = &(struct clk_init_data){
2455 .name = "fd_core_uar_clk",
2456 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
2457 .num_parents = 1,
2458 .ops = &clk_branch2_ops,
2459 .flags = CLK_SET_RATE_PARENT,
2460 },
2461 },
2462 };
2463
2464 static struct clk_branch fd_ahb_clk = {
2465 .halt_reg = 0x3b74,
2466 .clkr = {
2467 .enable_reg = 0x3b74,
2468 .enable_mask = BIT(0),
2469 .hw.init = &(struct clk_init_data){
2470 .name = "fd_ahb_clk",
2471 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2472 .num_parents = 1,
2473 .ops = &clk_branch2_ops,
2474 .flags = CLK_SET_RATE_PARENT,
2475 },
2476 },
2477 };
2478
2479 static struct clk_branch mnoc_ahb_clk = {
2480 .halt_reg = 0x5024,
2481 .clkr = {
2482 .enable_reg = 0x5024,
2483 .enable_mask = BIT(0),
2484 .hw.init = &(struct clk_init_data){
2485 .name = "mnoc_ahb_clk",
2486 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2487 .num_parents = 1,
2488 .ops = &clk_branch2_ops,
2489 .flags = CLK_SET_RATE_PARENT,
2490 },
2491 },
2492 };
2493
2494 static struct clk_branch bimc_smmu_ahb_clk = {
2495 .halt_reg = 0xe004,
2496 .hwcg_reg = 0xe004,
2497 .hwcg_bit = 1,
2498 .clkr = {
2499 .enable_reg = 0xe004,
2500 .enable_mask = BIT(0),
2501 .hw.init = &(struct clk_init_data){
2502 .name = "bimc_smmu_ahb_clk",
2503 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2504 .num_parents = 1,
2505 .ops = &clk_branch2_ops,
2506 .flags = CLK_SET_RATE_PARENT,
2507 },
2508 },
2509 };
2510
2511 static struct clk_branch bimc_smmu_axi_clk = {
2512 .halt_reg = 0xe008,
2513 .hwcg_reg = 0xe008,
2514 .hwcg_bit = 1,
2515 .clkr = {
2516 .enable_reg = 0xe008,
2517 .enable_mask = BIT(0),
2518 .hw.init = &(struct clk_init_data){
2519 .name = "bimc_smmu_axi_clk",
2520 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2521 .num_parents = 1,
2522 .ops = &clk_branch2_ops,
2523 },
2524 },
2525 };
2526
2527 static struct clk_branch mnoc_maxi_clk = {
2528 .halt_reg = 0xf004,
2529 .clkr = {
2530 .enable_reg = 0xf004,
2531 .enable_mask = BIT(0),
2532 .hw.init = &(struct clk_init_data){
2533 .name = "mnoc_maxi_clk",
2534 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
2535 .num_parents = 1,
2536 .ops = &clk_branch2_ops,
2537 .flags = CLK_SET_RATE_PARENT,
2538 },
2539 },
2540 };
2541
2542 static struct clk_branch vmem_maxi_clk = {
2543 .halt_reg = 0xf064,
2544 .clkr = {
2545 .enable_reg = 0xf064,
2546 .enable_mask = BIT(0),
2547 .hw.init = &(struct clk_init_data){
2548 .name = "vmem_maxi_clk",
2549 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
2550 .num_parents = 1,
2551 .ops = &clk_branch2_ops,
2552 .flags = CLK_SET_RATE_PARENT,
2553 },
2554 },
2555 };
2556
2557 static struct clk_branch vmem_ahb_clk = {
2558 .halt_reg = 0xf068,
2559 .clkr = {
2560 .enable_reg = 0xf068,
2561 .enable_mask = BIT(0),
2562 .hw.init = &(struct clk_init_data){
2563 .name = "vmem_ahb_clk",
2564 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2565 .num_parents = 1,
2566 .ops = &clk_branch2_ops,
2567 .flags = CLK_SET_RATE_PARENT,
2568 },
2569 },
2570 };
2571
2572 static struct clk_hw *mmcc_msm8998_hws[] = {
2573 &gpll0_div.hw,
2574 };
2575
2576 static struct gdsc video_top_gdsc = {
2577 .gdscr = 0x1024,
2578 .pd = {
2579 .name = "video_top",
2580 },
2581 .pwrsts = PWRSTS_OFF_ON,
2582 };
2583
2584 static struct gdsc video_subcore0_gdsc = {
2585 .gdscr = 0x1040,
2586 .pd = {
2587 .name = "video_subcore0",
2588 },
2589 .parent = &video_top_gdsc.pd,
2590 .pwrsts = PWRSTS_OFF_ON,
2591 };
2592
2593 static struct gdsc video_subcore1_gdsc = {
2594 .gdscr = 0x1044,
2595 .pd = {
2596 .name = "video_subcore1",
2597 },
2598 .parent = &video_top_gdsc.pd,
2599 .pwrsts = PWRSTS_OFF_ON,
2600 };
2601
2602 static struct gdsc mdss_gdsc = {
2603 .gdscr = 0x2304,
2604 .cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 },
2605 .cxc_count = 4,
2606 .pd = {
2607 .name = "mdss",
2608 },
2609 .pwrsts = PWRSTS_OFF_ON,
2610 };
2611
2612 static struct gdsc camss_top_gdsc = {
2613 .gdscr = 0x34a0,
2614 .cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494,
2615 0x35a8, 0x3868 },
2616 .cxc_count = 7,
2617 .pd = {
2618 .name = "camss_top",
2619 },
2620 .pwrsts = PWRSTS_OFF_ON,
2621 };
2622
2623 static struct gdsc camss_vfe0_gdsc = {
2624 .gdscr = 0x3664,
2625 .pd = {
2626 .name = "camss_vfe0",
2627 },
2628 .parent = &camss_top_gdsc.pd,
2629 .pwrsts = PWRSTS_OFF_ON,
2630 };
2631
2632 static struct gdsc camss_vfe1_gdsc = {
2633 .gdscr = 0x3674,
2634 .pd = {
2635 .name = "camss_vfe1_gdsc",
2636 },
2637 .parent = &camss_top_gdsc.pd,
2638 .pwrsts = PWRSTS_OFF_ON,
2639 };
2640
2641 static struct gdsc camss_cpp_gdsc = {
2642 .gdscr = 0x36d4,
2643 .pd = {
2644 .name = "camss_cpp",
2645 },
2646 .parent = &camss_top_gdsc.pd,
2647 .pwrsts = PWRSTS_OFF_ON,
2648 };
2649
2650 static struct gdsc bimc_smmu_gdsc = {
2651 .gdscr = 0xe020,
2652 .gds_hw_ctrl = 0xe024,
2653 .pd = {
2654 .name = "bimc_smmu",
2655 },
2656 .pwrsts = PWRSTS_OFF_ON,
2657 .flags = HW_CTRL | ALWAYS_ON,
2658 };
2659
2660 static struct clk_regmap *mmcc_msm8998_clocks[] = {
2661 [MMPLL0] = &mmpll0.clkr,
2662 [MMPLL0_OUT_EVEN] = &mmpll0_out_even.clkr,
2663 [MMPLL1] = &mmpll1.clkr,
2664 [MMPLL1_OUT_EVEN] = &mmpll1_out_even.clkr,
2665 [MMPLL3] = &mmpll3.clkr,
2666 [MMPLL3_OUT_EVEN] = &mmpll3_out_even.clkr,
2667 [MMPLL4] = &mmpll4.clkr,
2668 [MMPLL4_OUT_EVEN] = &mmpll4_out_even.clkr,
2669 [MMPLL5] = &mmpll5.clkr,
2670 [MMPLL5_OUT_EVEN] = &mmpll5_out_even.clkr,
2671 [MMPLL6] = &mmpll6.clkr,
2672 [MMPLL6_OUT_EVEN] = &mmpll6_out_even.clkr,
2673 [MMPLL7] = &mmpll7.clkr,
2674 [MMPLL7_OUT_EVEN] = &mmpll7_out_even.clkr,
2675 [MMPLL10] = &mmpll10.clkr,
2676 [MMPLL10_OUT_EVEN] = &mmpll10_out_even.clkr,
2677 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2678 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2679 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2680 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2681 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2682 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2683 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2684 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2685 [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr,
2686 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2687 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2688 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2689 [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr,
2690 [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr,
2691 [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr,
2692 [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr,
2693 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2694 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2695 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2696 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
2697 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2698 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2699 [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
2700 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2701 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2702 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2703 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2704 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2705 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2706 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
2707 [AXI_CLK_SRC] = &axi_clk_src.clkr,
2708 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2709 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2710 [ROT_CLK_SRC] = &rot_clk_src.clkr,
2711 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
2712 [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
2713 [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
2714 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2715 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2716 [MISC_AHB_CLK] = &misc_ahb_clk.clkr,
2717 [VIDEO_CORE_CLK] = &video_core_clk.clkr,
2718 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
2719 [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
2720 [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
2721 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
2722 [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
2723 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2724 [MDSS_HDMI_DP_AHB_CLK] = &mdss_hdmi_dp_ahb_clk.clkr,
2725 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2726 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2727 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2728 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2729 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2730 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2731 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2732 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2733 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2734 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2735 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2736 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2737 [MDSS_ROT_CLK] = &mdss_rot_clk.clkr,
2738 [MDSS_DP_LINK_CLK] = &mdss_dp_link_clk.clkr,
2739 [MDSS_DP_LINK_INTF_CLK] = &mdss_dp_link_intf_clk.clkr,
2740 [MDSS_DP_CRYPTO_CLK] = &mdss_dp_crypto_clk.clkr,
2741 [MDSS_DP_PIXEL_CLK] = &mdss_dp_pixel_clk.clkr,
2742 [MDSS_DP_AUX_CLK] = &mdss_dp_aux_clk.clkr,
2743 [MDSS_BYTE0_INTF_CLK] = &mdss_byte0_intf_clk.clkr,
2744 [MDSS_BYTE1_INTF_CLK] = &mdss_byte1_intf_clk.clkr,
2745 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
2746 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
2747 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
2748 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2749 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2750 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2751 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2752 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2753 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2754 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2755 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2756 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2757 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2758 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2759 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2760 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2761 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2762 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2763 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2764 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2765 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
2766 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
2767 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2768 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2769 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2770 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2771 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2772 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2773 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2774 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
2775 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
2776 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
2777 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
2778 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
2779 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
2780 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
2781 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
2782 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
2783 [CAMSS_VFE_VBIF_AHB_CLK] = &camss_vfe_vbif_ahb_clk.clkr,
2784 [CAMSS_VFE_VBIF_AXI_CLK] = &camss_vfe_vbif_axi_clk.clkr,
2785 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
2786 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
2787 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2788 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2789 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
2790 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
2791 [CAMSS_CPHY_CSID0_CLK] = &camss_cphy_csid0_clk.clkr,
2792 [CAMSS_CPHY_CSID1_CLK] = &camss_cphy_csid1_clk.clkr,
2793 [CAMSS_CPHY_CSID2_CLK] = &camss_cphy_csid2_clk.clkr,
2794 [CAMSS_CPHY_CSID3_CLK] = &camss_cphy_csid3_clk.clkr,
2795 [CAMSS_CSIPHY0_CLK] = &camss_csiphy0_clk.clkr,
2796 [CAMSS_CSIPHY1_CLK] = &camss_csiphy1_clk.clkr,
2797 [CAMSS_CSIPHY2_CLK] = &camss_csiphy2_clk.clkr,
2798 [FD_CORE_CLK] = &fd_core_clk.clkr,
2799 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
2800 [FD_AHB_CLK] = &fd_ahb_clk.clkr,
2801 [MNOC_AHB_CLK] = &mnoc_ahb_clk.clkr,
2802 [BIMC_SMMU_AHB_CLK] = &bimc_smmu_ahb_clk.clkr,
2803 [BIMC_SMMU_AXI_CLK] = &bimc_smmu_axi_clk.clkr,
2804 [MNOC_MAXI_CLK] = &mnoc_maxi_clk.clkr,
2805 [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
2806 [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
2807 };
2808
2809 static struct gdsc *mmcc_msm8998_gdscs[] = {
2810 [VIDEO_TOP_GDSC] = &video_top_gdsc,
2811 [VIDEO_SUBCORE0_GDSC] = &video_subcore0_gdsc,
2812 [VIDEO_SUBCORE1_GDSC] = &video_subcore1_gdsc,
2813 [MDSS_GDSC] = &mdss_gdsc,
2814 [CAMSS_TOP_GDSC] = &camss_top_gdsc,
2815 [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
2816 [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
2817 [CAMSS_CPP_GDSC] = &camss_cpp_gdsc,
2818 [BIMC_SMMU_GDSC] = &bimc_smmu_gdsc,
2819 };
2820
2821 static const struct qcom_reset_map mmcc_msm8998_resets[] = {
2822 [SPDM_BCR] = { 0x200 },
2823 [SPDM_RM_BCR] = { 0x300 },
2824 [MISC_BCR] = { 0x320 },
2825 [VIDEO_TOP_BCR] = { 0x1020 },
2826 [THROTTLE_VIDEO_BCR] = { 0x1180 },
2827 [MDSS_BCR] = { 0x2300 },
2828 [THROTTLE_MDSS_BCR] = { 0x2460 },
2829 [CAMSS_PHY0_BCR] = { 0x3020 },
2830 [CAMSS_PHY1_BCR] = { 0x3050 },
2831 [CAMSS_PHY2_BCR] = { 0x3080 },
2832 [CAMSS_CSI0_BCR] = { 0x30b0 },
2833 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
2834 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
2835 [CAMSS_CSI1_BCR] = { 0x3120 },
2836 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
2837 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
2838 [CAMSS_CSI2_BCR] = { 0x3180 },
2839 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
2840 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
2841 [CAMSS_CSI3_BCR] = { 0x31e0 },
2842 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
2843 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
2844 [CAMSS_ISPIF_BCR] = { 0x3220 },
2845 [CAMSS_CCI_BCR] = { 0x3340 },
2846 [CAMSS_TOP_BCR] = { 0x3480 },
2847 [CAMSS_AHB_BCR] = { 0x3488 },
2848 [CAMSS_MICRO_BCR] = { 0x3490 },
2849 [CAMSS_JPEG_BCR] = { 0x35a0 },
2850 [CAMSS_VFE0_BCR] = { 0x3660 },
2851 [CAMSS_VFE1_BCR] = { 0x3670 },
2852 [CAMSS_VFE_VBIF_BCR] = { 0x36a0 },
2853 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
2854 [CAMSS_CPP_BCR] = { 0x36d0 },
2855 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
2856 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
2857 [CAMSS_FD_BCR] = { 0x3b60 },
2858 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
2859 [MNOCAHB_BCR] = { 0x5020 },
2860 [MNOCAXI_BCR] = { 0xd020 },
2861 [BMIC_SMMU_BCR] = { 0xe000 },
2862 [MNOC_MAXI_BCR] = { 0xf000 },
2863 [VMEM_BCR] = { 0xf060 },
2864 [BTO_BCR] = { 0x10004 },
2865 };
2866
2867 static const struct regmap_config mmcc_msm8998_regmap_config = {
2868 .reg_bits = 32,
2869 .reg_stride = 4,
2870 .val_bits = 32,
2871 .max_register = 0x10004,
2872 .fast_io = true,
2873 };
2874
2875 static const struct qcom_cc_desc mmcc_msm8998_desc = {
2876 .config = &mmcc_msm8998_regmap_config,
2877 .clks = mmcc_msm8998_clocks,
2878 .num_clks = ARRAY_SIZE(mmcc_msm8998_clocks),
2879 .resets = mmcc_msm8998_resets,
2880 .num_resets = ARRAY_SIZE(mmcc_msm8998_resets),
2881 .gdscs = mmcc_msm8998_gdscs,
2882 .num_gdscs = ARRAY_SIZE(mmcc_msm8998_gdscs),
2883 .clk_hws = mmcc_msm8998_hws,
2884 .num_clk_hws = ARRAY_SIZE(mmcc_msm8998_hws),
2885 };
2886
2887 static const struct of_device_id mmcc_msm8998_match_table[] = {
2888 { .compatible = "qcom,mmcc-msm8998" },
2889 { }
2890 };
2891 MODULE_DEVICE_TABLE(of, mmcc_msm8998_match_table);
2892
mmcc_msm8998_probe(struct platform_device * pdev)2893 static int mmcc_msm8998_probe(struct platform_device *pdev)
2894 {
2895 struct regmap *regmap;
2896
2897 regmap = qcom_cc_map(pdev, &mmcc_msm8998_desc);
2898 if (IS_ERR(regmap))
2899 return PTR_ERR(regmap);
2900
2901 return qcom_cc_really_probe(pdev, &mmcc_msm8998_desc, regmap);
2902 }
2903
2904 static struct platform_driver mmcc_msm8998_driver = {
2905 .probe = mmcc_msm8998_probe,
2906 .driver = {
2907 .name = "mmcc-msm8998",
2908 .of_match_table = mmcc_msm8998_match_table,
2909 },
2910 };
2911 module_platform_driver(mmcc_msm8998_driver);
2912
2913 MODULE_DESCRIPTION("QCOM MMCC MSM8998 Driver");
2914 MODULE_LICENSE("GPL v2");
2915
